Re: [PATCH 1/1] target/riscv: Support Zama16b extension

Zhiwei, On 5/22/24 06:13, LIU Zhiwei wrote: Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more

Re: [PATCH v2 1/3] hw/riscv/virt: Add memory hotplugging and virtio-md-pci support

On 5/27/24 09:03, Björn Töpel wrote: David Hildenbrand writes: On 24.05.24 15:14, Daniel Henrique Barboza wrote: On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices (virtio-mem/virtio-pmem) allows for dynamic resizing of virtual machine memory

Re: [PATCH v6 0/3] Support RISC-V IOPMP

correspond registers Fix iopmp_write for ENTRY_ADDRH and ENTRYLCK_L - Refine coding style (Daniel Henrique Barboza) Thanks, Ethan Chen Ethan Chen (3): hw/core: Add config stream Add RISC-V IOPMP support hw/riscv/virt: Add IOPMP support docs/system/riscv/virt.rst

Re: [PATCH v1 4/4] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG

On 5/26/24 23:19, Chao Du wrote: To enable the KVM GUEST DEBUG for RISC-V at QEMU side. Signed-off-by: Chao Du --- Reviewed-by: Daniel Henrique Barboza configs/targets/riscv64-softmmu.mak | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/targets/riscv64-softmmu.mak b

Re: [PATCH v1 2/4] target/riscv/kvm: implement kvm_arch_update_guest_debug()

On 5/26/24 23:19, Chao Du wrote: Set the control flag when there are active breakpoints. This will help KVM to know the status in the userspace. Signed-off-by: Chao Du --- Reviewed-by: Daniel Henrique Barboza target/riscv/kvm/kvm-cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1

Re: [PATCH v1 3/4] target/riscv/kvm: handle the exit with debug reason

On 5/26/24 23:19, Chao Du wrote: If the breakpoint belongs to the userspace then set the ret value. Signed-off-by: Chao Du --- Reviewed-by: Daniel Henrique Barboza target/riscv/kvm/kvm-cpu.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/kvm

Re: [PATCH v1 1/4] target/riscv/kvm: add software breakpoints support

, and will be implemented later. Signed-off-by: Chao Du --- Reviewed-by: Daniel Henrique Barboza accel/kvm/kvm-all.c| 8 ++-- include/sysemu/kvm.h | 6 ++- target/arm/kvm.c | 6 ++- target/i386/kvm/kvm.c | 6 ++- target/mips/kvm.c | 6 ++- target/ppc

Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

with the patch files or any source file in particular, e.g.: $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c Palmer Dabbelt (supporter:RISC-V TCG CPUs) Alistair Francis (supporter:RISC-V TCG CPUs) Bin Meng (supporter:RISC-V TCG CPUs) Weiwei Li (reviewer:RISC-V TCG CPUs) Daniel Henrique Barboza

Re: [PATCH 0/6] target/riscv: Support Zabha extension

On 5/25/24 21:37, LIU Zhiwei wrote: On 2024/5/24 19:44, Daniel Henrique Barboza wrote: Hi Zhiwei! On 5/23/24 09:40, LIU Zhiwei wrote: Zabha adds support AMO operations for byte and half word. If zacas has been implemented, zabha also adds support amocas.b and amocas.h. More details

Re: [PATCH v2 1/3] hw/riscv/virt: Add memory hotplugging and virtio-md-pci support

On 5/24/24 12:02, David Hildenbrand wrote: On 24.05.24 15:14, Daniel Henrique Barboza wrote: On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices (virtio-mem/virtio-pmem) allows for dynamic resizing of virtual machine memory, and requires proper hotplugging

Re: [PATCH v2 1/3] hw/riscv/virt: Add memory hotplugging and virtio-md-pci support

On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices (virtio-mem/virtio-pmem) allows for dynamic resizing of virtual machine memory, and requires proper hotplugging (add/remove) support to work. Add device memory support for RISC-V "virt" machine, and enable

Re: [PATCH 0/6] target/riscv: Support Zabha extension

Hi Zhiwei! On 5/23/24 09:40, LIU Zhiwei wrote: Zabha adds support AMO operations for byte and half word. If zacas has been implemented, zabha also adds support amocas.b and amocas.h. More details is on the specification here: https://github.com/riscv/riscv-zabha The implemenation of zabha

Re: [PATCH 5/6] target/riscv: Enable zabha for max cpu

On 5/23/24 09:40, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 21d4e36405..9ec03a1edc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,7 @@

Re: [PATCH 1/1] target/riscv: Support Zama16b extension

On 5/22/24 06:13, LIU Zhiwei wrote: Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than

Re: [PATCH 3/4] target/riscv: Add zcmop extension

On 5/22/24 03:29, LIU Zhiwei wrote: Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n

Re: [PATCH 1/4] target/riscv: Add zimop extension

On 5/22/24 03:29, LIU Zhiwei wrote: Zimop extension defines an encoding space for 40 MOPs.The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an

Re: [PATCH v2 3/3] hw/riscv/virt: Add ACPI GED and PC-DIMM MHP support

On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Add ACPI GED for the RISC-V "virt" machine, and wire up PC-DIMM memory hotplugging support. Heavily based/copied from hw/arm/virt.c. Signed-off-by: Björn Töpel --- hw/riscv/Kconfig | 3 ++ hw/riscv/virt-acpi-build.c |

Re: [PATCH v2 1/3] hw/riscv/virt: Add memory hotplugging and virtio-md-pci support

On 5/21/24 07:56, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices (virtio-mem/virtio-pmem) allows for dynamic resizing of virtual machine memory, and requires proper hotplugging (add/remove) support to work. Add device memory support for RISC-V "virt" machine, and enable

[PATCH v3 12/13] hw/riscv/riscv-iommu: Add another irq for mrif notifications

From: Andrew Jones And add mrif notification trace. Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iommu-pci.c | 2 +- hw/riscv/riscv-iommu.c | 1 + hw/riscv/trace-events | 1 + 3 files changed, 3 insertions(+), 1

[PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h

a linux-header we would import instead of keeping our own. The Linux implementation isn't upstream yet so for now we'll have to manage riscv-iommu-bits.h. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iommu-bits.h | 347

[PATCH v3 11/13] hw/riscv/riscv-iommu: add DBG support

From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided for it. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu-bits.h | 17

[PATCH v3 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

elements, although we don't support it yet. We'll introduce them next. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iommu.c | 189 - hw/riscv/riscv-iommu.h | 2 + 2 files changed, 187

[PATCH v3 03/13] hw/riscv: add RISC-V IOMMU base emulation

Henrique Barboza --- hw/riscv/Kconfig |4 + hw/riscv/meson.build |1 + hw/riscv/riscv-iommu.c | 1602 ++ hw/riscv/riscv-iommu.h | 141 hw/riscv/trace-events| 11 + hw/riscv/trace.h |1 + include/hw/riscv/iommu.h | 36

[PATCH v3 06/13] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/virt.c | 33

[PATCH v3 05/13] hw/riscv: add riscv-iommu-pci reference device

From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza --- hw/riscv/meson.build |

[PATCH v3 10/13] hw/riscv/riscv-iommu: add ATS support

From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza --- hw/riscv

[PATCH v3 01/13] exec/memtxattr: add process identifier to the transaction attributes

From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-by: Tomasz Jeznach Reviewed-by: Frank Chang ---

[PATCH v3 09/13] hw/riscv/riscv-iommu: add s-stage and g-stage support

-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu-bits.h | 11 ++ hw/riscv/riscv-iommu.c | 331 +++- hw/riscv/riscv-iommu.h | 2 + 3 files changed, 336 insertions(+), 8 deletions(-) diff --git a/hw/riscv/riscv-iommu-bits.h b

[PATCH v3 13/13] qtest/riscv-iommu-test: add init queues test

itializing the IOMMU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- tests/qtest/libqos/riscv-iommu.h | 29 +++ tests/qtest/riscv-iommu-test.c | 141 +++ 2 files changed, 170 insertions(+) diff --git a/tests/qtest/libqos/riscv-iommu.h b/tests/qt

[PATCH v3 07/13] test/qtest: add riscv-iommu-pci tests

: a PCI sanity check and a reset state register test. The reset test was taken from the RISC-V IOMMU spec chapter 5.2, "Reset behavior". More tests will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- tests/qtest/libqos/meson.build | 4 ++ tests/qt

[PATCH v3 04/13] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

kind enough to give us a PCI ID for the RISC-V IOMMU PCI reference device. Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID. [1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 Cc: Gerd Hoffmann Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang

[PATCH v3 00/13] riscv: QEMU RISC-V IOMMU Support

tps://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarb...@ventanamicro.com/ [2] https://github.com/vlsunil/qemu/commits/acpi_rimt_poc_v1/ Andrew Jones (1): hw/riscv/riscv-iommu: Add another irq for mrif notifications Daniel Henrique Barboza (3): pci-ids.rst: add Red Hat pci-id for RISC-

Re: [PATCH v2 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

d IRQ filtering support.") Signed-off-by: Rajnesh Kanwal --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu_bits.h | 3 ++- target/riscv/csr.c | 9 - 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bit

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

On 5/21/24 07:52, Frank Chang wrote: Hi Daniel, On Tue, May 21, 2024 at 12:17 AM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote: Hi Frank, On 5/16/24 04:13, Frank Chang wrote: > On Mon, May 13, 2024 at 8:37 PM Daniel Henrique Barboza mai

Re: [PATCH] hw/riscv/virt: Add hotplugging and virtio-md-pci support

On 5/20/24 15:51, Björn Töpel wrote: Daniel/David, Daniel Henrique Barboza writes: On 5/18/24 16:50, David Hildenbrand wrote: Hi, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fdb66052587..16c2bdbfe6b6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -53,6 +53,8

Re: [PATCH] hw/riscv/virt: Add hotplugging and virtio-md-pci support

On 5/20/24 15:33, Björn Töpel wrote: Daniel, Thanks for taking a look! Daniel Henrique Barboza writes: Hi Björj, On 5/14/24 08:06, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices allows for dynamic resizing of virtual machine memory, and requires proper hotplugging

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

On 5/10/24 07:47, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年5月8日 週三 下午8:42寫道： On 5/7/24 12:44, Peter Maydell wrote: On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza wrote: Hi, In this RFC I want to check with Gerd and others if it's ok to add a PCI id

Re: [PATCH v2 00/15] riscv: QEMU RISC-V IOMMU Support

in the reviews! I'll do some last changes in the riscv-iommu-pci device, and check if we have any DT changes that happened that we need to sync up. The plan is to send v3 in the next couple of days. Let's see how it goes. Thanks, Daniel Regards, Frank Chang Daniel Henrique Barboza 於 2024年3月8日 週五 上

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Hi Frank, On 5/16/24 04:13, Frank Chang wrote: On Mon, May 13, 2024 at 8:37 PM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote: Hi Frank, On 5/8/24 08:15, Daniel Henrique Barboza wrote: > Hi Frank, > > I'll reply with that I've don

Re: [PATCH] hw/riscv/virt: Add hotplugging and virtio-md-pci support

On 5/18/24 16:50, David Hildenbrand wrote: Hi, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fdb66052587..16c2bdbfe6b6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -53,6 +53,8 @@    #include "hw/pci-host/gpex.h"    #include "hw/display/ramfb.h"    #include

Re: [PATCH] hw/riscv/virt: Add hotplugging and virtio-md-pci support

Hi Björj, On 5/14/24 08:06, Björn Töpel wrote: From: Björn Töpel Virtio-based memory devices allows for dynamic resizing of virtual machine memory, and requires proper hotplugging (add/remove) support to work. Enable virtio-md-pci with the corresponding missing hotplugging callbacks for the

Re: [PATCH] dias/riscv: Decode all of the pmpcfg and pmpaddr CSRs

"pmpcfg0"; Hmm it seems that the code for 'pmpcfg3' was incorrect from the get go. Perhaps it's worth adding a: Fixes: ea10325917 ("RISC-V Disassembler") Regardless of adding a 'Fixes' tag or not: Reviewed-by: Daniel Henrique Barboza Thanks, Daniel +case

Re: [PATCH 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

On 5/13/24 08:46, Rajnesh Kanwal wrote: Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any

Re: [PATCH 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.

is breaks the usual char limit: Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") As for the code: Reviewed-by: Daniel Henrique Barboza

[PATCH v2 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Reported-by: Robin Dapp Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML") Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Acked-by: Alex Bennée --- target/riscv/gdbstub.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/risc

[PATCH v2 0/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

: - rename 'reg_width' to 'bitsize' - v1 link: https://lore.kernel.org/qemu-riscv/20240516171010.639591-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (1): riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() target/riscv/gdbstub.c | 6 +++--- 1 file changed, 3 insertions

Re: [PATCH v2 10/15] hw/riscv/riscv-iommu: add ATS support

Hi Frank, On 5/7/24 23:57, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:06寫道： From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request

Re: [PATCH v2 08/15] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

On 5/8/24 04:26, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands

Re: [PATCH v2 09/15] hw/riscv/riscv-iommu: add s-stage and g-stage support

On 5/10/24 08:14, Andrew Jones wrote: On Fri, May 10, 2024 at 06:36:51PM GMT, Frank Chang wrote: ... static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, -IOMMUTLBEntry *iotlb) +IOMMUTLBEntry *iotlb, bool gpa) { +dma_addr_t addr, base; +uint64_t

[PATCH 0/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

{57920, 1, 57920, 1, 57920, 1, 57920, 1}, b = {64, 226, 1, 0, 64, 226, 1, 0, 64, 226, 1, 0, 64, 226, 1, 0}} (gdb) Michael, this is a good pick for qemu-stable. Daniel Henrique Barboza (1): riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() target/riscv/gdbstub.c | 2

[PATCH 1/1] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

ehand. Cc: Akihiko Odaki Cc: Alex Bennée Reported-by: Robin Dapp Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML") Signed-off-by: Daniel Henrique Barboza --- target/riscv/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/gdbs

Re: [PATCH v2 15/15] hw/misc: EDU: add ATS/PRI capability

Hi Frank! On 5/7/24 12:32, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： From: Tomasz Jeznach Mimic ATS interface with IOMMU translate request with IOMMU_NONE. If mapping exists, translation service will return current permission flags, otherwise

Re: [PATCH v2 02/15] hw/riscv: add riscv-iommu-bits.h

On 5/15/24 07:02, Eric Cheng wrote: On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote: From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Hi Jason, On 5/1/24 08:57, Jason Chien wrote: Daniel Henrique Barboza 於 2024/3/8 上午 12:03 寫道: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv

Re: [PATCH v2] target/riscv: Remove experimental prefix from "B" extension

off-by: Rob Bradford Reviewed-by: Andrew Jones --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7d6d..861d9f4350 10064

Re: [PATCH] target/riscv: rvzicbo: Fixup CBO extension register calculation

On 5/13/24 23:39, Alistair Francis wrote: When running the instruction ``` cbo.flush 0(x0) ``` QEMU would segfault. The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0] allocated. In order to fix this let's use the existing get_address() helper. This also has the benefit

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Hi Frank, On 5/10/24 07:58, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年5月8日 週三 下午7:16寫道： Hi Frank, I'll reply with that I've done so far. Still missing some stuff: On 5/2/24 08:37, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Hi Frank, On 5/8/24 08:15, Daniel Henrique Barboza wrote: Hi Frank, I'll reply with that I've done so far. Still missing some stuff: On 5/2/24 08:37, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道： From: Tomasz Jeznach The RISC-V IOMMU specification

Re: [PATCH RESEND] target/riscv/cpu.c: fix Zvkb extension config

sions to riscv_cpu_extensions") Reviewed-by: LIU Zhiwei --- Reviewed-by: Daniel Henrique Barboza Michael, here's another one for stable. Thanks, Daniel target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb1a2e7d6d..

Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension

On 5/10/24 05:29, Andrew Jones wrote: On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote: On 5/8/24 08:22, Andrew Jones wrote: On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote: This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so

Re: [PATCH] target/riscv: Remove experimental prefix from "B" extension

On 5/8/24 08:22, Andrew Jones wrote: On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote: This extension has now been ratified: https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be removed. Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 2 +- 1 file changed, 1

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

On 5/7/24 12:44, Peter Maydell wrote: On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza wrote: Hi, In this RFC I want to check with Gerd and others if it's ok to add a PCI id for the RISC-V IOMMU device. It's currently under review in [1]. The idea is to fold this patch into the RISC-V

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

On 5/7/24 12:53, Gerd Hoffmann wrote: On Tue, May 07, 2024 at 11:37:05PM GMT, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年5月3日 週五 下午8:43寫道： Hi, In this RFC I want to check with Gerd and others if it's ok to add a PCI id for the RISC-V IOMMU device. It's currently under

Re: [RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

On 5/7/24 12:37, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年5月3日 週五 下午8:43寫道： Hi, In this RFC I want to check with Gerd and others if it's ok to add a PCI id for the RISC-V IOMMU device. It's currently under review in [1]. The Is the link [1] missing? Ooops. Here's

Re: [PATCH v2 03/15] hw/riscv: add RISC-V IOMMU base emulation

Hi Frank, I'll reply with that I've done so far. Still missing some stuff: On 5/2/24 08:37, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:04寫道： From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process

Re: [PATCH v2 11/15] hw/riscv/riscv-iommu: add DBG support

Hi Frank, On 5/6/24 01:09, Frank Chang wrote: Hi Daniel, Daniel Henrique Barboza 於 2024年3月8日 週五 上午12:05寫道： From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided

[RFC PATCH 1/1] pci-ids.rst: add Red Hat pci-id for generic IOMMU device

Reserve an id to be used by the RISC-V IOMMU PCI device. Cc: Gerd Hoffmann Signed-off-by: Daniel Henrique Barboza --- docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + 2 files changed, 3 insertions(+) diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst index c0a3dec2e7

[RFC PATCH 0/1] pci: allocate a PCI ID for RISC-V IOMMU

. Let me know if you want another ID instead. Daniel Henrique Barboza (1): pci-ids.rst: add Red Hat pci-id for generic IOMMU device docs/specs/pci-ids.rst | 2 ++ include/hw/pci/pci.h | 1 + 2 files changed, 3 insertions(+) -- 2.44.0

Re: [PATCH v2 04/15] hw/riscv: add riscv-iommu-pci device

On 4/29/24 04:21, Frank Chang wrote: Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> 於 2024年3月8日 週五 上午12:04寫道： > > From: Tomasz Jeznach mailto:tjezn...@rivosinc.com>> > > The RISC-V IOMMU can be modelled as a PCIe device following the > guidelin

Re: [PATCH 2/3] target/riscv: Enforce WARL behavior for scounteren/hcounteren

On 4/29/24 16:28, Atish Patra wrote: scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra --- Reviewed-by: Daniel Henrique Barboza target/riscv/csr.c

Re: [PATCH 1/3] target/riscv: Save counter values during countinhibit update

On 4/29/24 16:28, Atish Patra wrote: Currently, if a counter monitoring cycle/instret is stopped via mcountinhibit we just update the state while the value is saved during the next read. This is not accurate as the read may happen many cycles after the counter is stopped. Ideally, the read

Re: [PATCH 2/2] target/riscv: do not set mtval2 for non guest-page faults

ten with either zero or guest physical address that faulted, shifted by 2 bits. *For other traps, mtval2 is set to zero...* Signed-off-by: Alexei Filippov --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --

Re: [PATCH v3] target/riscv: Raise exceptions on wrs.nto

to the exception is implementation-specific. Signed-off-by: Andrew Jones Reviewed-by: Christoph Müllner --- Reviewed-by: Daniel Henrique Barboza v3: - Sending again, hoping the ü remains in Müllner v2: - Added #ifndef CONFIG_USER_ONLY around helper call target/riscv/helper.h

[PATCH] target/riscv/kvm: implement SBI debug console (DBCN) calls

using DBCN. With this patch we're taking around 14 seconds to boot due to the speed-up in the terminal output. There's no change in boot time if the guest isn't using earlycon. Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 111 + ta

[PATCH v2 1/2] target/riscv/kvm: remove sneaky strerrorname_np() instance

Henrique Barboza Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé --- target/riscv/kvm/kvm-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 6a6c6cae80..ee69ea9785 100644 --- a/target/riscv/kvm

[PATCH v2 0/2] riscv,kvm: remove another strerrorname_np()

and I'll send a v3. Changes from v1: - patch 2: - move the strerrorname_np() check to the "non-portable libc calls" section - v1 link: https://lore.kernel.org/qemu-riscv/20240424094700.453356-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (2): target/riscv/kvm: remove

[PATCH v2 2/2] checkpatch.pl: forbid strerrorname_np()

time: $ ./scripts/checkpatch.pl 0001-temp-test.patch ERROR: use strerror() instead of strerrorname_np() #22: FILE: target/riscv/kvm/kvm-cpu.c:1058: + strerrorname_np(errno)); total: 1 errors, 0 warnings, 10 lines checked Signed-off-by: Daniel Henrique Barboza

Re: [PATCH 1/2] target/riscv/kvm: remove sneaky strerrorname_np() instance

On 4/24/24 06:55, Philippe Mathieu-Daudé wrote: On 24/4/24 11:46, Daniel Henrique Barboza wrote: Commit d424db2354 excluded some strerrorname_np() instances because they break musl libc builds. Another instance happened to slip by via commit d4ff3da8f4. Remove it before it causes trouble

[PATCH 1/2] target/riscv/kvm: remove sneaky strerrorname_np() instance

Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 6a6c6cae80..ee69ea9785 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1054,8 +1054,8

[PATCH 2/2] checkpatch.pl: forbid strerrorname_np()

time: $ ./scripts/checkpatch.pl 0001-temp-test.patch ERROR: use strerror() instead of strerrorname_np() #22: FILE: target/riscv/kvm/kvm-cpu.c:1058: + strerrorname_np(errno)); total: 1 errors, 0 warnings, 10 lines checked Signed-off-by: Daniel Henrique Barboza

[PATCH 0/2] riscv,kvm: remove another strerrorname_np()

. Michael, patch 1 is qemu-stable material. Daniel Henrique Barboza (2): target/riscv/kvm: remove sneaky strerrorname_np() instance checkpatch.pl: forbid strerrorname_np() scripts/checkpatch.pl | 4 target/riscv/kvm/kvm-cpu.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions

Re: RISC-V u-boot unable to boot QEMU using '-cpu max'

On 4/23/24 09:41, Conor Dooley wrote: On Tue, Apr 23, 2024 at 01:34:42PM +0800, Leo Liang wrote: On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote: [EXTERNAL MAIL] Hi, In QEMU we have a 'max' type CPU that implements (almost) all extensions that QEMU is able

RISC-V u-boot unable to boot QEMU using '-cpu max'

Hi, In QEMU we have a 'max' type CPU that implements (almost) all extensions that QEMU is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the extensions for this CPU. And after this commit this CPU is now unable to boot a guest using upstream u-boot. Here's the error being

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

On 4/22/24 16:44, Richard Henderson wrote: On 4/22/24 10:45, Daniel Henrique Barboza wrote: Palmer, Anup, On 4/22/24 10:58, Clément Léger wrote: The current semihost exception number (16) is a reserved number (range [16-17]). The upcoming double trap specification uses that number

Re: [PATCH] target/riscv/kvm: Fix exposure of Zkr

drew Jones --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.h | 3 +++ target/riscv/csr.c | 18 ++ target/riscv/kvm/kvm-cpu.c | 25 + 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/ta

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Palmer, Anup, On 4/22/24 10:58, Clément Léger wrote: The current semihost exception number (16) is a reserved number (range [16-17]). The upcoming double trap specification uses that number for the double trap exception. Since the privileged spec (Table 22) defines ranges for custom uses change

[PATCH v2 1/1] target/riscv/kvm: tolerate KVM disable ext errors

in KVM, since adding the extension in riscv,isa at this point will cause a guest malfunction because the extension isn't enabled in the vcpu. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 12 1 file changed, 8 insertions(+), 4

[PATCH v2 0/1] target/riscv/kvm: tolerate KVM disable ext errors

if EINVAL is returned. We'll keep erroring out otherwise. - v1 link: https://lore.kernel.org/qemu-riscv/20240422131253.313869-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (1): target/riscv/kvm: tolerate KVM disable ext errors target/riscv/kvm/kvm-cpu.c | 12 1 file changed

Re: [PATCH] target/riscv/kvm: tolerate KVM disable ext errors

On 4/22/24 10:43, Andrew Jones wrote: On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote: Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr enabled, will fail with a kernel oops SIGILL right at the start. The reason is that we can't expose zkr

[PATCH] target/riscv/kvm: tolerate KVM disable ext errors

at this point will cause a guest malfunction because the extension isn't enabled in the vcpu. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/kvm/kvm

Re: [PATCH] target/riscv: Use get_address() to get address with Zicbom extensions

ilippe Mathieu-Daudé --- Reviewed-by: Daniel Henrique Barboza target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc index d5d7095903..6f6b29598d

Re: [PATCH for-9.0 v3 2/2] qtest/virtio-9p-test.c: remove g_test_slow() gate

On 4/16/24 16:54, Michael Tokarev wrote: 27.03.2024 17:20, Daniel Henrique Barboza : Commit 558f5c42ef gated the local tests with g_test_slow() to skip them in 'make check'. The reported issue back then was this following CI problem: https://lists.nongnu.org/archive/html/qemu-devel/2020-11

[PATCH for-9.1 v3 0/2] target/riscv: set tval in breakpoints

/ Daniel Henrique Barboza (2): target/riscv/debug: set tval=pc in breakpoint exceptions trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint target/riscv/cpu_helper.c | 1 + target/riscv/debug.c | 3 +++ target/riscv/insn_trans

[PATCH for-9.1 v3 2/2] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/

[PATCH for-9.1 v3 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

used as as scratch area for traps with address information. 'tval' is then set during riscv_cpu_do_interrupt(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu_helper.c | 1 + target/riscv/debug.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_helper.c b/ta

[PATCH for-9.1 v2 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

used as as scratch area for traps with address information. 'tval' is then set during riscv_cpu_do_interrupt(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu_helper.c | 1 + target/riscv/debug.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_helper.c b/ta

[PATCH for-9.1 v2 2/2] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_privileged.c.inc | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/

[PATCH for-9.1 v2 0/2] target/riscv: set (m|s)tval on

patch (2): - set mtval/stval during ebreak - v1 link: https://lore.kernel.org/qemu-riscv/20240320093221.220854-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (2): target/riscv/debug: set tval=pc in breakpoint exceptions trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint target

Re: [RFC PATCH 0/4] target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V

) can be moved to kvm-all.c, it looks good to me. Since you're changing kvm-all.c we'll need Paolo to ack the changes in patch 1, so feel free to wait for him to take a look before sending v2. Thanks, Daniel Thanks, Chao On 2023-12-22 22:16, Daniel Henrique Barboza wrote: Hi, It seems

Re: [RFC PATCH 1/4] target/riscv/kvm: add software breakpoints support

On 12/21/23 06:49, Chao Du wrote: This patch implements insert/remove software breakpoint process: Add an input parameter for kvm_arch_insert_sw_breakpoint() and kvm_arch_remove_sw_breakpoint() to pass the length information, which helps us to know whether it is a compressed instruction. For

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