@@ -5336,6 +5336,7 @@ X86:
operand in a SSE register. If AVX is also enabled, can also be a 256-bit
vector operand in an AVX register. If AVX-512 is also enabled, can also be a
512-bit vector operand in an AVX512 register. Otherwise, an error.
+- ``Ws``: A symbolic
@@ -56966,6 +56965,17 @@ void
X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
}
return;
}
+ case 'W': {
+assert(Constraint[1] == 's');
+if (const auto *GA = dyn_cast(Op)) {
+ Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=i686 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
+
+@var = external dso_local global i32, align 4
+
+define dso_local void @test() {
+;
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/77608
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@@ -1624,6 +1632,15 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB)
{
} else {
DidChange = true;
PMBB->ReplaceUsesOfBlockWith(MBB, CurTBB);
+ // Add rest successors of MBB to successors of CurTBB. Those
+
@@ -1363,6 +1363,14 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB)
{
MachineBasicBlock *Pred = *(MBB->pred_end()-1);
Pred->ReplaceUsesOfBlockWith(MBB, &*FallThrough);
}
+ // Add rest successors of MBB to successors of FallThrough. Those
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>From 72fa88d9e2277a8df60cf39d8cc96aad984dc2e9 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Thu, 11 Jan 2024 14:59:51 +0800
Subject: [PATCH 1/2] [X86][WIP] Use vXi1 for `k` constraint in inline asm
Fixes
https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/77733
Fixes #77172
>From 72fa88d9e2277a8df60cf39d8cc96aad984dc2e9 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Thu, 11 Jan 2024 14:59:51 +0800
Subject: [PATCH] [X86][WIP] Use vXi1 for `k` constraint in inline
@@ -173,25 +183,59 @@ __popcntq(unsigned long long __A)
#endif /* __x86_64__ */
#ifdef __x86_64__
+/// Returns the program status and control \c RFLAGS register with the \c VM
+///and \c RF flags cleared.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the
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phoebewang wrote:
> > > This keeps CFG as only have one entry which is required by LiveDebugValues
> >
> >
> > If we just want to make LiveDebugValues happy, should it better to remove
> > these died BB instead?
>
> This died BB was already removed by BranchFolder. See rebased test diff. We
@@ -1363,6 +1363,14 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB)
{
MachineBasicBlock *Pred = *(MBB->pred_end()-1);
Pred->ReplaceUsesOfBlockWith(MBB, &*FallThrough);
}
+ // Add rest successors of MBB to successors of FallThrough. Those
https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/77525
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LGTM.
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@@ -933,6 +933,14 @@ X86 Support
- Support ISA of ``AVX10.1``.
- ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
- Added ABI handling for ``__float128`` to match with GCC.
+- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF,
@@ -933,6 +933,14 @@ X86 Support
- Support ISA of ``AVX10.1``.
- ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported.
- Added ABI handling for ``__float128`` to match with GCC.
+- Emit warnings for options to enable knl/knm specific ISAs: AVX512PF,
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify
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>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/5] [X86] Add ABI handling for fp128
Fixes #74601
---
@@ -18,7 +18,7 @@ This test serves two purposes:
The list of warnings below should NEVER grow. It should gradually shrink to 0.
-CHECK: Warnings without flags (65):
phoebewang wrote:
Maybe it's not a good example. The test is to prevent adding warnings
@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const
LiveRange ,
OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
}
+ bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
while (true) {
@@ -18,7 +18,7 @@ This test serves two purposes:
The list of warnings below should NEVER grow. It should gradually shrink to 0.
-CHECK: Warnings without flags (65):
phoebewang wrote:
The comment says we should not increase it.
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify
@@ -3347,10 +3348,37 @@ void MachineVerifier::verifyLiveRangeSegment(const
LiveRange ,
OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
}
+ bool IsEHa = MF->getMMI().getModule()->getModuleFlag("eh-asynch");
while (true) {
https://github.com/phoebewang closed
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phoebewang wrote:
Thanks @FreddyLeaf !
https://github.com/llvm/llvm-project/pull/76901
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@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 =
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 =
@@ -2621,6 +2642,29 @@ SDValue
DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
}
+// Explicit operation to reduce precision. Reduce the value to half precision
+// and promote it back to the legal
@@ -1097,7 +1097,7 @@ def : Pat <
multiclass f16_fp_Pats {
// f16_to_fp patterns
def : GCNPat <
-(f32 (f16_to_fp i32:$src0)),
+(f32 (any_f16_to_fp i32:$src0)),
phoebewang wrote:
Should we replace more `f16_to_fp` to `any_f16_to_fp` in this file
phoebewang wrote:
> Add a Release notes entry? I always forget exactly what we need to do for ABI
> fixes/tweaks
Goot point! Done.
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>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/4] [X86] Add ABI handling for fp128
Fixes #74601
---
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/3] [X86] Add ABI handling for fp128
Fixes #74601
---
https://github.com/phoebewang edited
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>From ff9b72bdb5442a037d4325619de66e25ad211586 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 1 Jan 2024 15:13:38 +0800
Subject: [PATCH] [X86][BF16][WIP] Try to use `f16` for lowering
---
phoebewang wrote:
Ping @RKSimon
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phoebewang wrote:
> Making avx512f the only case where avx512vl can be disabled doesn't seem like
> too much of a stretch to me - we'd be merely making all avx512 extension
> features depend on avx512vl.
Agreed.
https://github.com/llvm/llvm-project/pull/75580
phoebewang wrote:
> I also think we need a policy regarding what test coverage we need for
> various avx512 features (when should we assume avx512vl etc.)
Considering the new evolution in AVX10, we should switch testing model from
`avx512xxx ± avx512vl` to `avx512xxx + avx512vl ±
evex512`.
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
Yes, e.g, `llvm/test/CodeGen/X86/{soft-fp,x87}.ll`, though I doubt if they can
work in reality since they
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
I decided not to report error for `-sse` after investigating the current
diagnosis machinism.
We didn't
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75156
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH 1/2] [X86] Add ABI handling for fp128
Fixes #74601
---
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phoebewang wrote:
Thanks @MaxEW707 ! I don't have other comments now. Do you need help to merge
it for you?
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@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
I think comment is
@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
Sorry, just noticed
@@ -92,136 +92,11 @@ __INLINE unsigned char
}
#endif
-/* Intrinsics that are also available if __ADX__ is undefined. */
-
-/// Adds unsigned 32-bit integers \a __x and \a __y, plus 0 or 1 as indicated
-///by the carry flag \a __cf. Stores the unsigned 32-bit sum in the
https://github.com/phoebewang approved this pull request.
LGTM.
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@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
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@@ -0,0 +1,160 @@
+/*=== adxintrin.h - ADX intrinsics -===
phoebewang wrote:
adx -> adc
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phoebewang wrote:
> Can you give me a better idea of the stages you intend to follow with this.
> The patch title suggests removing all KNL/KNM handling but the patch itself
> looks to be just about the KNL/KNM specific features.
>
> Removing the (incomplete) KNL/KNM specific features
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phoebewang wrote:
One more reason I can think of is with KNL/KNM removal, we can simplify
supporting widen 128/256-bit vector to 512-bit without AVX512VL feature since
all reset targets support AVX512VL. The test cases can be simplified too.
https://github.com/llvm/llvm-project/pull/75580
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/75571
>From 2e31cbd1a0b5b9c1689f664c6c261cabbc656f2a Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Fri, 15 Dec 2023 16:11:02 +0800
Subject: [PATCH 1/2] [X86][AVX10] Allow 64-bit mask register used without
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -triple x86_64-linux -emit-llvm -target-feature +sse2 < %s
| FileCheck %s --check-prefixes=CHECK
phoebewang wrote:
This patch only changes for 64-bit ABI, non-SSE is not a valid case for 64-bit.
OTOH, -sse just generate
phoebewang wrote:
Can this solve https://github.com/llvm/llvm-project/issues/68566 too?
https://github.com/llvm/llvm-project/pull/75448
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@@ -8251,6 +8251,25 @@ static void HandleVectorSizeAttr(QualType ,
const ParsedAttr ,
return;
}
+ // check -mgeneral-regs-only is specified
+ const TargetInfo = S.getASTContext().getTargetInfo();
+ llvm::Triple::ArchType arch = targetInfo.getTriple().getArch();
+
@@ -717,8 +717,15 @@ bool TargetInfo::validateOutputConstraint(ConstraintInfo
) const {
if (*Name != '=' && *Name != '+')
return false;
- if (*Name == '+')
+ if (*Name == '+') {
Info.setIsReadWrite();
+// To align with GCC asm: "=f" is not allowed, the
+
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Fixes #74601
>From 9860e5454bdf3ee3a4283ab7102a8d70c3ebcbbc Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 12 Dec 2023 17:27:33 +0800
Subject: [PATCH] [X86] Add ABI handling for fp128
Fixes #74601
Author: Phoebe Wang
Date: 2023-12-05T15:58:55+08:00
New Revision: 0ca80eb5e814a6d061556888c9c9fbd04f054a80
URL:
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80
DIFF:
https://github.com/llvm/llvm-project/commit/0ca80eb5e814a6d061556888c9c9fbd04f054a80.diff
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/68618
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LGTM.
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@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
@@ -422,3 +422,28 @@
// RUN: touch %t.o
// RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu
-mharden-sls=all %t.o -o /dev/null 2>&1 | count 0
+// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=APXF %s
+//
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable
Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8
URL:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff
@@ -7254,6 +7255,10 @@ static SDValue
lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
EVT CVT = Ld.getValueType();
assert(!CVT.isVector() && "Must not broadcast a vector type");
+// 512 bit vpbroadcastw is only available with AVX512BW
+if (ScalarSize ==
Author: Phoebe Wang
Date: 2023-11-22T21:59:30+08:00
New Revision: e5cc3da6a9077548f613eee3aacc5e7b017c81f3
URL:
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3
DIFF:
https://github.com/llvm/llvm-project/commit/e5cc3da6a9077548f613eee3aacc5e7b017c81f3.diff
Author: Phoebe Wang
Date: 2023-11-19T10:14:34+08:00
New Revision: 5237193b87721134541f228e28edfd544a9c8ac8
URL:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8
DIFF:
https://github.com/llvm/llvm-project/commit/5237193b87721134541f228e28edfd544a9c8ac8.diff
Author: Phoebe Wang
Date: 2023-11-14T15:39:30+08:00
New Revision: e96eddec5e8ecc0fdab377571aabe85a2ee7617e
URL:
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e
DIFF:
https://github.com/llvm/llvm-project/commit/e96eddec5e8ecc0fdab377571aabe85a2ee7617e.diff
Author: Phoebe Wang
Date: 2023-11-14T15:34:38+08:00
New Revision: 17dd0c70c8c3183c62d184de2e91a859c36880e9
URL:
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9
DIFF:
https://github.com/llvm/llvm-project/commit/17dd0c70c8c3183c62d184de2e91a859c36880e9.diff
https://github.com/phoebewang closed
https://github.com/llvm/llvm-project/pull/72126
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https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/8] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/7] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/6] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/4] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/3] [X86][AVX10] Fix a bug when using -march with no-evex512
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/72126
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject: [PATCH 1/2] [X86][AVX10] Fix a bug when using -march with no-evex512
phoebewang wrote:
Thanks @ronlieb and @mstorsjo. Created #72126 for it.
https://github.com/llvm/llvm-project/pull/71318
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https://github.com/phoebewang created
https://github.com/llvm/llvm-project/pull/72126
failed to clear EVEX512 feature for intended intrinsics.
Fixes #72106
>From a7642c3216cac9901f2e8b2290732ad526406b06 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Mon, 13 Nov 2023 23:21:35 +0800
Subject:
phoebewang wrote:
@ronlieb The reproducer can compile successfully in trunk:
https://godbolt.org/z/hvKhGq9bq
Are you using a downstream compiler? You can check if the "emmintrin.h" has the
same change as main trunk.
You can also check it through pre-compile the code:
```
$ clang++ -E
phoebewang wrote:
@ronlieb Do you have a reproducer for this problem? I just checked the
definition of both intrinsics have `no-evex512` already, so shouldn't have such
problem.
You can use -mno-evex512 as workaround for the problem anyway.
https://github.com/llvm/llvm-project/pull/71318
phoebewang wrote:
Thanks @KanRobert @e-kud
https://github.com/llvm/llvm-project/pull/71318
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phoebewang wrote:
> I'm a little bit confused, What's the expected behavior of `+avx10.1-512
> -avx10.1-256` in codegen aspect? Should we generate only instructions in the
> difference of sets? Or do we consider `avx10.1-256` as a base of
> `avx10.1-512` and if it is disabled `avx10.1-512`
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- }
@@ -50,11 +50,11 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS
\
-
@@ -15,8 +15,12 @@
#define __AVX2INTRIN_H
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__,
__target__("avx2"), __min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabled(Features, F, true);
std::vector UpdatedFeaturesVec;
- bool HasEVEX512 = true;
+ std::vector UpdatedAVX10FeaturesVec;
+ int HasEVEX512 = -1;
phoebewang wrote:
I think it's
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