Re: [Alsa-devel] preallocate_pages_for_all

2004-05-16 Thread Jaroslav Kysela
On Sat, 15 May 2004, Giuliano Pochini wrote: > snd_pcm_lib_preallocate_pages_for_all() preallocates the buffers for the > first 4 substreams by default. Can I change that number from the driver ? I > would like to preallocate a buffer only for the first subdev, or maybe for > the first, the 3rd, t

Re: [Alsa-devel] spin_lock_irqwhat ?

2004-05-16 Thread Takashi Iwai
At Sat, 15 May 2004 23:37:47 +0200, Giuliano Pochini wrote: > > On Fri, 14 May 2004 12:37:46 +0200 > Takashi Iwai <[EMAIL PROTECTED]> wrote: > > > > > prepare and trigger callbacks are already in irq-disabled. > > > > i.e. you need only spin_lock() in them. > > > > > > Does it mean that ALSA acqu

Re: [Alsa-devel] Emu10k1x driver

2004-05-16 Thread Takashi Iwai
At Sat, 15 May 2004 17:30:52 -0400, Francisco Moraes wrote: > > Takashi Iwai wrote: > > >>Is your patch for kernel 2.6? > >> > >> > > > >to the latest ALSA cvs. > >you'd better to get the CVS tree (either via cvs or snapshot). > >it already incldues emu10k1x.c. > > > > > I got it from there

Ignore this -> [Alsa-devel] 24bit .wav file fails to output to "plug:front" device with aplay on Audigy2

2004-05-16 Thread James Courtier-Dutton
James Courtier-Dutton wrote: I have been doing some tests with 24bit audio. It seems that any 24bit stream is muted if one tries to send it to alsa-lib. I am going to do further tests, but I just wanted to see if anyone else has ever tried 24bit sound with the Audigy2? Cheers James Please ignor

[Alsa-devel] sample rate rule problems

2004-05-16 Thread Giuliano Pochini
I'm trying to write a rule for the Layla24. That card supports all standard sample rates 8KHz-96KHz and continuous rates only in the range 25KHz-100KHz. I wrote this rule, but ALSA gets confused and it sometimes chooses a wrong value, sometimes fails. I can't figure out why. This is the rule: {

[Alsa-devel] RME HDSP 9652 syncing problem

2004-05-16 Thread Ryan Winter
Hi, I have been using the RME HDSP 9652 for several months now and have noticed a problem with the synchonisation. I have an external word clock which runs into 2 RME analog/digital interfaces, as well as the HDSP itself. The HDSP is setup to sync to word clock input, and sample clock source is