RE: [PATCH] drm/amdgpu:fix DMAframe for GFX8

1,drop inserting double SWITCH_BUFFERS scheme, which impacts performance, because double SWITCH_BUFFER actaully doesn't switch buffer, so the CE's ping-pong buffer is not used at all. Now only insert one SWITCH_BUFFERS at the bottom of each GFX dmaframe. And only inserting one SWITCH_BUFFER is

FW: [PATCH] drm/amdgpu:fix DMAframe for GFX8

-Original Message- From: Monk Liu [mailto:monk@amd.com] Sent: Wednesday, August 24, 2016 12:00 PM To: amd-gfx@lists.freedesktop.org Cc: Liu, Monk Subject: [PATCH] drm/amdgpu:fix DMAframe for GFX8 1,drop inserting double SWITCH_BUFFERS scheme, which impacts

[PATCH] drm/amdgpu:fix DMAframe for GFX8

1,drop inserting double SWITCH_BUFFERS scheme, which impacts performance, because double SWITCH_BUFFER actaully doesn't switch buffer, so the CE's ping-pong buffer is not used at all. Now only insert one SWITCH_BUFFERS at the bottom of each GFX dmaframe. And only inserting one SWITCH_BUFFER is a

Re: [PATCH] drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit

Looks very good to me, binding time and byte is good idea according free vram. Did you test more games for your algorithm? Regards, David Zhou On 2016年08月24日 06:19, Marek Olšák wrote: From: Marek Olšák The old mechanism used a per-submission limit that didn't take

答复: [PATCH 3/3] drm/amdgpu: reset the asic when hibernating v2

Or, we also can use PM_EVENT_ messages to separate freeze, thaw, suspend, resume, poweroff and restore. Thanks JimQu 发件人: amd-gfx 代表 Michel Dänzer 发送时间: 2016年8月24日 9:03:20 收件人: Alex Deucher

Re: [PATCH 3/3] drm/amdgpu: reset the asic when hibernating v2

On 24/08/16 02:45 AM, Alex Deucher wrote: > Some blocks require a reset to properly resume if there > is no power down of the asic like during various > hibernation steps. > > Reset the asic on freeze and force asic_init on thaw. > > Port of: > 274ad65c9d02bdcbee9bae045517864c3521d530 >

[PATCH] drm/amdgpu: throttle buffer migrations at CS using a fixed MBps limit

From: Marek Olšák The old mechanism used a per-submission limit that didn't take previous submissions within the same time frame into account. It also filled VRAM slowly when VRAM usage dropped due to a big eviction or buffer deallocation. This new method establishes a

[PATCH 4/4] drm/radeon: switch UVD code to use UVD_NO_OP for padding

Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c| 2 +- drivers/gpu/drm/radeon/cikd.h

[PATCH 3/4] drm/amdgpu: switch UVD code to use UVD_NO_OP for padding

Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 --

[PATCH 2/4] drm/radeon: add support for UVD_NO_OP register

Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/r600d.h | 1 + drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-

[PATCH 1/4] drm/amdgpu: add support for UVD_NO_OP register

Writes to this register are the preferred way to do NOPs. Bump the driver version as well. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-

Re: Random short freezes due to TTM buffer migrations

On Tue, Aug 23, 2016 at 8:01 PM, Marek Olšák wrote: > On Thu, Aug 18, 2016 at 10:52 AM, Christian König > wrote: >> In that case my patch should clearly help with that. >> >> Going to release what I have so far today, but looks like I need more time >>

Re: Random short freezes due to TTM buffer migrations

On Thu, Aug 18, 2016 at 10:52 AM, Christian König wrote: > In that case my patch should clearly help with that. > > Going to release what I have so far today, but looks like I need more time > actually fixing this. > > In the meantime you could try the "drm/amdgpu: fix

[PATCH 2/3] drm/amdgpu: add new device suspend and resume parameters

Add support for asic_reset and asic_init to the device suspend and resume functions. No change in functionality. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 +-

[PATCH 3/3] drm/amdgpu: reset the asic when hibernating v2

Some blocks require a reset to properly resume if there is no power down of the asic like during various hibernation steps. Reset the asic on freeze and force asic_init on thaw. Port of: 274ad65c9d02bdcbee9bae045517864c3521d530 (drm/radeon: hard reset r600 and newer GPU when hibernating.) from

[PATCH 1/3] drm/amdgpu: rename suspend_kms and resume_kms

The old names were dragged over from radeon. The new ones better match the naming conventions used in the driver. No functional change. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |

[PATCH] drm/amdgpu: fix IB alignment for UVD

According to the hw team, it should be 16, not 8. Cc: Peter Fang Signed-off-by: Alex Deucher Cc: sta...@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

RE: [PATCH 4/4] drm/amd/powerplay: delete useless code in iceland_hwmgr.c.

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Monday, August 22, 2016 8:50 AM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 4/4] drm/amd/powerplay: delete useless code in > iceland_hwmgr.c. > >

RE: [PATCH] drm/amd/amdgpu: Print ring name in amdgpu_ib_schedule()

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Tom St Denis > Sent: Monday, August 22, 2016 11:01 AM > To: amd-gfx@lists.freedesktop.org > Cc: StDenis, Tom > Subject: [PATCH] drm/amd/amdgpu: Print ring name in > amdgpu_ib_schedule() > >

RE: [PATCH 1/2] drm/amdgpu: use memcpy_to/fromio for UVD fw upload

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Christian König > Sent: Tuesday, August 23, 2016 5:20 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH 1/2] drm/amdgpu: use memcpy_to/fromio for UVD fw > upload > > From: Christian

RE: amdgpu's dce_vX_0_afmt_setmode(): why so different from radeon's

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Alexandre Demers > Sent: Monday, August 22, 2016 11:29 PM > To: amd-gfx@lists.freedesktop.org > Cc: Alexander Deucher; Christian König > Subject: amdgpu's dce_vX_0_afmt_setmode(): why so

[PATCH] drm/amdgpu: fix IB alignment for UVD

According to the hw team, it should be 16, not 8. Cc: Peter Fang Signed-off-by: Alex Deucher Cc: sta...@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

答复: [PATCH 1/2] drm/amdgpu: reset the asic when hibernating

Hi Alex: Are you working on S4 issue ? Thanks JimQu 发件人: amd-gfx 代表 Alex Deucher 发送时间: 2016年8月23日 0:05:24 收件人: amd-gfx@lists.freedesktop.org 抄送: Deucher, Alexander 主题: [PATCH 1/2]

[PATCH] Re: Mullins support in xf86-video-amdgpu

On 08/22/2016 08:27 PM, Michel Dänzer wrote: On 23/08/16 10:18 AM, Reid Hekman wrote: I was encouraged by a commit I saw today to add Sea Islands PCI ids to xf86-video-amdgpu. However I did not see MULLINS included. Are there other showstoppers preventing inclusion? I assume the commit

[PATCH 2/2] drm/amdgpu: use memcpy_toio for VCE firmware upload

From: Christian König Try to be clean here, even when it's a noop on x86. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

答复: 答复: [PATCH] drm/amdgpu: fix the wrong value of UVD bo size

OK. Thanks JimQu 发件人: Christian König 发送时间: 2016年8月23日 16:53:50 收件人: Qu, Jim; amd-gfx@lists.freedesktop.org 主题: Re: 答复: [PATCH] drm/amdgpu: fix the wrong value of UVD bo size > I will update the patch. Let me do this. I already

答复: [PATCH] drm/amdgpu: fix the wrong value of UVD bo size

Hi Christian: Yes, I have misunderstand the AMDGPU_UVD_FIRMWARE_OFFSET in amdgpu_uvd_mc_resume(). I will update the patch. Thanks JimQu 发件人: Christian König 发送时间: 2016年8月23日 16:02:11 收件人: Qu, Jim; amd-gfx@lists.freedesktop.org

Re: [PATCH 1/2] drm/amdgpu: wire up a pci shutdown callback

Am 22.08.2016 um 20:30 schrieb Alex Deucher: Normally on shutdown or reboot we don't care about necessarily making sure the hw is in a good state because the system is about to be powered down or reset. However, after a shutdown or reboot in a VM, it's best to tear down the hw properly

Re: [PATCH 1/2] drm/amdgpu: reset the asic when hibernating

Am 22.08.2016 um 18:05 schrieb Alex Deucher: Some blocks require a reset to properly resume if there is no power down of the asic like during various hibernation steps. Port of: 274ad65c9d02bdcbee9bae045517864c3521d530 (drm/radeon: hard reset r600 and newer GPU when hibernating.) from radeon.

Re: [PATCH] drm/amdgpu: fix the wrong value of UVD bo size

Am 23.08.2016 um 08:20 schrieb jimqu: Driver allocate bo for restore UVD fw ,cache, stack , etc. the firmware size is not only ucode size but the ucode and header. Nope that isn't correct. Only the firmware is copied to the BO, not the header. See amdgpu_uvd_resume(). Saying this we should

[PATCH] drm/amdgpu: fix the wrong value of UVD bo size

Driver allocate bo for restore UVD fw ,cache, stack , etc. the firmware size is not only ucode size but the ucode and header. Change-Id: I886c099fa123c4814de9b7db3559c30e7b41fd1b Signed-off-by: JimQu --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- 1 file changed, 1