[PATCH 2/3] drm/amdgpu:implement META-DATA write routines

Change-Id: I66007a7f7e4e27fb129121f36143dce3cfb43738 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 31 ++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 61 +++ 2 files changed, 92 insertions(+) diff --git

[PATCH 0/3] GFX8's meta-data write feature for SRIOV

*** BLURB HERE *** to enable GFX SRIOV we need insert some new packag in gfx ring which called META-DATA write command, and meta-data is composed by two parts: CE and DE. CE's meta-data write need prior to CNTX_CNTL package while DE's should following that. meta-data will notify CP about the CSA

[PATCH 1/3] drm/amdgpu:add META_DATA struct for CSA/SRIOV

META-DATA is used in GFX cmd submit, we have two types of META-DATA now, one is legacy and the other is for chained-ib-preemption, which is used in vulkan UMD. Change-Id: I17324905b4822a93fd3ffb3e8f86e544871b89ab Signed-off-by: Monk Liu ---

[PATCH 3/3] drm/amdgpu:invoke meta-data write around cntx_cntl

ce's META-DATA write need prior to cntx_cntrl package and de's should following. Change-Id: I2bf436d8a16bae38ce484f846f0b399e16cfe80a Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 3 +++

RE: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

> -Original Message- > From: Michel Dänzer [mailto:mic...@daenzer.net] > Sent: Thursday, January 12, 2017 1:45 PM > To: Liu, Monk ; Christian König > ; Yu, Xiangliang > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [V3

Re: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

On 12/01/17 12:21 PM, Liu, Monk wrote: > >if (in_interrupt()) > BUG(); Current coding style is BUG_ON(in_interrupt()); according to https://kernelnewbies.org/FAQ/BUG . -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast

答复: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

Xiangliang please BUG() when register access occured in RUNTIME and IRQ context, e.g.: for register read: if (amdgpu_sriov_runtime(adev)) { if (in_interrupt()) BUG(); else return amdgpu_virt_kiq_rreg(adev, reg, v); } and also for register write, with above addressed,

答复: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

Xiangliang please BUG() when register access occured in RUNTIME and IRQ context, e.g.: if (amdgpu_sriov_runtime(adev)) { } return amdgpu_virt_kiq_wreg(adev, reg, v); with above addressed, Reviewed-by: Monk Liu 发件人: amd-gfx

Re: More specific libdrm error message

Hi Xie, Perhaps you want to use `fprintf(stderr, "...")` over `printf("..")` and lose the space before the start parenthesis. Also, line wrap your commit message. Side note, use git send-email so that the patch is inline and not a HTML email for easy review and application of the patch. Kind

More specific libdrm error message

Hi, Provide more specific error message if non-privileged user runs amdgpu_test Before this change, the error message is:" WARNING - Suite initialization failed..." People might think this is a driver problem. Tested with non-privileged user. Now the error message is like. ...

Re: [PATCH 4/4] drm/amdgpu: extend profiling mode.

Rex Zhu wrote: in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as

Re: More specific libdrm error message

Hi, v2: Use strerror instead of %m. %m is a GNU C Library extension. Thanks, Alex Bin Xie From: Xie, AlexBin Sent: Wednesday, January 11, 2017 4:14 PM To: amd-gfx@lists.freedesktop.org Subject: More specific libdrm error message Hi, Provide more specific

[PATCH] drm/amdgpu: use the num_rings variable for checking vce rings

Difference families may have different numbers of rings. Use the variable rather than a hardcoded number. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

RE: [PATCH 05/10] drm/amd/display: Support 64-bit Polaris11 5k VSR

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Deucher, Alexander > Sent: Wednesday, January 11, 2017 2:25 PM > To: Wentland, Harry; amd-gfx@lists.freedesktop.org > Cc: Aberback, Joshua > Subject: RE: [PATCH 05/10] drm/amd/display:

RE: [PATCH 05/10] drm/amd/display: Support 64-bit Polaris11 5k VSR

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Harry Wentland > Sent: Wednesday, January 11, 2017 1:11 PM > To: amd-gfx@lists.freedesktop.org > Cc: Aberback, Joshua > Subject: [PATCH 05/10] drm/amd/display: Support 64-bit Polaris11 5k VSR

[PATCH 04/10] drm/amd/display: When signal type of sink is none, use link type for stream

From: Joshua Aberback Change-Id: If711bd494fcece078ef9c09eb542b510dcd68885 Signed-off-by: Joshua Aberback Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 08/10] drm/amd/display: Use DTO as clock on DP if not

From: Ding Wang Use DVO as pixel clock for DP before enabling link PHY. Otherwise, when switching from HDMI passive dongle to DP on the same connector, the PHY PLL is used as pixel clock, and CRTC would stop working. Change-Id: Iad2e20eaac6675ce53f9fec6781e75151c43666f

[PATCH 06/10] drm/amd/display: drop min/max wrappers

From: Dave Airlie These aren't needed, and aren't really used in too many places. Change-Id: I1a52c694d6d8a84f5756fed4f60f295173cba6b5 Signed-off-by: Dave Airlie Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland

[PATCH 03/10] drm/amd/display: set blank functionality

From: Hersen Wu 1. remove the sleep mechanism while set_blank true from the timing generator. Since Hw sequencer is the one that manages the flow he will be responsible for wait for blanck in a critical places. Change-Id: Idd2136fced775b5c9012c4034a6ee1306fce0945

[PATCH 10/10] drm/amd/display: Pass visible flag into surface programming

From: Yongqiang Sun Change-Id: Ic6c140575b5ffb6ce32e75d3a3725312a8be6942 Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

[PATCH 00/10] DC Patches Jan 11, 2017

* bunch of fixes, including for Polaris 12 * some cleanup, in particular to use HDMI header for HDMI defines Harry Arindam Nath (1): drm/amd/display: fix cursor disappearing after resume Dave Airlie (2): drm/amd/display: drop min/max wrappers drm/amd/display: start using linux hdmi

[PATCH 07/10] drm/amd/display: start using linux hdmi header

From: Dave Airlie DAL has defines for things, and it doesn't even use them itself. Change-Id: Ic94412df212f8d66b4ad482fcd70de46b7b8c61a Signed-off-by: Dave Airlie Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland

[PATCH 01/10] drm/amd/display: fix cursor disappearing after resume

From: Arindam Nath Since during suspend, the cursor registers are cleared, once the system resumes back, the cursor remains disabled. cursor_set_attributes() only sets the cursor attributes along with cursor size and surface address, but does not enable the cursor back on.

[PATCH 05/10] drm/amd/display: Support 64-bit Polaris11 5k VSR

From: Joshua Aberback - pass full asic_id info into bw_calc_init instead of only version enum - 64-bit Polaris11 needs an extra microsecond of dmif_urgent_latency - add helper to convert from asic_id.family to bw_calc version enum Change-Id:

[PATCH 02/10] drm/amd/display: blank mechanism for supporting MPO

From: Leon Elazar blank/unblanck functionality apply_ctx_for_surface will update planes visibility by manipulating Blender and CRTC HW modules. Change-Id: I0fa0b46cb36de203b07af7a846a740e81fda6233 Signed-off-by: Leon Elazar Reviewed-by: Dmytro

[PATCH 09/10] drm/amd/display: Add Polaris12 to bw_calc

From: Joshua Aberback Change-Id: I77c287c6d6fe2e46f232e707383347f11ade91c0 Signed-off-by: Joshua Aberback Reviewed-by: Tony Cheng Acked-by: Harry Wentland ---

RE: [PATCH] Revert "drm/amdgpu: Only update the CUR_SIZE register when necessary"

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Michel Dänzer > Sent: Wednesday, January 11, 2017 4:36 AM > To: amd-gfx@lists.freedesktop.org > Cc: Harald Judt; Johannes Hirte > Subject: [PATCH] Revert "drm/amdgpu: Only update the CUR_SIZE

[PATCH v2 2/2] drm/amd/amdgpu: fix locking in bo creation error path

From: Nicolai Hähnle Unlock the resv lock only if we were the ones to lock it in the first place. Signed-off-by: Nicolai Hähnle Reviewed-by: Edward O'Callaghan Reviewed-by: Christian König

[PATCH v2 1/2] drm/amd/amdgpu: lock reservation object while creating shadow bo

From: Nicolai Hähnle ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of the newly allocated buffer is used and must explicitly be locked. Uninterruptible w/w locks

Re: [PATCH 1/3] drm/amdgpu:new field members for SRIOV

[ML] do you mean If some where want to use vmid0_gds_address I should just use vmid0_csa_addr + 4096 ? Yes. Can I get your RB after above two place modified in patch ? Yeah, with that fixed the patch is Reviewed-by: Christian König . Regards, Christian. Am

RE: [V3 09/11] drm/amdgpu/virt: enable virtual display

Reviewed-by: Monk Liu -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Xiangliang Yu Sent: Wednesday, January 11, 2017 9:18 PM To: amd-gfx@lists.freedesktop.org Cc: Yu, Xiangliang Subject: [V3 09/11] drm/amdgpu/virt:

RE: [V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

Sounds make sense! BR Monk -Original Message- From: Yu, Xiangliang Sent: Wednesday, January 11, 2017 11:04 PM To: Yu, Xiangliang ; Liu, Monk ; amd-gfx@lists.freedesktop.org Cc: Liu, Shaoyun Subject: RE: [V3 06/11]

RE: [V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

> > We will discuss it tomorrow, I'm not sure of your approach right now > > > > We can stop running driver right after IDH_FLR_NOTIFICATION received > > and continue driver right after IDH_FLR_NOTIFICATION_CMPL If missing the interrupt, I think we can't easy to handle the error. That what i

RE: [V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

> We will discuss it tomorrow, I'm not sure of your approach right now > > We can stop running driver right after IDH_FLR_NOTIFICATION received and > continue driver right after IDH_FLR_NOTIFICATION_CMPL I have verified the method on my platform and work fine. Let's discuss it tomorrow if you

RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt

> -Original Message- > From: Liu, Monk > Sent: Wednesday, January 11, 2017 10:33 PM > To: Yu, Xiangliang ; amd- > g...@lists.freedesktop.org > Subject: RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt > > See in lines > > > -Original

RE: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

We should BUG and not access register at all if found during RUNTIME && IRQ_context By far. BR Monk -Original Message- From: Christian König [mailto:deathsim...@vodafone.de] Sent: Wednesday, January 11, 2017 10:44 PM To: Liu, Monk ; Yu, Xiangliang

RE: [V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

We will discuss it tomorrow, I'm not sure of your approach right now We can stop running driver right after IDH_FLR_NOTIFICATION received and continue driver right after IDH_FLR_NOTIFICATION_CMPL BR Monk -Original Message- From: Yu, Xiangliang Sent: Wednesday, January 11, 2017 10:43

RE: [PATCH 1/3] drm/amdgpu:new field members for SRIOV

>Similar to the GDS address inside the VMs I think the code actually using it >should calculate it from the BO address. [ML] do you mean If some where want to use vmid0_gds_address I should just use vmid0_csa_addr + 4096 ? >The validate buffer is only temporarily used during mapping the CSA

RE: [V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

> -Original Message- > From: Liu, Monk > Sent: Wednesday, January 11, 2017 10:28 PM > To: Yu, Xiangliang ; amd- > g...@lists.freedesktop.org > Cc: Yu, Xiangliang ; Liu, Shaoyun > > Subject: RE: [V3 06/11] drm/amdgpu/virt:

RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt

See in lines -Original Message- From: Yu, Xiangliang Sent: Wednesday, January 11, 2017 10:27 PM To: Liu, Monk ; amd-gfx@lists.freedesktop.org Subject: RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt > This patch is not derived from my work

RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt

> This patch is not derived from my work (amd-sriov-4.3/4.6), please don't add > my "signed-off-by: Monk Liu " line on it, Seems you add an upper layer > interface to invoke on gpu_request/release routines, And I will also take role > in the reviewing of it: > > + adev->virt.caps &=

Re: [PATCH 1/2] drm/amd/amdgpu: lock reservation object while creating shadow bo

Am 11.01.2017 um 15:09 schrieb Nicolai Hähnle: On 11.01.2017 12:56, Christian König wrote: Am 11.01.2017 um 08:31 schrieb Nicolai Hähnle: From: Nicolai Hähnle ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv !=

Re: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

Because if we are in interrupt , we are forbid to do schedule, and use kiq to read register will invoke fence_wait() ... That won't work. Locking a mutext like it is done in the write path can cause scheduling as well. If we need to push writes through the KIQ in interrupt context we need to

RE: [V3 05/11] drm/amdgpu/virt: add high level interfaces for virt

Hi Xiangliang This patch is not derived from my work (amd-sriov-4.3/4.6), please don't add my "signed-off-by: Monk Liu " line on it, Seems you add an upper layer interface to invoke on gpu_request/release routines, And I will also take role in the reviewing of it: +

Re: [PATCH 1/2] drm/amd/amdgpu: lock reservation object while creating shadow bo

On 11.01.2017 12:56, Christian König wrote: Am 11.01.2017 um 08:31 schrieb Nicolai Hähnle: From: Nicolai Hähnle ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of

RE: [V3 00/11] Add support AMD GPU virtualization soultion

> Patch #7 is missing a comment that this applies during driver load/unload, > cause that isn't obvious. Not just only for loading/unloading, resume process will need to request/release full gpu access after FLR (function level reset). Later I'll upstream FLR patches. > > With that fixed the

Re: [PATCH 1/2] drm/amd/amdgpu: lock reservation object while creating shadow bo

On 11.01.2017 12:56, Christian König wrote: Am 11.01.2017 um 08:31 schrieb Nicolai Hähnle: From: Nicolai Hähnle ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of

RE: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

Because if we are in interrupt , we are forbid to do schedule, and use kiq to read register will invoke fence_wait() ... If you think that's odds, we can use BUG_ON() to stop driver running if we need read registers in SRIOV case. And to fully support register reading, we need to implement a

Re: [V3 00/11] Add support AMD GPU virtualization soultion

Patches #1-#3, #5 and #8 are Reviewed-by: Christian König . Patch #6, #9 and #10 are Acked-by: Christian König . Patch #4: Just send out a question on this. Patch #7 is missing a comment that this applies during driver load/unload, cause

Re: [V3 04/11] drm/amdgpu/virt: use kiq to access registers

Am 11.01.2017 um 14:18 schrieb Xiangliang Yu: For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu ---

[V3 11/11] drm/amdgpu: do not reset gpu for virtualization

Current amdgpu reset process only works on bare-metal and for SRIOV many inside it need re-work to adapt to vf device. This is a temporary workaround to skip gpu reset. Signed-off-by: Monk Liu Signed-off-by: Xiangliang Yu ---

[V3 10/11] drm/amdgpu/virt: disable dc

Virtualization don't need the dc, disable it. Signed-off-by: Xiangliang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index

[V3 09/11] drm/amdgpu/virt: enable virtual display

Virtual display is default setting for virtualization, enable it. Signed-off-by: Xiangliang Yu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

[V3 07/11] drm/amdgpu: request/release full gpu access if device is vf

For gpu vf device, first need to request full gpu access before accessing gpu registers, and release full gpu access after the access is done. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9

[V3 08/11] drm/amdgpu/vi: add support virtualization

Call VI virtualization functions if device is Vf. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/vi.c | 34 -- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git

[V3 00/11] Add support AMD GPU virtualization soultion

This patch series will enable AMD GPU virtualization and wires it into amdgpu modules. Changes in V3: 1. rename field name; 2. remove extra fence_get()/fence_put(); 3. fixed coding style; 4. update patch comment; Changes in V2: 1. define new high level interface for non-asic specific; 2. add

[V3 04/11] drm/amdgpu/virt: use kiq to access registers

For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/Makefile| 2 +-

[V3 03/11] drm/amdgpu/virt: add runtime flag

Add new flag to define gpu runtime that is out of full gpu access. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 1 file changed, 4 insertions(+) diff --git

[V3 06/11] drm/amdgpu/virt: implement VI virt operation interfaces

VI has asic specific virt support, which including mailbox and golden registers init. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-

[V3 01/11] drm/amdgpu/ring: add two interfaces to support r/w registers with kiq

During virtual runtime, need to send command to kiq ring to read/write GPU registers. Add two interface to support the two actions. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Linu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++

[V3 05/11] drm/amdgpu/virt: add high level interfaces for virt

Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 57

[V3 02/11] drm/amdgpu/gfx8: implement emit_rreg/wreg function

Implement emit_rreg/wreg function for kiq ring. Signed-off-by: Xiangliang Yu Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 37 2 files changed,

Re: [PATCH 3/3] drm/amdgpu:invoke CSA functions

Am 11.01.2017 um 11:43 schrieb Monk Liu: Change-Id: I528c2f324830aaa21ab8d8250bc80a2a6bab33bd Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12

Re: [PATCH 2/3] drm/amdgpu:add new file for SRIOV

Am 11.01.2017 um 11:43 schrieb Monk Liu: for SRIOV usage, CSA is only used per device and each VM will map on it. Change-Id: Ibc63d87be59d7d89b96117e4d1b7e970a872580d Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-

Re: [PATCH 1/3] drm/amdgpu:new field members for SRIOV

Am 11.01.2017 um 11:43 schrieb Monk Liu: and implement CSA functions in this file Change-Id: Ife0eff7b13b8b5946f005a39f6ecb8db1cb72c38 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ 2

Re: [PATCH] drm/amdgpu: fix typo of CGTS

Reviewed-by: Tom St Denis From: amd-gfx on behalf of Huang Rui Sent: Tuesday, January 10, 2017 21:30 To: amd-gfx@lists.freedesktop.org Cc: StDenis, Tom; Huang, Ray Subject: [PATCH]

Re: [PATCH 1/2] drm/amd/amdgpu: lock reservation object while creating shadow bo

Am 11.01.2017 um 08:31 schrieb Nicolai Hähnle: From: Nicolai Hähnle ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of the newly allocated buffer is used and must

Re: [PATCH 2/2] drm/amd/amdgpu: fix locking in bo creation error path

Am 11.01.2017 um 08:31 schrieb Nicolai Hähnle: From: Nicolai Hähnle Unlock the resv lock only if we were the ones to lock it in the first place. Signed-off-by: Nicolai Hähnle Reviewed-by: Christian König . ---

Re: [PATCH 1/2] drm/amdgpu: fix bug set incorrect value to vce register

Am 11.01.2017 um 04:48 schrieb Rex Zhu: Change-Id: I1495894d01ca10e5d496e71f5d4b1a93a12336f3 Signed-off-by: Rex Zhu Not deeply into VCE programming any more, but both patches look like they make sense and are Acked-by: Christian König . Regards,

Re: 答复: [V2 04/11] drm/amdgpu/virt: use kiq to access registers

Ah, that issue again. Yeah that was fixed in the meantime. Please remove the extra fance_get()/fence_put() for upstreaming. If an old branch still has that issue we should backport the proper fixes and not work around them like this. Thanks for looking into it, Christian. Am 11.01.2017 um

Re: [PATCH] drm/amdgpu: fix vm_fault_stop on gfx6

Am 11.01.2017 um 07:31 schrieb Flora Cui: Change-Id: I9fcdb4bc69e5f5c80eadb1e5fd31570802b0ce70 Signed-off-by: Flora Cui Reviewed-by: Christian König . --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 23 +-- 1 file changed, 9

[PATCH 0/3] CSA patch v3

v2: drop invoking gem_va and update CSA address in CS routines, v3: reserve CSA bo and call vm_bo_rmv() to remove CSA mappings prior to vm_fini() Monk Liu (3): drm/amdgpu:new field members for SRIOV drm/amdgpu:add new file for SRIOV drm/amdgpu:invoke CSA functions

[PATCH 2/3] drm/amdgpu:add new file for SRIOV

for SRIOV usage, CSA is only used per device and each VM will map on it. Change-Id: Ibc63d87be59d7d89b96117e4d1b7e970a872580d Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 95

[PATCH 1/3] drm/amdgpu:new field members for SRIOV

and implement CSA functions in this file Change-Id: Ife0eff7b13b8b5946f005a39f6ecb8db1cb72c38 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ 2 files changed, 11 insertions(+) diff --git

[PATCH 3/3] drm/amdgpu:invoke CSA functions

Change-Id: I528c2f324830aaa21ab8d8250bc80a2a6bab33bd Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 14 ++

[PATCH] Revert "drm/amdgpu: Only update the CUR_SIZE register when necessary"

From: Michel Dänzer This reverts commits 7c83d7abc9997cf1efac2c0ce384b5e8453ee870 and a1f49cc179ce6b7b7758ae3ff5cdb138d0ee0f56. They caused the HW cursor to disappear under various circumstances in the wild. I wasn't able to reproduce any of them, and I'm not sure what's

答复: [V2 04/11] drm/amdgpu/virt: use kiq to access registers

Hi Christian latest updates on the fence grab/release I recall the impression of why I added those grab/release pare: I checked the history, the first time I added those pare is because they are first introduced/implemented in amd-sriov-4.3, and that branch's fence implement has big gap