On 18/08/17 11:51 PM, Abramov, Slava wrote:
> *From:* amd-gfx on behalf of
>
>> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
>> index 1a805b82d..bdd3866b8 100644
>> --- a/src/drmmode_display.c
>> +++ b/src/drmmode_display.c
>> @@ -96,6 +96,14
On 2017年08月22日 03:25, Alex Deucher wrote:
On Mon, Aug 21, 2017 at 7:26 AM, Christian König
wrote:
Ping? Can somebody take a look?
This is an bugfix and I would like to have it upstream before the next merge
window closes.
Reviewed-by: Alex Deucher
On 2017年08月21日 20:58, Christian König wrote:
From: Christian König
When a process is killed we shouldn't submit all waiting jobs, but instead
clean up as fast as possible.
Signed-off-by: Christian König
---
On 2017-08-21 12:00 PM, Alex Deucher wrote:
> We need a larger gart for asics that do not support GPUVM on all
> engines (e.g., MM) to make sure we have enough space for all
> gtt buffers in physical mode. Change the default size based on
> the asic type.
>
> Signed-off-by: Alex Deucher
On 2017-08-21 03:21 PM, Oded Gabbay wrote:
> On Mon, Aug 21, 2017 at 8:39 PM, Jerome Glisse wrote:
>> On Tue, Aug 15, 2017 at 11:00:20PM -0400, Felix Kuehling wrote:
>>> From: Moses Reuben
>>>
>>> v2:
>>> * Renamed ALLOC_MEMORY_OF_SCRATCH to
On 2017-08-21 04:01 PM, Jerome Glisse wrote:
>> From this explanation, I think that the user's supplied VA should be
>> tested that its a valid writable area of the user.
>> How do you test for that ? could you point me to such a code in the kernel ?
>> From looking at other drivers that pin host
On Mon, Aug 21, 2017 at 4:01 PM, Harry Wentland wrote:
> From: Roman Li
>
> Added missing reg shift/masks to soc base
>
> Signed-off-by: Roman Li
> Reviewed-by: Harry Wentland
Acked-by: Alex Deucher
On 2017-08-21 03:45 PM, Dave Airlie wrote:
> Running amd-staging-4.12
>
> Happens a lot, rather annoying.
>
Indeed. Just sent out a patch that should fix it.
Harry
> Dave.
>
> [ 50.552027] [ cut here ]
> [ 50.552070] WARNING: CPU: 5 PID: 1092 at
>
From: Roman Li
Added missing reg shift/masks to soc base
Signed-off-by: Roman Li
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
On Mon, Aug 21, 2017 at 10:21:48PM +0300, Oded Gabbay wrote:
> On Mon, Aug 21, 2017 at 8:39 PM, Jerome Glisse wrote:
> > On Tue, Aug 15, 2017 at 11:00:20PM -0400, Felix Kuehling wrote:
> >> From: Moses Reuben
> >>
> >> v2:
> >> * Renamed
Running amd-staging-4.12
Happens a lot, rather annoying.
Dave.
[ 50.552027] [ cut here ]
[ 50.552070] WARNING: CPU: 5 PID: 1092 at
/home/airlied/devel/kernel/linux-2.6/drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:170
generic_reg_update_ex+0xd4/0x133
On 2017-08-21 01:39 PM, Jerome Glisse wrote:
> On Tue, Aug 15, 2017 at 11:00:20PM -0400, Felix Kuehling wrote:
>> From: Moses Reuben
>>
>> v2:
>> * Renamed ALLOC_MEMORY_OF_SCRATCH to SET_SCRATCH_BACKING_VA
>> * Removed size parameter from the ioctl, it was unused
>> *
On Mon, Aug 21, 2017 at 8:58 AM, Christian König
wrote:
> From: Christian König
>
> When a process is killed we shouldn't submit all waiting jobs, but instead
> clean up as fast as possible.
>
> Signed-off-by: Christian König
On Mon, Aug 21, 2017 at 7:26 AM, Christian König
wrote:
> Ping? Can somebody take a look?
>
> This is an bugfix and I would like to have it upstream before the next merge
> window closes.
Reviewed-by: Alex Deucher
>
> Regards,
> Christian
>
On Mon, Aug 21, 2017 at 8:39 PM, Jerome Glisse wrote:
> On Tue, Aug 15, 2017 at 11:00:20PM -0400, Felix Kuehling wrote:
>> From: Moses Reuben
>>
>> v2:
>> * Renamed ALLOC_MEMORY_OF_SCRATCH to SET_SCRATCH_BACKING_VA
>> * Removed size parameter from the
Further optimizations to the VM trace parser that brings the parse
time of ~3.8M lines of trace data down from >3.5seconds to ~1.08 seconds
on my Carrizo (A12-9800). The goal is to ensure that parsing large
amounts of mappings (for say large games/compute users) is always somewhat
reasonable.
In
On Tue, Aug 15, 2017 at 11:00:20PM -0400, Felix Kuehling wrote:
> From: Moses Reuben
>
> v2:
> * Renamed ALLOC_MEMORY_OF_SCRATCH to SET_SCRATCH_BACKING_VA
> * Removed size parameter from the ioctl, it was unused
> * Removed hole in ioctl number space
> * No more call to
On Sat, Aug 19, 2017 at 12:18 PM, Kuehling, Felix
wrote:
> I'm not sure how dynamic CU masking works. But on a GPU with 64 CUs, a 32-bit
> CU mask (in struct v9_mqd_allocation) seems too small.
Good question even on gfx8. I've got a request out to the hw team.
Alex
>
On Mon, Aug 21, 2017 at 01:31:28PM +0100, Emil Velikov wrote:
> Hi all,
>
> Can anyone skim through this patch?
>
> Thanks
> Emil
>
> On 22 January 2017 at 18:48, Emil Velikov wrote:
> > All one needs is to establish if dev->fd is the flink (primary/card)
> > node,
We need a larger gart for asics that do not support GPUVM on all
engines (e.g., MM) to make sure we have enough space for all
gtt buffers in physical mode. Change the default size based on
the asic type.
Signed-off-by: Alex Deucher
---
Signed-off-by: Tom St Denis
---
src/lib/ring_decode.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
index d659b39b0920..fe29d52e69aa 100644
--- a/src/lib/ring_decode.c
+++
On AI+ platforms some register names are shared between
IP blocks (for instance VM registers). Now we print
out a fuller path to the register in the ring decoding
output.
Signed-off-by: Tom St Denis
---
src/lib/ring_decode.c | 14 ++
1 file changed, 10
From: Christian König
When a process is killed we shouldn't submit all waiting jobs, but instead
clean up as fast as possible.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/scheduler/gpu_scheduler.c | 23 +++
1
Am 21.08.2017 um 14:31 schrieb Emil Velikov:
Hi all,
Can anyone skim through this patch?
Thanks
Emil
On 22 January 2017 at 18:48, Emil Velikov wrote:
All one needs is to establish if dev->fd is the flink (primary/card)
node, rather than use DRM_IOCTL_GET_CLIENT to
Ping? Can somebody take a look?
This is an bugfix and I would like to have it upstream before the next
merge window closes.
Regards,
Christian
Am 18.08.2017 um 17:29 schrieb Christian König:
From: Christian König
Set the shadow flag on the shadow and not the
Am 21.08.2017 um 11:35 schrieb Quan, Evan:
Hi Christian,
On the 1st run, it goes for amdgpu/%s_mec2_2.bin. Then it will goes for
amdgpu/%s_mec2.bin if failed.
So, i did not see any problem with it.
Ah, now I see. The naming of the firmware files is a bit confusing, but
should indeed work.
Hi Christian,
On the 1st run, it goes for amdgpu/%s_mec2_2.bin. Then it will goes for
amdgpu/%s_mec2.bin if failed.
So, i did not see any problem with it.
Actually i talked with firmware guys. There is no change for the firmware
loading way.
The new firmwares depends on a critical
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