Path property is used for userspace to know what MST connector goes to
what actual DRM DisplayPort connector, the tiling property is for tiling
configurations. Not sure what else there is to figure out.
Signed-off-by: Lyude Paul
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 3
Some fixes for things I spotted after trying to look at a bug Jerry Zuo
mentioned to me. Didn't manage to reproduce the bug! But I found these.
Cc: Jerry Zuo
Lyude Paul (2):
drm/amd/dm: Don't forget to attach MST encoders
drm/amd/dm: Understand why attaching path/tile properties are needed
Drive-by fix, this is bound to cause problems somewhere.
Signed-off-by: Lyude Paul
Cc: Jerry Zuo
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/a
On 2018-11-16 4:35 p.m., Alex Deucher wrote:
>> + ring->doorbell_index += 0x400;
> I don't quite understand how this works. Why don't we have to adjust
> the doorbell range registers in the nbio code?
NBIO only looks at the lower 12 bits of the doorbell address. So adding
0
On 2018-11-16 4:35 p.m., Alex Deucher wrote:
> On Fri, Nov 16, 2018 at 2:08 PM Yang, Philip wrote:
>> Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for paging
>> queue will
>> break SRIOV, instead we can reserve and map two doorbell pages for amdgpu,
>> paging
>> queues doorbell
On Fri, Nov 16, 2018 at 2:08 PM Yang, Philip wrote:
>
> Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for paging
> queue will
> break SRIOV, instead we can reserve and map two doorbell pages for amdgpu,
> paging
> queues doorbell index use same index as SDMA gfx queues index but
On 2018-11-16 3:30 p.m., Alex Deucher wrote:
> Looks like a copy paste typo.
>
> Signed-off-by: Alex Deucher
Reviewed-by: Felix Kuehling
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
Looks like a copy paste typo.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c27caa144c57..e409fbf67fe7 100644
--- a/dri
Hi Christian,
Would you review this patch? Just looking at the code, calling
amdgpu_sync_fence with adev=NULL should be OK for us. It's just a bit
unusual compared to amdgpu's usage of this function. We've had this
patch in kfd-staging for a while without problems. If you're OK with
this I'll go a
Setting this allows for display scaling by default
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amd
Before:
We use drm_match_cea_mode() to get the vic for any mode we
want to set, most of the time vic will be different for the new mode.
DC uses memcmp to check if timing changed, in this case DC will
say timing changed and we endup doing a full modeset.
Current:
Now we check if !RMX_OFF and old_
Looks good to me. Reviewed-by: Felix Kuehling
I hope Alex or Christian can also review this in case I'm missing
something about how doorbells are used in amdgpu.
Regards,
Felix
On 2018-11-16 2:08 p.m., Yang, Philip wrote:
> Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for pag
Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for paging queue
will
break SRIOV, instead we can reserve and map two doorbell pages for amdgpu,
paging
queues doorbell index use same index as SDMA gfx queues index but on second
page.
For Vega20, after we change doorbell layout to
On Thu, Nov 15, 2018 at 09:56:51PM +, Kuehling, Felix wrote:
> On Vega20 and other pre-production GPUs, powerplay is not enabled yet.
> Check for NULL pointers before calling pp_funcs function pointers.
>
> Also affects Kaveri.
>
> CC: Joerg Roedel
> Signed-off-by: Felix Kuehling
> ---
> d
Use the define rather than hardcoded value.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index e1ebf770c303..940894e8c67e 10
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Guttula,
Suresh
Sent: Friday, November 16, 2018 1:50:37 AM
To: amd-gfx@lists.freedesktop.org
Cc: Sharma, Deepak; Guttula, Suresh; Agrawal, Akshu
Subject: [PATCH v2 3/3] drm/amd:Enable/Disable NBPS
Hi,
Would you help on it?
-Original Message-
From: amd-gfx On Behalf Of Trigger Huang
Sent: Thursday, November 15, 2018 3:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Trigger
Subject: [PATCH V3] drm/scheduler: Fix bad job be re-processed in TDR
A bad job is the one triggered TDR(
As amd_uvd_resume() accesses the uvd ring, it must be initialised first
or else we trigger errors like:
[5.595963] [drm] Found UVD firmware Version: 1.87 Family ID: 17
[5.595969] [drm] PSP loading UVD firmware
[5.596266] [ cut here ]
[5.596268] ODEBUG: asser
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Chengming Gui
> Sent: Friday, November 16, 2018 4:21 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gui, Jack
> Subject: [PATCH revert] Revert "drm/amdgpu: use GMC v9 KIQ workaround
> only for
With GFXOFF enabled, this patch will cause PCO amdgpu_test failed,
but GFXOFF is necessary for PCO, so revert the patch.
This reverts commit b83761bb0b09ec11c924afe9d88e458cb16a0372.
Signed-off-by: Jack Gui
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
1 file changed, 3 insertions(+), 3
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