On 04.12.2018 20:02, Ville Syrjälä wrote:
> On Tue, Dec 04, 2018 at 08:03:53AM +0100, Andrzej Hajda wrote:
>> On 03.12.2018 22:48, Ville Syrjälä wrote:
>>> On Thu, Nov 29, 2018 at 09:46:16AM +0100, Andrzej Hajda wrote:
Quite late, hopefully not too late.
On 21.11.2018 12:51,
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Aaron Liu
> Sent: Wednesday, December 05, 2018 11:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Aaron
> Subject: [PATCH] drm/amdgpu: both support PCO real/fake rlc fw
>
> For Picasso
PSP only support VMR ring for SRIOV vf since v45 and all commands will
be send to VMR ring for executing.
VMR ring use C2PMSG 101 ~ 103 instead of C2PMSG 64 ~ 71.
Signed-off-by: Xiangliang Yu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1
PSP ring need to be destroy before starting reinit for vf.
This patche move it from hypervisor driver into guest.
Signed-off-by: Xiangliang Yu
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
If PSP FW is running already, driver will not load PSP FW again and skip
it. So psp fw version is not correct if reading it from FW binary file,
need to get right version from register.
Signed-off-by: Xiangliang Yu
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 4 +++-
1 file changed, 3
Hi Ville,
On Tuesday, 4 December 2018 21:13:20 EET Ville Syrjälä wrote:
> On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
> > On 03.12.2018 22:38, Ville Syrjälä wrote:
> >> On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
> >>> On 21.11.2018 19:19, Laurent Pinchart
For Picasso && AM4 SOCKET board, we use picasso_rlc_fake.bin
For Picasso && FP5 SOCKET board, we use picasso_rlc.bin
Judgment method:
PCO AM4: revision >= 0xC8 && revision <= 0xCF
or revision >= 0xD8 && revision <= 0xDF
otherwise is PCO FP5
Change-Id:
On 2018-12-04 4:06 a.m., Christian König wrote:
> Am 03.12.18 um 21:19 schrieb Yang, Philip:
>> Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
>> callback. Enable CONFIG_HMM and CONFIG_HMM_MIRROR as a dependency in
>> DRM_AMDGPU_USERPTR Kconfig.
>>
>> It supports both KFD
Reviewed-by: Oak Zeng
Regards,
Oak
-Original Message-
From: Alex Deucher
Sent: Tuesday, December 4, 2018 2:01 PM
To: amd-gfx list ; Zeng, Oak
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu/si: fix SI after doorbell rework
Ping?
On Sun, Dec 2, 2018 at 9:50 PM Alex Deucher
On Tue, Dec 04, 2018 at 08:46:53AM +0100, Andrzej Hajda wrote:
> On 03.12.2018 22:38, Ville Syrjälä wrote:
> > On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
> >> On 21.11.2018 19:19, Laurent Pinchart wrote:
> >>> Hi Ville,
> >>>
> >>> Thank you for the patch.
> >>>
> >>> On
On Tue, Dec 04, 2018 at 02:00:54PM -0500, Alex Deucher wrote:
> Ping?
Does fix the SI issue (done in bugzilla).
--
Sylvain
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On Tue, Dec 04, 2018 at 08:03:53AM +0100, Andrzej Hajda wrote:
> On 03.12.2018 22:48, Ville Syrjälä wrote:
> > On Thu, Nov 29, 2018 at 09:46:16AM +0100, Andrzej Hajda wrote:
> >> Quite late, hopefully not too late.
> >>
> >>
> >> On 21.11.2018 12:51, Ville Syrjälä wrote:
> >>> On Wed, Nov 21, 2018
Ping?
On Sun, Dec 2, 2018 at 9:50 PM Alex Deucher wrote:
>
> SI does not use doorbells, move asic doorbell init later
> asic check.
>
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=108920
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
> 1 file
On Mon, Dec 3, 2018 at 9:39 PM Zhang, Jerry(Junwei) wrote:
>
> On 12/4/18 12:21 AM, Alex Deucher wrote:
> > Adjust limits for newer polaris variants.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 17
> > +++--
> > 1 file
Thanks, going to take a look tomorrow.
Christian.
Am 04.12.2018 18:28 schrieb "StDenis, Tom" :
This commit causes a regression on my Carrizo running piglit (dmesg
attached)
commit 5786b66c9e3b7b18f3c24566e70cae450969cb14
Refs: v4.20-rc3-498-g5786b66c9e3b
Author: Christian König
AuthorDate:
This commit causes a regression on my Carrizo running piglit (dmesg
attached)
commit 5786b66c9e3b7b18f3c24566e70cae450969cb14
Refs: v4.20-rc3-498-g5786b66c9e3b
Author: Christian König
AuthorDate: Mon Sep 24 13:35:53 2018 +0200
Commit: Christian König
CommitDate: Tue Dec 4 10:22:22 2018
Please re-state the patch subject instead of "Fixed S3 hung issue"
With that fixed, the patch is
Reviewed-by: Leo Liu
On 12/4/18 10:31 AM, Zhu, James wrote:
> Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend,
> to keep adev->vcn.cur_state update. It will fix VCN S3
Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend,
to keep adev->vcn.cur_state update. It will fix VCN S3 hung issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
For the series:
Acked-by: Alex Deucher
On Mon, Dec 3, 2018 at 7:05 PM Kuehling, Felix wrote:
>
> Ping. Any comments, R-b, A-b?
>
> On 2018-11-20 10:07 p.m., Kuehling, Felix wrote:
> > This round adds support for more ROCm memory manager features:
> > * VRAM limit checking to avoid overcommitment
Quoting Chris Wilson (2018-12-04 12:52:15)
> Quoting Christian König (2018-12-04 11:59:39)
> > -static inline bool __dma_fence_is_later(u32 f1, u32 f2)
> > +static inline bool __dma_fence_is_later(u64 f1, u64 f2)
> > {
> > - return (int)(f1 - f2) > 0;
> > + /* This is for backward
Quoting Christian König (2018-12-04 11:59:39)
> -static inline bool __dma_fence_is_later(u32 f1, u32 f2)
> +static inline bool __dma_fence_is_later(u64 f1, u64 f2)
> {
> - return (int)(f1 - f2) > 0;
> + /* This is for backward compatibility with drivers which can only
> handle
> +
在 2018/12/4 19:59, Christian König 写道:
> Implement finding the right timeline point in drm_syncobj_find_fence.
>
> v2: return -EINVAL when the point is not submitted yet.
> v3: fix reference counting bug, add flags handling as well
>
> Signed-off-by: Christian König
> ---
>
在 2018/12/4 19:59, Christian König 写道:
> Use the dma_fence_chain object to create a timeline of fence objects
> instead of just replacing the existing fence.
>
> v2: rebase and cleanup
>
> Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
> ---
> drivers/gpu/drm/drm_syncobj.c | 37
在 2018/12/4 19:59, Christian König 写道:
> This completes "drm/syncobj: Drop add/remove_callback from driver
> interface" and cleans up the implementation a bit.
>
> Signed-off-by: Christian König
Reviewed-by: Chunming Zhou
> ---
> drivers/gpu/drm/drm_syncobj.c | 91
>
在 2018/12/4 19:59, Christian König 写道:
> This reverts commit 9a09a42369a4a37a959c051d8e1a1f948c1529a4.
>
> The whole interface isn't thought through. Since this function can't
> fail we actually can't allocate an object to store the sync point.
>
> Sorry, I should have taken the lead on this
在 2018/12/4 19:59, Christian König 写道:
> Lockless container implementation similar to a dma_fence_array, but with
> only two elements per node and automatic garbage collection.
>
> v2: properly document dma_fence_chain_for_each, add
> dma_fence_chain_find_seqno,
> drop prev reference
在 2018/12/4 19:59, Christian König 写道:
> For a lot of use cases we need 64bit sequence numbers. Currently drivers
> overload the dma_fence structure to store the additional bits.
>
> Stop doing that and make the sequence number in the dma_fence always
> 64bit.
>
> For compatibility with hardware
From: Chunming Zhou
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 37 +
include/drm/drm_syncobj.h | 5 +
2
From: Chunming Zhou
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 90f474f98b6e..316bfc1a6a75 100644
---
Implement finding the right timeline point in drm_syncobj_find_fence.
v2: return -EINVAL when the point is not submitted yet.
v3: fix reference counting bug, add flags handling as well
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 43
From: Chunming Zhou
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
Cc: Chris Wilson
---
From: Chunming Zhou
user mode can query timeline payload.
v2: check return value of copy_to_user
v3: handle querying entry by entry
v4: rebase on new chain container, simplify interface
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
This completes "drm/syncobj: Drop add/remove_callback from driver
interface" and cleans up the implementation a bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 91 ++-
include/drm/drm_syncobj.h | 21 --
2 files changed,
This reverts commit 9a09a42369a4a37a959c051d8e1a1f948c1529a4.
The whole interface isn't thought through. Since this function can't
fail we actually can't allocate an object to store the sync point.
Sorry, I should have taken the lead on this from the very beginning and
reviewed it more
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's not a chain fence.
v3:
For a lot of use cases we need 64bit sequence numbers. Currently drivers
overload the dma_fence structure to store the additional bits.
Stop doing that and make the sequence number in the dma_fence always
64bit.
For compatibility with hardware which can do only 32bit sequences the
comparisons in
On Mon, Dec 03, 2018 at 07:50:53AM -0800, Eric Anholt wrote:
> Boris Brezillon writes:
>
> > On Mon, 3 Dec 2018 16:40:11 +0200
> > Ville Syrjälä wrote:
> >
> >> On Thu, Nov 22, 2018 at 12:23:29PM +0100, Boris Brezillon wrote:
> >> > @@ -924,6 +978,29 @@ struct drm_connector {
> >> >
thanks Rex, done!
I only push it to amd-staging-drm-next, is this enough?
发件人: Zhu, Rex
发送时间: 2018年12月4日 17:26:36
收件人: Yin, Tianci (Rico); Zhang, Jerry; Li, Pauline; Teng, Rui; Liang, Prike;
Zhu, Changfeng; Wang, Kevin(Yang); amd-gfx@lists.freedesktop.org
主题:
Please add Signed-off-by in the patch commit.
Except that,
Patch is
Reviewed-by: Rex Zhu
Best Regards
Rex
From: Yin, Tianci (Rico)
Sent: Tuesday, December 4, 2018 5:01 PM
To: Zhu, Rex; Zhang, Jerry; Li, Pauline; Teng, Rui; Liang, Prike; Zhu,
Changfeng;
Am 03.12.18 um 21:19 schrieb Yang, Philip:
Replace our MMU notifier with hmm_mirror_ops.sync_cpu_device_pagetables
callback. Enable CONFIG_HMM and CONFIG_HMM_MIRROR as a dependency in
DRM_AMDGPU_USERPTR Kconfig.
It supports both KFD userptr and gfx userptr paths.
The depdent HMM patchsets from
hi ,
a lower request system clock may cause gpu hang,
add protection code to avoid this kind of issue,
pls help to review.
thanks!
Rico
From e8f0a05ae172f6e2988148dc925b0bde9943be9a Mon Sep 17 00:00:00 2001
From: tianci yin
Date: Tue, 4 Dec 2018 16:07:18 +0800
Subject: [PATCH]
Fix the return value check which testing the wrong variable
in amdgpu_allocate_static_csa().
Fixes: 7946340fa389 ("drm/amdgpu: Move csa related code to separate file")
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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