On Tue, Dec 18, 2018 at 3:42 PM Michel Dänzer wrote:
> Do you want to make an xf86-video-amdgpu merge request as well? If not,
> I can take care of porting the fix. If you do it, please enable the
Ok Michel, spent some more time. Patch for amdgpu-ddx should be out as
well via good ol' e-mail.
amdgpu_do_pageflip() indexed the flipdata->fb[] array
indexing over config->num_crtc, but the flip completion
routines, e.g., drmmode_flip_handler(), index that array
via the crtc hw id from drmmode_get_crtc_id(crtc).
This is mismatched and causes indexing into the wrong
array slot at flip
Support manual LCLK DPM level switch on Vega20.
Change-Id: I4c6ea6356a90ef6d99f39f7a5cd5cdcb89846d32
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Reviewed-by: Rex Zhu
Reviewed-by: Feifei Xu
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 43 +++
1 file changed, 43
Hi Alex,
I am already using drm_arch_can_wc_memory() set to false.
I will try to bisect...
Regards,
Luís
On Tue, Dec 18, 2018 at 7:03 PM Alex Deucher wrote:
>
> On Tue, Dec 18, 2018 at 8:58 AM Luís Mendes wrote:
> >
> > Hi Christian,
> >
> > I've been using a Sapphire RX 550 and a Sapphire RX
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Zhu, James
Sent: Tuesday, December 18, 2018 4:07:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: jzh...@gmail.com
Subject: [PATCH] drm/amdgpu/uvd:Change uvd ring name convention
Since umr tool can't handle
On Fri, 2018-12-14 at 10:38 +0100, Daniel Vetter wrote:
> On Thu, Dec 13, 2018 at 08:25:34PM -0500, Lyude Paul wrote:
> > Up until now, freeing payloads on remote MST hubs that just had ports
> > removed has almost never worked because we've been relying on port
> > validation in order to stop us
On Fri, 2018-12-14 at 10:32 +0100, Daniel Vetter wrote:
> On Thu, Dec 13, 2018 at 08:25:35PM -0500, Lyude Paul wrote:
> > So that the ports stay around until we've destroyed the connectors, in
> > order to ensure that we don't pass an invalid pointer to any MST helpers
> > once we introduce the
On Fri, 2018-12-14 at 10:29 +0100, Daniel Vetter wrote:
> On Thu, Dec 13, 2018 at 08:25:32PM -0500, Lyude Paul wrote:
> > The current way of handling refcounting in the DP MST helpers is really
> > confusing and probably just plain wrong because it's been hacked up many
> > times over the years
Since umr tool can't handle bracket, change uvd ring name convention.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index
On 12/18/2018 12:09 PM, Kazlauskas, Nicholas wrote:
> On 12/18/18 10:26 AM, sunpeng...@amd.com wrote:
>> From: Leo Li
>>
>> drm_atomic_helper_check_planes() calls the crtc atomic check helpers. In
>> an attempt to better align with the DRM framework, we can move the
>> entire dm_update dance to
On 12/18/2018 10:26 AM, sunpeng...@amd.com wrote:
> From: Leo Li
>
> drm_atomic_helper_check_planes() calls the crtc atomic check helpers. In
> an attempt to better align with the DRM framework, we can move the
> entire dm_update dance to the crtc check helper (since it essentially
> checks
On Tue, Dec 18, 2018 at 3:42 PM Michel Dänzer wrote:
>
>
> Good catch, thanks! Pushed with
>
> Fixes: 740f0850f1e4 "Store FB for each CRTC in drmmode_flipdata_rec"
> Reviewed-by: Michel Dänzer
>
>
> Do you want to make an xf86-video-amdgpu merge request as well? If not,
> I can take care of
On Tue, Dec 18, 2018 at 8:58 AM Luís Mendes wrote:
>
> Hi Christian,
>
> I've been using a Sapphire RX 550 and a Sapphire RX 460 on a custom
> armhf board that runs well with Linux 4.19.9 at least, but now
> starting with Linux kernel 4.20, I'm having a gpu hang, right after
> the console being
The reason I set it to 20 is we reserved 10 doorbells for each sdma engine. See
definition in amdgpu_doorbell.h, line 118. But setting it to 16 is fine as
vega20 only have 8 sdma queues per engine. Since the vega20 doorbell layout
will be reused for future asics. So setting it to 20 will cover
On 12/18/18 10:26 AM, sunpeng...@amd.com wrote:
> From: Leo Li
>
> drm_atomic_helper_check_planes() calls the crtc atomic check helpers. In
> an attempt to better align with the DRM framework, we can move the
> entire dm_update dance to the crtc check helper (since it essentially
> checks that
Thanks Oak for the clarification for Vega10.
For Vega20, 8 user space sdma queues should set doorbell range to 16,
maybe you add gfx and page queue doorbell together to become 20? But gfx
and page queue doorbell is on kernel space, user space sdma queues
doorbell mapping is on user space, they
Thank you Dhiren. So we will also set it to 4 in Linux device driver.
BTW, patch 2 set the doorbell range for vega20 from 2 to 20. With previous
setting of 2, I believe only the first two user space sdma queues work. The
rest 6 queues won't work because the doorbell ringing won't be routed to
Hi Oak,
Windows will set 4 dwords for both sdma0 and 1.
Thanks,
Dhiren
-Original Message-
From: Zeng, Oak
Sent: Tuesday, December 18, 2018 10:52 AM
To: Yang, Philip ; amd-gfx@lists.freedesktop.org; Partap
Singh Rana, Dhirendra ; Deng, Emily
Subject: RE: [PATCH 1/2] drm/amdgpu: Add
Thanks Philip.
For vega10, sdma doorbells are defined to be windows sriov compatible. Two
qwords doorbell are defined for each sdma engine. See amdgpu_doorbell.h line
192. So program nbio sdma doorbell routing range to 4 (dwords) is correct. I am
not sure why previously the doorbell range was
From: Colin Ian King
There are several variables that are defined and never used and hence can
be removed. Remove them. Cleans up clang -Wunused-const-variable warnings:
warning: ‘dvi_hdmi_dongle_signature_str’ defined but not used
warning: ‘dce11_one_lpt_channel_max_resolution’ defined but not
From: Leo Li
drm_atomic_helper_check_planes() calls the crtc atomic check helpers. In
an attempt to better align with the DRM framework, we can move the
entire dm_update dance to the crtc check helper (since it essentially
checks that we can align DC states to what DRM is requesting)
From: Leo Li
In preparation of implementing the CRTC atomic_check helper,
dm_update_crtcs need to operate on single instances.
Move iteration of plane states into atomic_check.
No functional change is intended.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 331
From: Leo Li
In preparation for moving the dm_update dance to the crtc atomic helper,
the lock_and_validation_needed flag need to be de-localized.
Move it to dm_*_states, and update it in the corresponding dm_update*
functions. Add a function to determine if DC global locking is needed by
On 2018-12-17 9:12 p.m., Zeng, Oak wrote:
> Different ASIC has different sdma doorbell range. Add
> a per device sdma_doorbell_range field and initialize
> it.
>
> Change-Id: Idd980db1a72cfb373e24ac23ba3e48bb329ed4ad
> Signed-off-by: Oak Zeng
> ---
>
Hi Christian,
I've been using a Sapphire RX 550 and a Sapphire RX 460 on a custom
armhf board that runs well with Linux 4.19.9 at least, but now
starting with Linux kernel 4.20, I'm having a gpu hang, right after
the console being displayed, but before entering in graphical mode,
when starting X
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Zhu,
James
Sent: Monday, December 17, 2018 9:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: jzh...@gmail.com
Subject: [PATCH v2] drm/amdgpu:Improves robustness of
Am 18.12.18 um 02:42 schrieb Trigger Huang:
When a job is timeout, try to print the related process information
for debugging
Signed-off-by: Trigger Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 4
1 file changed, 4 insertions(+)
diff --git
radeon_do_pageflip() indexed the flipdata->fb[] array
indexing over config->num_crtc, but the flip completion
routines, e.g., drmmode_flip_handler(), index that array
via the crtc hw id from drmmode_get_crtc_id(crtc).
This is mismatched and causes indexing into the wrong
array slot at flip
Hi Wentao,
We need to check psp firmware version here instead of to change
psp_ring_destroy to psp_ring_stop.
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Yu,
>Xiangliang
>Sent: Tuesday, December 18, 2018 3:58 PM
>To: Lou, Wentao ;
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