Adding thick tile mode for Oland to prevent UMD from getting mode value 0
Change-Id: Ic73265c89e075361452830d673dfd8af9c18ab53
Signed-off-by: Tao Zhou
Tested-by: Hui.Deng
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 +++
1 file changed, 19 insertions(+)
diff --git
@Michel Dänzer,
I have reviewed your patch and verified it passed.
I couldn't merge this merge request to your master manually.
The log is below:
aaliu@lnx-aaliu:~/work/brahma/xf86-video-amdgpu-gitlab$ git push origin master
Username for 'https://gitlab.freedesktop.org': aaliu
Password for
From: Yang Wei
Delete superfluous semicolons.
Signed-off-by: Yang Wei
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 8
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git
Hi all,
today I've spotted a warning during hibernation (S4) process while the machine
was attempting to disable all HW and write hibernation image to disk just
before "amdgpu :00:01.0: GPU pci config reset" and disabling EC interrupt.
Besides that everything works just fine. System
From: Marek Olšák
---
src/amdgpu_present.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/amdgpu_present.c b/src/amdgpu_present.c
index ce88bd8f..f4fc6ebd 100644
--- a/src/amdgpu_present.c
+++ b/src/amdgpu_present.c
@@ -271,26 +271,34 @@
Reviewed-by: Marek Olšák
Marek
On Thu, Feb 28, 2019 at 9:59 AM Nicholas Kazlauskas <
nicholas.kazlaus...@amd.com> wrote:
> To help xf86-video-amdgpu and mesa know DC supports updating the
> tiling attributes for a framebuffer per-flip.
>
> Cc: Michel Dänzer
> Cc: Marek Olšák
> Signed-off-by:
From: Leo Li
Summary of change:
* Fix cursor-pageflip interactions on DCN1
* Expose plane alpha-blending support
Aric Cyr (1):
drm/amd/display: 3.2.21
Charlene Liu (1):
drm/amd/display: add HW i2c arbitration with dmcu
David Francis (1):
drm/amd/display: On DCN1, Wait for vupdate on
From: Eric Bernstein
HDMI has TMDS and FRL signal types. Be specific about what is used.
Signed-off-by: Eric Bernstein
Reviewed-by: Nevenko Stupar
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
From: Nicholas Kazlauskas
[Why]
The DRM overlay planes DM exposes support RGBA formats but are currently
forced as fully opaque over whatever they overlay.
[How]
Expose DRM blending mode and alpha properties to userspace.
The overlays exposed support per-pixel pre-multiplied alpha along with
From: Yongqiang Sun
[Why]
field toggle write is actual field sequence write with the same
field name.
[How]
Use REG_UPDATE_SEQ_2 for both sequence write and toggle.
Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Wenjing Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 12 +++-
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 8 ++--
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e755e2f..9b50536 100644
From: David Francis
[Why]
Cursor updates must acquire the pipe control lock to
prevent vupdate from triggering in the middle of cursor
programming. On DCN1 the pipe control lock prevents
pageflips from occurring. This means that a cursor update
right before vupdate can delay a pending pageflip
From: Ken Chalmers
[Why]
At 24 Hz, a frame is 41.7 ms, so a 30 ms wait can (and does often)
timeout.
[How]
Bump timeout from 30 ms to 50 ms.
Signed-off-by: Ken Chalmers
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++--
1 file
From: Josip Pavic
[Why]
Increased power savings are desired for ABM 2.2.
[How]
Reduce the minimum reduction level, the deviation gain and the contrast factor
to allow for more aggressive operation of the algorithm.
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
From: Jun Lei
[why]
Actual breakdown of DPM level varies by SKU (for the same family)
DC needs some ability to ammend pre-silicon numbers
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 4 +++-
1 file changed, 3
From: Jun Lei
[why]
"reference clock" is a very overloaded variable in DC and causes confusion
as there are multiple sources of reference clock, which may be different values
incorrect input values to DML will cause DCHUB to be programmed improperly
and lead to hard to debug underflow issues
From: Yongqiang Sun
[Why]
Current reg update and reg set use same functions and
only delta is update reads reg value and call update function.
[How]
Refactor reg update and reg set functions.
1.Implement different functions for reg update and reg set.
2.Wrap same process to a help function,
From: Dmytro Laktyushkin
Get rid of DV style dml init in favour of the cleaner DC
style.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
.../gpu/drm/amd/display/dc/dml/display_mode_lib.c | 58
From: Wenjing Liu
[why]
Stream update will adjust both info packets and stream params,
need to make sure all things are applied togather.
[how]
add pipe lock during stream update
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c |
From: SivapiriyanKumarasamy
[WHY]
We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want
this interrupt to be fired on PSR transitions such that we enter s0i2
when entering PSR active.
[HOW]
Add code to send the SMU interrupt with the appropriate
staticscreen flag when
From: Eric Bernstein
Cross a TODO item off the list. Cleanup SIGNAL_TYPE_HDMI_FRL, it's
not currently supported.
Signed-off-by: Eric Bernstein
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 1 +
From: Wenjing Liu
[why]
We will not retry when EDID read failure using i2c over aux
[how]
treat i2c over aux failure the same as defer
Signed-off-by: Wenjing Liu
Reviewed-by: David Francis
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc_ddc_types.h | 2 ++
Am 28.02.19 um 18:08 schrieb Russell, Kent:
Add 6 files that return (in bytes):
The total amount of VRAM/visible VRAM/GTT
and the current total used VRAM/visible VRAM/GTT
v2: Split used and total into separate files
Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent
Add 6 files that return (in bytes):
The total amount of VRAM/visible VRAM/GTT
and the current total used VRAM/visible VRAM/GTT
v2: Split used and total into separate files
Change-Id: I0bd702b166b4253887ef76fb1bba8b9aadc7e2c5
Signed-off-by: Kent Russell
---
The issue with the pcie_bw file is that the sent/received information needs to
be obtained simultaneously, so those calculations need to be together and thus
can't be split over two files (aside: I did find an old article about the whole
one-value-per-file thing, where it's described as being a
Wasn't there a long discussion about this timing some months ago... ?
Regards
//Ernst
Den tors 28 feb. 2019 kl 11:47 skrev Xu, Feifei :
>
> Reviewed-by: Feifei Xu
>
> -Original Message-
> From: amd-gfx On Behalf Of Evan Quan
> Sent: Thursday, February 28, 2019 6:32 PM
> To:
On 2019-02-28 1:05 p.m., Michel Dänzer wrote:
> On 2019-02-28 3:52 a.m., Aaron Liu wrote:
>>
>> @@ -900,7 +900,12 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer,
>> CARD32 now, pointer data)
>> delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
>> delta_seq /= 100;
>>
Am 28.02.19 um 17:09 schrieb Kuehling, Felix:
On 2/28/2019 9:56 AM, Christian König wrote:
Am 28.02.19 um 16:32 schrieb Russell, Kent:
Add 3 files that return:
The total amount of VRAM and the current total used VRAM
The total amount of VRAM and the current total used visible VRAM
The total
> -Original Message-
> From: amd-gfx On Behalf Of
> Kuehling, Felix
> Sent: Thursday, February 28, 2019 11:09 AM
> To: Koenig, Christian ; Russell, Kent
> ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Add sysfs files for returning VRAM/GTT
> info
>
> On 2/28/2019
On 2/28/2019 9:56 AM, Christian König wrote:
> Am 28.02.19 um 16:32 schrieb Russell, Kent:
>> Add 3 files that return:
>> The total amount of VRAM and the current total used VRAM
>> The total amount of VRAM and the current total used visible VRAM
>> The total GTT size and the current total of used
Acked-by: Alex Deucher
> -Original Message-
> From: amd-gfx On Behalf Of
> Nicholas Kazlauskas
> Sent: Thursday, February 28, 2019 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Michel Dänzer ; Kazlauskas, Nicholas
> ; Marek Olšák
> Subject: [PATCH] drm/amdgpu: Bump amdgpu version
Am 28.02.19 um 16:32 schrieb Russell, Kent:
Add 3 files that return:
The total amount of VRAM and the current total used VRAM
The total amount of VRAM and the current total used visible VRAM
The total GTT size and the current total of used GTT
Each returns 2 integers, total and used, in bytes
> -Original Message-
> From: amd-gfx On Behalf Of Evan
> Quan
> Sent: Thursday, February 28, 2019 5:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan
> Subject: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20
>
> This is needed for the new SMC firmwares only.
>
>
Hi Alex,
May you help take a look? It is not merged into amd-staging-drm-next
yet, maybe missing code-review+2, it was done automatically after code
review for other patch.
http://git.amd.com:8080/c/brahma/ec/linux/+/206711
Regards,
Philip
On 2019-02-28 6:51 a.m., Michel Dänzer wrote:
>
> [
From: Chris Wilson
[ Upstream commit 6e11ea9de9576a644045ffdc2067c09bc2012eda ]
amdgpu only uses shared-fences internally, but dmabuf importers rely on
implicit write hazard tracking via the reservation_object.fence_excl.
For example, the importer use the write hazard for timing a page flip to
From: Alex Deucher
[ Upstream commit dc14eb12f6bb3e779c5461429c1889a339c67aab ]
Add missing power_average to visible check for power
attributes for APUs. Was missed before.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Philip Yang
[ Upstream commit 0a5f49cbf9d6ad3721c16f8a6d823363ea7a160f ]
amdgpu_vm_get_task_info is called from interrupt handler and sched timeout
workqueue, we should use irq version spin_lock to avoid deadlock.
Signed-off-by: Philip Yang
Reviewed-by: Christian König
Signed-off-by:
From: Jay Cornwall
[ Upstream commit 12292519d919ecde92e7e7c8acbcdb9f0c7c6013 ]
Fixes doorbell reflection on Vega20.
Change-Id: I0495139d160a9032dff5977289b1eec11c16f781
Signed-off-by: Jay Cornwall
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Huang Rui
[ Upstream commit 7e4545d372b560df10fa47281ef0783a479ce435 ]
This patch fixes the incorrect external id that kernel reports to user mode
driver. Raven2's rev_id is starts from 0x8, so its external id (0x81) should
start from rev_id + 0x79 (0x81 - 0x8). And Raven's rev_id should
From: Alex Deucher
[ Upstream commit dc14eb12f6bb3e779c5461429c1889a339c67aab ]
Add missing power_average to visible check for power
attributes for APUs. Was missed before.
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
From: Alex Deucher
[ Upstream commit afeff4c16edaa6275b903f82b0561406259aa3a3 ]
Check if the device is root rather before attempting to see what
speeds the pcie port supports. Fixes a crash with pci passthrough
in a VM.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366
Reviewed-by:
From: Chris Wilson
[ Upstream commit 6e11ea9de9576a644045ffdc2067c09bc2012eda ]
amdgpu only uses shared-fences internally, but dmabuf importers rely on
implicit write hazard tracking via the reservation_object.fence_excl.
For example, the importer use the write hazard for timing a page flip to
To help xf86-video-amdgpu and mesa know DC supports updating the
tiling attributes for a framebuffer per-flip.
Cc: Michel Dänzer
Cc: Marek Olšák
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Hi Aaron,
thanks for the patch. xf86-video-amdgpu now uses GitLab merge requests
for patch submission and review:
https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests
That said, comments on the patch below:
On 2019-02-28 3:52 a.m., Aaron Liu wrote:
> The hang happened
It's pretty noisy:
In file included from ./include/linux/list.h:9,
from ./include/linux/agp_backend.h:33,
from ./include/drm/drmP.h:35,
from drivers/gpu/drm//amd/amdgpu/amdgpu_kms.c:28:
drivers/gpu/drm//amd/amdgpu/amdgpu_kms.c: In function
[ Dropping Jérôme and the linux-mm list ]
On 2019-02-27 7:48 p.m., Yang, Philip wrote:
> Hi Alex,
>
> Pushed, thanks.
>
> mm/hmm: use reference counting for HMM struct
Thanks, but I'm not seeing it yet. Maybe it needs some special
treatment, because it's not a DRM code change?
--
Earthling
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Thursday, February 28, 2019 6:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 1/2] drm/amd/powerplay: correct power reading on fiji
Set sampling period as 500ms to provide a
Ackced-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Thursday, February 28, 2019 6:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH 2/2] drm/amd/powerplay: override duty cycle on Vega20
This is needed for the new SMC firmwares only.
This is needed for the new SMC firmwares only.
Change-Id: I5934e5161ec53c1dd73cb1542ef6b738ad2e620c
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 16
drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h | 3 ++-
2 files changed, 18 insertions(+),
Set sampling period as 500ms to provide a smooth power
reading output. Also, correct the register for power
reading.
Change-Id: I13935f3e7fcd026d34aa6a68cf7f683dc6785ab7
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 +++---
1 file changed, 3 insertions(+), 3
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Cui, Flora
Sent: 2019年2月28日 13:44
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Cui, Flora
Subject: [PATCH libdrm 2/2] tests/amdgpu: add memcpy dispatch test
add memcpy
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