Max Link Width's full mask is 0x3f,
and it's highest bit express X16.
Signed-off-by: Chengming Gui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
data is a pointer. So add * back.
Fixes: ad258a5c ("drm/amdgpu: add human readable debugfs control support")
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
support per device test mask. Skip inject test on non-server card.
Signed-off-by: xinhui pan
Reviewed-by: Feifei Xu
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
---
tests/amdgpu/ras_tests.c | 71 +++-
1 file changed, 63 insertions(+), 8 deletions(-)
Signed-off-by: xinhui pan
Reviewed-by: Feifei Xu
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
---
include/drm/amdgpu_drm.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index be84e43c..ecd5fb21 100644
---
Signed-off-by: xinhui pan
Reviewed-by: Feifei Xu
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
---
tests/amdgpu/Makefile.am | 3 +-
tests/amdgpu/amdgpu_test.c | 11 +
tests/amdgpu/amdgpu_test.h | 22 ++
tests/amdgpu/meson.build | 2 +-
tests/amdgpu/ras_tests.c | 594
Dear Harry,
On 18.03.19 21:55, Wentland, Harry wrote:
On 2019-03-08 4:11 a.m., Michel Dänzer wrote:
On 2019-03-06 5:35 p.m., Paul Menzel wrote:
On 03/06/19 15:55, Michel Dänzer wrote:
On 2019-03-06 1:41 p.m., Paul Menzel wrote:
On 03/05/19 20:07, Alex Deucher wrote:
On Tue, Mar 5, 2019
Hello everyone,
My name is Shaobo He and I am a graduate student at University of Utah. I am
using a static analysis tool to search for null pointer dereferences and came
across a potentially invalid memory access in the file
drivers/gpu/drm/radeon/radeon_ttm.c: in function
Hello everyone,
My name is Shaobo He and I am a graduate student at University of Utah. I am
using a static analysis tool to search for null pointer dereferences and came
across a potentially invalid memory accesses in the file
drivers/gpu/drm/radeon/atombios_encoders.c: in function
On 2019-03-08 4:11 a.m., Michel Dänzer wrote:
> On 2019-03-06 5:35 p.m., Paul Menzel wrote:
>> On 03/06/19 15:55, Michel Dänzer wrote:
>>> On 2019-03-06 1:41 p.m., Paul Menzel wrote:
On 03/05/19 20:07, Alex Deucher wrote:
> On Tue, Mar 5, 2019 at 1:16 PM Paul Menzel wrote:
>>
On 2019-03-14 12:53 p.m., Nicholas Kazlauskas wrote:
> We want DRM planes to be initialized in the following order:
>
> - primary planes
> - overlay planes
> - cursor planes
>
> to support existing userspace expectations for plane z-ordering. This
> means that we also need to register CRTCs
On my system, programs like Blender have very noticeable input lag that
makes it hard to use. It happens no matter what Linux distro or
compositor I try. At first the only fix that seemed to work was
installing the proprietary amdgpu-pro drivers on Ubuntu. Running "env
LIBGL_DRI3_DISABLE=1
On 3/18/19 1:25 PM, Kuehling, Felix wrote:
> Alex already applied an equivalent patch by Colin King (attached for
> reference).
>
Oh, that's great. Good to know.
Thanks, Felix.
--
Gustavo
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
Assign return value of function amdgpu_bo_sync_wait() to variable ret
for its further check.
Addresses-Coverity-ID: 1443914 ("Logically dead code")
Fixes: c60cd590cb7d ("drm/amdgpu: Replace ttm_bo_wait with amdgpu_bo_sync_wait")
Signed-off-by: Gustavo A. R. Silva
---
On 18/03/2019 15:17, Alex Deucher wrote:
> On Mon, Mar 18, 2019 at 6:50 AM Klaus Kusche
> wrote:
>
>> Hello,
>>
>> I was unable to find any documentation (neither on the amd side
>> nor on the linux side) giving the maximum number of independent displays
>> supported by the amd polaris GPU's.
>>
On Mon, Mar 18, 2019 at 1:50 PM Klaus Kusche
wrote:
>
>
> On 18/03/2019 15:17, Alex Deucher wrote:
> > On Mon, Mar 18, 2019 at 6:50 AM Klaus Kusche
> > wrote:
> >
> >> Hello,
> >>
> >> I was unable to find any documentation (neither on the amd side
> >> nor on the linux side) giving the maximum
Alex already applied an equivalent patch by Colin King (attached for
reference).
Regards,
Felix
On 3/18/2019 2:05 PM, Gustavo A. R. Silva wrote:
> Assign return value of function amdgpu_bo_sync_wait() to variable ret
> for its further check.
>
> Addresses-Coverity-ID: 1443914 ("Logically
On 18/03/2019 17:20, Koenig, Christian wrote:
- if (dma_fence_is_signaled(entries[i].fence)) {
+ if (fence)
+ entries[i].fence = fence;
+ else
+ entries[i].fence = dma_fence_get_stub();
+
+ if ((flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE)
On 3/18/19 1:19 PM, Mario Kleiner wrote:
> For throttling to work correctly, we always need a baseline vblank
> count last_flip_vblank that increments at start of front-porch.
>
> This is the case for drm_crtc_vblank_count() in non-VRR mode, where
> the vblank irq fires at start of front-porch
On 3/18/19 1:19 PM, Mario Kleiner wrote:
> During VRR mode we can not allow vblank irq dis-/enable
> transitions, as an enable after a disable can happen at
> an arbitrary time during the video refresh cycle, e.g.,
> with a high likelyhood inside vblank front-porch. An
> enable during front-porch
In VRR mode, proper vblank/pageflip timestamps can only be computed
after the display scanout position has left front-porch. Therefore
delay calls to drm_crtc_handle_vblank(), and thereby calls to
drm_update_vblank_count() and pageflip event delivery, to after the
end of front-porch when in VRR
Am 18.03.19 um 17:59 schrieb Lionel Landwerlin:
> On 15/03/2019 12:09, Chunming Zhou wrote:
>> points array is one-to-one match with syncobjs array.
>> v2:
>> add seperate ioctl for timeline point wait, otherwise break uapi.
>> v3:
>> userspace can specify two kinds waits::
>> a. Wait for time
We want vblank counts and timestamps of flip completion as sent
in pageflip completion events to be consistent with the vblank
count and timestamp of the vblank of flip completion, like in non
VRR mode.
In VRR mode, drm_update_vblank_count() - and thereby vblank
count and timestamp updates - must
For throttling to work correctly, we always need a baseline vblank
count last_flip_vblank that increments at start of front-porch.
This is the case for drm_crtc_vblank_count() in non-VRR mode, where
the vblank irq fires at start of front-porch and triggers DRM core
vblank handling, but it is no
During VRR mode we can not allow vblank irq dis-/enable
transitions, as an enable after a disable can happen at
an arbitrary time during the video refresh cycle, e.g.,
with a high likelyhood inside vblank front-porch. An
enable during front-porch would cause vblank timestamp
updates/calculations
Hi
This series implements properly working vblank and pageflip completion
timestamping for amdgpu in VRR / FreeSync mode.
Now pageflip timestamps for pageflip events always carry the
vblank timestamp of the vblank in which the flip completed,
and the vblank timestamp is as accurate as in fixed
On 15/03/2019 12:09, Chunming Zhou wrote:
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
On Mon, Mar 18, 2019 at 6:50 AM Klaus Kusche
wrote:
>
>
> Hello,
>
> I was unable to find any documentation (neither on the amd side
> nor on the linux side) giving the maximum number of independent displays
> supported by the amd polaris GPU's.
>
> The old cape verde GPU supports six displays,
>
On Mon, Mar 18, 2019 at 6:14 AM Christian König
wrote:
>
> We only need to clear the bit in a 32bit integer.
>
> This fixes a crah on ARM64 and PPC64LE caused by
> "drm/amdgpu: update the vm invalidation engine layout V2"
>
> Signed-off-by: Christian König
> Cc: sta...@vger.kernel.org
Acked-by:
Hello,
I was unable to find any documentation (neither on the amd side
nor on the linux side) giving the maximum number of independent displays
supported by the amd polaris GPU's.
The old cape verde GPU supports six displays,
either with cards having 6 separate DP outputs or with MST hubs.
But
Hi everyone,
we currently use kernel 4.14.22 and a RX570. To get max performance we set
power_dpm_force_performance_level to manual, pp_dpm_mclk to 2, and
pp_dpm_sclk to 7.
A 'cat pp_dpm_mclk pp_dpm_sclk' shows:
0: 300Mhz
1: 1000Mhz
2: 1750Mhz *
0: 300Mhz
1: 588Mhz
2: 952Mhz
3: 1041Mhz
4:
We only need to clear the bit in a 32bit integer.
This fixes a crah on ARM64 and PPC64LE caused by
"drm/amdgpu: update the vm invalidation engine layout V2"
Signed-off-by: Christian König
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
1 file changed, 1
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