From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 54 ++
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
From: Jack Xiao
Allocate CSA for the given sdma ring.
Acked-by: Hawking Zhang
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 27
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 2 +-
2 files changed, 28 insertions(+),
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index
From: Jack Xiao
For new submission ib, CE/DE metadata should be programmed to 0;
for partially execution ib, CE/DE metadata should be restored.
Acked-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 57 +++--
1 file changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
From: Rex Zhu
can preempt the ring by setting cond_exec to false
Acked-by: Hawking Zhang
Signed-off-by: Rex Zhu
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
From: Hawking Zhang
rlc autoload is supported since navi10
Signed-off-by: Hawking Zhang
Acked-by: Alex Deucher
Reviewed-by: Jack Xiao
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Jack Xiao
In mcbp unit test, the test should detect the preempted job which may
be a partial execution ib and mark it as preempted; so that the gfx
block can correctly generate PM4 frame.
Reviewed-by: Hawking Zhang
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
From: Jack Xiao
The trailing fence for ring is used to track the
completion of preemption.
Acked-by: Hawking Zhang
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10
From: "Le.Ma"
Signed-off-by: Le.Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
.../include/ivsrcid/gfx/irqsrcs_gfx_10_1.h| 53 +++
1 file changed, 53 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_10_1.h
From: "Le.Ma"
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC.
Signed-off-by: Le.Ma
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 5 +
1 file changed, 5 insertions(+)
diff
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
.../include/ivsrcid/sdma0/irqsrcs_sdma0_5_0.h | 43 ++
.../include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h | 44 +++
2 files changed, 87 insertions(+)
create
From: Hawking Zhang
Since from navi10, the tmr_size should be decided by psp sos according to
toc header. Driver should issue LOAD_TOC to psp sos to get the tmr_size needed.
The allocation of tmr_size then should be done only when sos/sysdrv loading
completed
Accordingly, asd_init also move to
From: "Le.Ma"
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware
autoloading new feature in gfx10.
This flag can be leveraged for future engines that need autoload fw.
Signed-off-by: Le.Ma
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex
From: Huang Rui
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
From: Hawking Zhang
GMC in the GPU memory controller.
v1: add place holder and initial basic implementation (Ray)
v2: retire unused amdgpu_gart_set_defaults (Hawking)
v3: re-work get_vm_pde function (Hawking)
v4: replace legacy amdgpu_vram/gtt_location with
amdgpu_gmc_vram/gtt_location
From: Tao Zhou
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now.
Will enable it when psp 11.0 firmware is available.
Signed-off-by: Tao Zhou
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
From: Hawking Zhang
v2: update (Alex)
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
.../amd/include/ivsrcid/vcn/irqsrcs_vcn_2_0.h | 32 +++
1 file changed, 32 insertions(+)
create mode 100644
From: Hawking Zhang
psp_firmware_header_v1_1 is used for psp sos with build-in toc
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 31 +++--
2 files
From: Hawking Zhang
Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes
minus sos_size_bytes actually is not sys_bin_size.
Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and
navi10 (psp_firmware_header_v1_1)
Signed-off-by: Hawking Zhang
From: Hawking Zhang
RLC autoload is supported since from Navi10
Signed-off-by: Hawking Zhang
Acked-by: Alex Deucher
Reviewed-by: Jack Xiao
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Hawking Zhang
This is to differentiate rlc backdoor autoload from rlc
frontdoor autoload
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Hawking Zhang
When autoload is enabled, there is no need to load mec jt,
RLC will handle it automatically
Signed-off-by: Hawking Zhang
Acked-by: Alex Deucher
Reviewed-by: Jack Xiao
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
From: Huang Rui
This patch loades smc ucode at first with psp while rlc auto load is supported
on navi10.
Signed-off-by: Huang Rui
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 35 -
1 file changed, 28
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 24 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 +
2 files changed, 25 insertions(+)
diff --git
From: Hawking Zhang
v1: add place holder and initial functions (Ray)
v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang Rui
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
From: Jack Xiao
Enable athub2 clock gating and light sleep
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 +
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index
From: Hawking Zhang
Instead of putting toc into driver source code, the toc will
be part of psp_sos fw. Driver need to get and parse it from
psp fw
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 93
From: Hawking Zhang
IH is the interrupt handler block.
v1: add initial ih support (Ray)
v2: add dummy prescreen iv function for navi10 (Hawking)
v3: squash in additional updates (Alex)
Signed-off-by: Huang Rui
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
From: Hawking Zhang
Table Of Content (TOC) is used by RLC to auto load gc firmwares.
PSP need to parse the toc to calculate the tmr size needed and
load gc firmwares to tmr for RLC to auto load them finally
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
From: Hawking Zhang
To differentiate the mtypes across asics.
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c| 2 +-
drivers/gpu/drm/amd/include/ivsrcid/{ =>
From: Jack Xiao
Due to GCR change from navi10, the PTE encoding of PRT
needs change VSCTL = 0 (was 0XX1X).
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++
From: Hawking Zhang
v1: add place holder and initial basic functions (Ray)
v2: replace the refernce to legacy mc structure with gmc structure
remove the direct use of gart.table_addr (Hawking)
v3: switch to use amdgpu_gmc_pd_addr (Hawking)
v4: squash in updates (Alex)
Signed-off-by: Huang
From: Leo Liu
For Navi10 VCN2.0, the engine supports Doorbell
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
From: Hawking Zhang
Driver will get channel_number and channel_width from
vram_info table, then calculate vram_width by multiply
channel_number by channel_width
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
From: Hawking Zhang
nbio handles bus io functionality.
v1: add place holder and initial basic nbio v2.3 functions (Ray)
v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking)
v3: squash in updates (Alex)
Signed-off-by: Huang Rui
Signed-off-by: Hawking Zhang
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Reviewed-by: Alex Deucher
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 42 ++
From: Huang Rui
Header for CP structures (MQD, etc.)
V2: squash in updates
Signed-off-by: Huang Rui
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/v10_structs.h | 1258 +
1 file changed, 1258 insertions(+)
create mode 100644
From: Hawking Zhang
A pm4 header for Navi. PM4 is the packet format used
by the compute and gfx engines.
Signed-off-by: Huang Rui
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nvd.h | 418
From: Jack Xiao
CP introduced a special unmap_queues packet for gfx preemtion.
Acked-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11
From: Hawking Zhang
The MTYPE filed moves from bits 58:57 to 50:48 for NV10
And the size of MTYPE field is now 3bits
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++--
From: Hawking Zhang
move common code to amdgpu_gfx_enable_kcq,so
this function can be shared with gfx8 and gfx9
Signed-off-by: Hawking Zhang
Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Reviewed-by: Alex Deucher
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 35 -
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git
From: Hawking Zhang
Navi10 has 2 gfx pipe and need to enable gfx eop interrupt
per pipe, instead of enable eop int for all gfx pipes at one
time.
Signed-off-by: Hawking Zhang
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++-
From: Hawking Zhang
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/
DS (Deep Sleep)/SD (Shut Down) modes are supported. However,
only one of these modes can be enabled at one time.
There is no dynamic power mode switch support. clock/power gating
has to be disabled before making
From: Jack Xiao
VDDGFX requires gfx queue to be installed via MAP_QUEUES packet.
Hence, enable async gfx ring by default.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Hawking Zhang
The function now will create mqd bos for both gfx queue and compute queue
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Reviewed-by: Alex Deucher
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Reviewed-by: Alex Deucher
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 8
1 file changed, 8 insertions(+)
diff --git
From: Rex Zhu
so can be shared with gfx8 and gfx9
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 19 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
2 files changed,
From: Hawking Zhang
gfx10 allows to only upload ce jumptable while save the whole
ce image at gtt memory.
v2: program CP_CE_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create ce fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang
From: Hawking Zhang
gfx10 allows to only upload me jumptable while save the whole
me image at gtt memory.
v2: program CP_ME_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create me fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang
From: Hawking Zhang
gfx10 allows to only upload pfp jumptable while save the whole
pfp image at gtt memory.
v2: program CP_PFP_IC_BASE_CNTL to default value
v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo
v4: split common code from gfx10 code
Signed-off-by: Hawking Zhang
From: Hawking Zhang
currently, amdgpu will owns the first gfx queue of each pipe
they are:
me:0 pipe:0 queue:0
me:0 pipe:1 queue:0
Signed-off-by: Hawking Zhang
Reviewed-by: Jack Xiao
Reviewed-by: Alex Deucher
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
From: Rex Zhu
kiq can support 4 pm4 scheduler packets
set_resource, map_queues, unmap_queues, query_status.
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Rex Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 20
1 file
From: Hawking Zhang
vram_type is saved in member vram_module[0].memory_type
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 7 +++
1 file changed, 7 insertions(+)
diff
From: Huang Rui
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
From: Huang Rui
Clear state for gfx pipe.
v2: squash in updates
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/clearstate_gfx10.h | 975 ++
1 file changed, 975 insertions(+)
create
From: Hawking Zhang
For printing vram type.
Signed-off-by: Hawking Zhang
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
From: Hawking Zhang
two new members that specific for navi10 are included in v2_0:
num_sc_per_sh and num_packer_per_sc
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 6 ++
1 file changed, 6 insertions(+)
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/include/navi10_ip_offset.h| 855 ++
drivers/gpu/drm/amd/include/soc15_hw_ip.h | 4 +-
2 files changed, 858 insertions(+), 1 deletion(-)
create mode 100644
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
From: Huang Rui
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index
From: Huang Rui
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
include/uapi/drm/amdgpu_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index
From: Huang Rui
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
include/drm/amd_asic_type.h| 1 +
2 files changed, 2 insertions(+)
diff --git
From: Hawking Zhang
The two members are used to cache the values from gpu_info fw accordingly
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Hawking Zhang
Update mappings for Navi10.
Signed-off-by: Hawking Zhang
Reviewed-by: Alex Deucher
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 40
1 file changed, 40 insertions(+)
diff --git
From: Hawking Zhang
Updated tables for Navi10.
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/atomfirmware.h | 188 -
1 file changed, 180 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
Hi,
This patch set adds support for Navi10 asics to amdgpu. This includes
support for:
- Core driver support
- Displays (DCN2)
- GFX and compute (GFX10)
- System DMA (SDMA 5)
- Multimedia decode and encode (VCN2)
- Power management
The new register headers are huge, so I have not sent them out.
Looks good to me. One cosmetic comment inline. With that fixed this
patch is Reviewed-by: Felix Kuehling
On 2019-06-14 12:51 p.m., StDenis, Tom wrote:
> On 32-bit hosts mem->num_pages is 32-bits and can overflow
> when shifted. Add a cast to avoid this.
>
> Signed-off-by: Tom St Denis
> ---
ping?
On Fri, Jun 14, 2019 at 12:51 PM StDenis, Tom wrote:
> On 32-bit hosts mem->num_pages is 32-bits and can overflow
> when shifted. Add a cast to avoid this.
>
> Signed-off-by: Tom St Denis
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 8 +---
> 1 file changed, 5
On 2019/06/14, Daniel Vetter wrote:
> Split out to make the functional changes stick out more.
>
Since this patch flew-by, as standalone one (intentionally or not) I'd
add, anything vaguely like:
"Core users of DRIVER_PRIME were removed from core with prior patches."
HTH
Emil
A quick guide to the different tags:
Signed-off-by: I'm somehow responsible that the code is in the mainline
tree. E.g. either the Author of a patch or some maintainer who forwarded
the stuff to Linus.
Tested-by: I tested the code and found it working good.
Reviewed-by: I'm familiar with both
On Mon, Jun 17, 2019 at 09:57:36AM -0700, Evgenii Stepanov wrote:
> On Mon, Jun 17, 2019 at 6:56 AM Catalin Marinas
> wrote:
> > On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote:
> > > From: Catalin Marinas
> > >
> > > It is not desirable to relax the ABI to allow tagged user
On Mon, Jun 17, 2019 at 6:56 AM Catalin Marinas wrote:
>
> On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote:
> > From: Catalin Marinas
> >
> > It is not desirable to relax the ABI to allow tagged user addresses into
> > the kernel indiscriminately. This patch introduces a prctl()
On 17/06/2019 14:56, Catalin Marinas wrote:
> On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote:
>> From: Catalin Marinas
>>
>> It is not desirable to relax the ABI to allow tagged user addresses into
>> the kernel indiscriminately. This patch introduces a prctl() interface
>> for
Split out to make the functional changes stick out more.
v2: amdgpu gained DRIVER_SYNCOBJ_TIMELINE.
v3: amdgpu lost DRIVER_SYNCOBJ_TIMELINE.
v4: Don't add a space in i915_drv.c (Sam)
Cc: Sam Ravnborg
Reviewed-by: Eric Anholt
Signed-off-by: Daniel Vetter
Cc: amd-gfx@lists.freedesktop.org
Cc:
Thanks, I need to get familiar with all of the tags
Kent
From: Deucher, Alexander
Sent: Monday, June 17, 2019 11:24 AM
To: Russell, Kent ; Alex Deucher ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init
I'll make that a
I'll make that a tested-by. Thanks!
Alex
From: Russell, Kent
Sent: Monday, June 17, 2019 11:14 AM
To: Alex Deucher; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init
This also
This also worked. I don't think that I'm qualified enough to RB it, but you can
add my
Verified-By: Kent Russell
Kent
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Monday, June 17, 2019 10:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject:
Applied this and the dc patch.
Thanks!
Alex
On Mon, Jun 17, 2019 at 10:07 AM Markus Elfring wrote:
>
> From: Markus Elfring
> Date: Mon, 17 Jun 2019 14:24:14 +0200
>
> The memory was set to zero already by a call of the function “kzalloc”.
> Thus remove an extra call of the function “memset”
On Mon, Jun 17, 2019 at 10:45 AM Geert Uytterhoeven
wrote:
>
> "git diff" says:
>
> \ No newline at end of file
>
> after modifying the file.
>
> Signed-off-by: Geert Uytterhoeven
Applied. thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/modules/power/Makefile | 2 +-
> 1 file changed,
On Mon, Jun 17, 2019 at 8:57 AM Arnd Bergmann wrote:
>
> When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we
> store uninitialized data in a register, as gcc points out:
>
> drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start':
>
Thanks Alex, I am testing it out now.
Kent
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Monday, June 17, 2019 10:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: wait to fetch the vbios until after common init
We need the
On Mon, Jun 17, 2019 at 4:41 PM Sam Ravnborg wrote:
> On Mon, Jun 17, 2019 at 02:38:55PM +0200, Arnd Bergmann wrote:
> > Some randconfig builds fail to compile the dcn10 code because of
> > a missing declaration:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
> >
We need the asic_funcs set for the get rom callbacks in some
cases.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 --
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Hi Arnd.
On Mon, Jun 17, 2019 at 02:38:55PM +0200, Arnd Bergmann wrote:
> Some randconfig builds fail to compile the dcn10 code because of
> a missing declaration:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
> function 'dcn10_apply_ctx_for_surface':
>
On Mon, Jun 17, 2019 at 7:08 AM Russell, Kent wrote:
>
> The issue was limited to one specific model of MI25, I'll see if I can get
> access to that later today and try your patch out. Thank you Emily!
Where is the crash happening in amdgpu_bios.c? What pointer is NULL?
Presumably it's one of
"git diff" says:
\ No newline at end of file
after modifying the file.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/amd/display/modules/power/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile
On Wed, Jun 12, 2019 at 01:43:20PM +0200, Andrey Konovalov wrote:
> From: Catalin Marinas
>
> It is not desirable to relax the ABI to allow tagged user addresses into
> the kernel indiscriminately. This patch introduces a prctl() interface
> for enabling or disabling the tagged ABI with a global
When df_v3_6_pmc_get_ctrl_settings() fails for some reason, we
store uninitialized data in a register, as gcc points out:
drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function 'df_v3_6_pmc_start':
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1012:29: error: 'lo_val' may be used
uninitialized in this function
Some randconfig builds fail to compile the dcn10 code because of
a missing declaration:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In
function 'dcn10_apply_ctx_for_surface':
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2378:3:
error: implicit
From: Markus Elfring
Date: Mon, 17 Jun 2019 14:24:14 +0200
The memory was set to zero already by a call of the function “kzalloc”.
Thus remove an extra call of the function “memset” for this purpose.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
From: Markus Elfring
Date: Mon, 17 Jun 2019 13:56:39 +0200
The memory was set to zero already by a call of the function “kzalloc”.
Thus remove an extra call of the function “memset” for this purpose.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
Thanks Emily, this fixed the issue.
Verified-By: Kent Russell
Kent
-Original Message-
From: Deng, Emily
Sent: Sunday, June 16, 2019 11:53 PM
To: Yang, Philip ; Russell, Kent ;
Quan, Evan ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Need to set the baco cap before
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