RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

Reviewed-by: Jack Gui -Original Message- From: Wang, Kevin(Yang) Sent: Friday, July 19, 2019 11:46 AM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Quan, Evan ; Huang, Ray ; Xu, Feifei ; Gui, Jack ; Wang, Kevin(Yang) Subject: [PATCH] drm/amd/powerplay: custom peak clock freq

Re: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

Comment inline From: Quan, Evan Sent: Friday, July 19, 2019 1:03 PM To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Huang, Ray ; Xu, Feifei ; Gui, Jack Subject: RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

Comment inline > -Original Message- > From: Wang, Kevin(Yang) > Sent: Friday, July 19, 2019 11:46 AM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth ; Quan, Evan > ; Huang, Ray ; Xu, Feifei > ; Gui, Jack ; Wang, Kevin(Yang) > > Subject: [PATCH] drm/amd/powerplay: custom peak

RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

With this change, all the below requests have the same sclk and mclk values on navi10 XT. Is it expected? enum amd_dpm_forced_level { AMD_DPM_FORCED_LEVEL_AUTO = 0x1, AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, AMD_DPM_FORCED_LEVEL_LOW = 0x4, AMD_DPM_FORCED_LEVEL_HIGH =

[PATCH AUTOSEL 4.19 029/101] drm/amd/display: fix compilation error

From: Hariprasad Kelam [ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ] this patch fixes below compilation error drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_apply_ctx_for_surface’:

[PATCH AUTOSEL 4.19 010/101] drm/amd/display: Fill prescale_params->scale for RGB565

From: Nicholas Kazlauskas [ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ] [Why] An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565 formats on DCE since the prescale_params->scale wasn't being filled. Found by a dmesg-fail when running the

[PATCH AUTOSEL 4.19 011/101] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

From: Tiecheng Zhou [ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ] it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal

[PATCH AUTOSEL 4.19 026/101] drm/amd/display: Always allocate initial connector state state

From: Nicholas Kazlauskas [ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ] [Why] Unlike our regular connectors, MST connectors don't start off with an initial connector state. This causes a NULL pointer dereference to occur when attaching the bpc property since it tries to modify

[PATCH AUTOSEL 4.19 014/101] drm/amdkfd: Fix sdma queue map issue

From: Oak Zeng [ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ] Previous codes assumes there are two sdma engines. This is not true e.g., Raven only has 1 SDMA engine. Fix the issue by using sdma engine number info in device_info. Signed-off-by: Oak Zeng Reviewed-by: Felix

[PATCH AUTOSEL 4.19 012/101] drm/amd/display: Disable ABM before destroy ABM struct

From: Paul Hsieh [ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ] [Why] When disable driver, OS will set backlight optimization then do stop device. But this flag will cause driver to enable ABM when driver disabled. [How] Send ABM disable command before destroy ABM construct

[PATCH AUTOSEL 4.19 013/101] drm/amdkfd: Fix a potential memory leak

From: Oak Zeng [ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ] Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails. Signed-off-by: Oak Zeng Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin ---

[PATCH AUTOSEL 5.1 042/141] drm/amd/display: fix compilation error

From: Hariprasad Kelam [ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ] this patch fixes below compilation error drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_apply_ctx_for_surface’:

[PATCH AUTOSEL 5.1 038/141] drm/amd/display: Always allocate initial connector state state

From: Nicholas Kazlauskas [ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ] [Why] Unlike our regular connectors, MST connectors don't start off with an initial connector state. This causes a NULL pointer dereference to occur when attaching the bpc property since it tries to modify

[PATCH AUTOSEL 5.1 027/141] drm/amd/display: Increase Backlight Gain Step Size

From: Eryk Brol [ Upstream commit e25228b02e4833e5b0fdd262801a2ae6cc72b39d ] [Why] Some backlight tests fail due to backlight settling taking too long. This happens because the step size used to change backlight levels is too small. [How] 1. Change the size of the backlight gain step size 2.

[PATCH AUTOSEL 5.1 040/141] drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

From: Samson Tam [ Upstream commit 233d87a579b8adcc6da5823fa507ecb6675e7562 ] [Why] Found issue in EDID Emulation where if we connect a display using a passive HDMI-DP dongle, disconnect it and then try to emulate a display using DP, we could not see 4K modes. This was because on a

[PATCH AUTOSEL 5.1 026/141] drm/amd/display: CS_TFM_1D only applied post EOTF

From: Krunoslav Kovac [ Upstream commit 6ad34adeaec5b56a5ba90e90099cabf1c1fe9dd2 ] [Why] There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger than in regular case when it's actually needed. This leads to

[PATCH AUTOSEL 5.1 019/141] drm/amdkfd: Fix a potential memory leak

From: Oak Zeng [ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ] Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails. Signed-off-by: Oak Zeng Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin ---

[PATCH AUTOSEL 5.1 015/141] drm/amdgpu: Reserve shared fence for eviction fence

From: Felix Kuehling [ Upstream commit dd68722c427d5b33420dce0ed0c44b4881e0a416 ] Need to reserve space for the shared eviction fence when initializing a KFD VM. Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

[PATCH AUTOSEL 5.1 020/141] drm/amdkfd: Fix sdma queue map issue

From: Oak Zeng [ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ] Previous codes assumes there are two sdma engines. This is not true e.g., Raven only has 1 SDMA engine. Fix the issue by using sdma engine number info in device_info. Signed-off-by: Oak Zeng Reviewed-by: Felix

[PATCH AUTOSEL 5.1 018/141] drm/amd/display: Disable ABM before destroy ABM struct

From: Paul Hsieh [ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ] [Why] When disable driver, OS will set backlight optimization then do stop device. But this flag will cause driver to enable ABM when driver disabled. [How] Send ABM disable command before destroy ABM construct

[PATCH AUTOSEL 5.1 014/141] drm/amd/display: Fill prescale_params->scale for RGB565

From: Nicholas Kazlauskas [ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ] [Why] An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565 formats on DCE since the prescale_params->scale wasn't being filled. Found by a dmesg-fail when running the

[PATCH AUTOSEL 5.1 017/141] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

From: Tiecheng Zhou [ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ] it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal

[PATCH AUTOSEL 5.2 057/171] drm/amd/display: fix compilation error

From: Hariprasad Kelam [ Upstream commit 88099f53cc3717437f5fc9cf84205c5b65118377 ] this patch fixes below compilation error drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function ‘dcn10_apply_ctx_for_surface’:

[PATCH AUTOSEL 5.2 053/171] drm/amd/display: Update link rate from DPCD 10

From: Wesley Chalmers [ Upstream commit 53c81fc7875bc2dca358485dac3999e14ec91a00 ] [WHY] Some panels return a link rate of 0 (unknown) in DPCD 0. In this case, an appropriate mode cannot be set, and certain panels will show corruption as they are forced to use a mode they do not support. [HOW]

[PATCH AUTOSEL 5.2 052/171] drm/amd/display: Always allocate initial connector state state

From: Nicholas Kazlauskas [ Upstream commit f04bee34d6e35df26cbb2d65e801adfd0d8fe20d ] [Why] Unlike our regular connectors, MST connectors don't start off with an initial connector state. This causes a NULL pointer dereference to occur when attaching the bpc property since it tries to modify

[PATCH AUTOSEL 5.2 055/171] drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

From: Samson Tam [ Upstream commit 233d87a579b8adcc6da5823fa507ecb6675e7562 ] [Why] Found issue in EDID Emulation where if we connect a display using a passive HDMI-DP dongle, disconnect it and then try to emulate a display using DP, we could not see 4K modes. This was because on a

[PATCH AUTOSEL 5.2 026/171] drm/amd/display: Disable ABM before destroy ABM struct

From: Paul Hsieh [ Upstream commit 1090d58d4815b1fcd95a80987391006c86398b4c ] [Why] When disable driver, OS will set backlight optimization then do stop device. But this flag will cause driver to enable ABM when driver disabled. [How] Send ABM disable command before destroy ABM construct

[PATCH AUTOSEL 5.2 022/171] drm/amd/display: Fill plane attrs only for valid pxl format

From: Roman Li [ Upstream commit 1894478ad1f8fd7366edc5cee49ee9caea0e3d52 ] [Why] In fill_plane_buffer_attributes() we calculate chroma/luma assuming that the surface_pixel_format is always valid. If it's not the case, there's a risk of divide by zero error. [How] Check if format valid before

[PATCH AUTOSEL 5.2 028/171] drm/amdkfd: Fix sdma queue map issue

From: Oak Zeng [ Upstream commit 065e4bdfa1f3ab2884c110394d8b7e7ebe3b988c ] Previous codes assumes there are two sdma engines. This is not true e.g., Raven only has 1 SDMA engine. Fix the issue by using sdma engine number info in device_info. Signed-off-by: Oak Zeng Reviewed-by: Felix

[PATCH AUTOSEL 5.2 021/171] drm/amd/display: Disable cursor when offscreen in negative direction

From: Nicholas Kazlauskas [ Upstream commit e371e19c10a264bd72c2ff1d21e2167b994710d1 ] [Why] When x or y is negative we set the x and y values to 0 and compensate with a positive cursor hotspot in DM since DC expects positive cursor values. When x or y is less than or equal to the maximum

[PATCH AUTOSEL 5.2 019/171] drm/amd/display: fix multi display seamless boot case

From: Anthony Koo [ Upstream commit 4cd75ff096f4ef49c343093b52a952f27aba7796 ] [Why] There is a scenario that causes eDP to become blank if there are multiple displays connected, and the external display is set as the primary display such that the first flip comes to the external display. In

[PATCH AUTOSEL 5.2 035/171] drm/amd/display: Reset planes for color management changes

From: Nicholas Kazlauskas [ Upstream commit 7316c4ad299663a16ca9ce13e5e817b4ca760809 ] [Why] For commits with allow_modeset=false and CRTC degamma changes the planes aren't reset. This results in incorrect rendering. [How] Reset the planes when color management has changed on the CRTC.

[PATCH AUTOSEL 5.2 023/171] drm/amdgpu: Reserve shared fence for eviction fence

From: Felix Kuehling [ Upstream commit dd68722c427d5b33420dce0ed0c44b4881e0a416 ] Need to reserve space for the shared eviction fence when initializing a KFD VM. Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

[PATCH AUTOSEL 5.2 027/171] drm/amdkfd: Fix a potential memory leak

From: Oak Zeng [ Upstream commit e73390d181103a19eec2f25559a0570e9fe0 ] Free mqd_mem_obj it GTT buffer allocation for MQD+control stack fails. Signed-off-by: Oak Zeng Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin ---

[PATCH AUTOSEL 5.2 036/171] drm/amd/display: CS_TFM_1D only applied post EOTF

From: Krunoslav Kovac [ Upstream commit 6ad34adeaec5b56a5ba90e90099cabf1c1fe9dd2 ] [Why] There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger than in regular case when it's actually needed. This leads to

[PATCH AUTOSEL 5.2 037/171] drm/amd/display: Increase Backlight Gain Step Size

From: Eryk Brol [ Upstream commit e25228b02e4833e5b0fdd262801a2ae6cc72b39d ] [Why] Some backlight tests fail due to backlight settling taking too long. This happens because the step size used to change backlight levels is too small. [How] 1. Change the size of the backlight gain step size 2.

[PATCH AUTOSEL 5.2 025/171] drm/amdgpu/sriov: Need to initialize the HDP_NONSURFACE_BAStE

From: Tiecheng Zhou [ Upstream commit fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 ] it requires to initialize HDP_NONSURFACE_BASE, so as to avoid using the value left by a previous VM under sriov scenario. v2: it should not hurt baremetal, generalize it for both sriov and baremetal

[PATCH AUTOSEL 5.2 018/171] drm/amd/display: Fill prescale_params->scale for RGB565

From: Nicholas Kazlauskas [ Upstream commit 1352c779cb74d427f4150cbe779a2f7886f70cae ] [Why] An assertion is thrown when using SURFACE_PIXEL_FORMAT_GRPH_RGB565 formats on DCE since the prescale_params->scale wasn't being filled. Found by a dmesg-fail when running the

RE: [PATCH] drm/amd/powerplay: custom peak clock freq for navi10

> -Original Message- > From: Wang, Kevin(Yang) > Sent: Friday, July 19, 2019 11:46 AM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth ; Quan, Evan > ; Huang, Ray ; Xu, Feifei > ; Gui, Jack ; Wang, Kevin(Yang) > > Subject: [PATCH] drm/amd/powerplay: custom peak clock freq for

[PATCH] drm/amd/powerplay: custom peak clock freq for navi10

1.NAVI10_PEAK_SCLK_XTX1830 Mhz 2.NAVI10_PEAK_SCLK_XT 1755 Mhz 3.NAVI10_PEAK_SCLK_XL 1625 Mhz Change-Id: I48863a9d0e261b9e7778a6c0e4a8762d7c978da6 Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 65 ++-

Re: [PATCH 5/7] drm/amd/display: Use proper enum conversion functions

pe_with_latency(>smu, > - > dc_to_pp_clock_type(clk_type), > + > dc_to_smu_clock_type(clk_type), > _clks)) > return false; > } > -- > 2.22.0 > Gentle ping for review, this is the last remaining warning that I see from amdgpu on next-20190718. Cheers, Nathan

RE: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

Hi Evan, 1, The hack hard code was just served for profile_peak mode and (max_count - 1) level always used for GFX clock, we just force the limit value with data from tool team. 2, The requirement from tool team is to force GFX clock limit value with different SKU’s clocks when enter profile

RE: [PATCH] drm/amdgpu/smu: move fan rpm query into the asic specific code

Reviewed-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: Friday, July 19, 2019 4:28 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/smu: move fan rpm query into the asic > specific code > > On vega20,

Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends

On 2019-07-18 4:47 a.m., Christian König wrote: [snip] >>> This is a corner case we can handle later on. As long as the VM is >>> still alive just allocating page tables again should be sufficient for >>> this. >> Do you mean, instead of migrating page tables back, throwing them away >> and

[pull] amdgpu, amdkfd drm-next-5.3

Hi Dave, Daniel, Fixes for 5.3, mostly for Navi. The following changes since commit 7f963d9f69bf28d639013630da30d7a4c95edd5d: drm/amdgpu/navi10: add uclk activity sensor (2019-07-09 17:43:36 -0500) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux

RE: [PATCH v2] drm/amdgpu: Default disable GDS for compute VMIDs

> -Original Message- > From: Christian König > Sent: Thursday, July 18, 2019 3:14 AM > To: Kuehling, Felix ; Greathouse, Joseph > ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH v2] drm/amdgpu: Default disable GDS for compute > VMIDs > > Am 17.07.19 um 22:09 schrieb Kuehling,

Re: The problem "ring gfx timeout" are experienced yet another AMD GPU Vega 8 user

On Wed, 3 Jul 2019 at 23:57, Marek Olšák wrote: > > It looks like memory corruption. You can try to disable IOMMU in the BIOS. > We disabled IOMMU in the BIOS [1]. And was run the memory check with MemTest86. MemTest86 did not find any memory problems [2]. But previously reported issue with GPU

[PATCH] drm/amdgpu/smu: move fan rpm query into the asic specific code

On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 4 ++-- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 6 +++--- drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 12

[PATCH] Collect all page_base_address bits for pte-further addresses (v2)

The specification says to treat a PTE with the F bit set "like a PDE" which means that all but the lower 6 bits are part of the page base address. Indeed, in the wild a comment came back indicating that we were stripping off bits needed to properly fetch the next PTE. (v2): Only capture excess

Re: [PATCH] drm/radeon: Prefer pcie_capability_read_word()

On Wed, Jul 17, 2019 at 9:08 PM Frederick Lawler wrote: > > Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") > added accessors for the PCI Express Capability so that drivers didn't > need to be aware of differences between v1 and v2 of the PCI > Express Capability. > >

[PATCH] Collect all page_base_address bits for pte-further addresses

The specification says to treat a PTE with the F bit set "like a PDE" which means that all but the lower 6 bits are part of the page base address. Indeed, in the wild a comment came back indicating that we were stripping off bits needed to properly fetch the next PTE. Signed-off-by: Tom St Denis

Re: [PATCH 07/87] drm/amd/display: move bw calc code into helpers

On 2019-07-18 10:49 a.m., Michel Dänzer wrote: > On 2019-07-15 11:19 p.m., sunpeng...@amd.com wrote: >> From: Eric Yang >> >> [Why] >> For better readability and reusability >> >> [How] >> Move snippets of BW calculation code into helpers. >> >> Signed-off-by: Eric Yang >> Reviewed-by: Fatemeh

[PATCH xf86-video-ati] Don't disable page flipping completely with SW cursor

From: Michel Dänzer Even with SW cursor, page flipping can be used while no X cursor is visible. Occurred to me in the context of xorg/xserver#828. (Ported from amdgpu commit 87f41ace4920fd2069794211683659eb25b025a6) Signed-off-by: Michel Dänzer --- src/radeon_kms.c | 8 ++-- 1 file

[PATCH] drm/amdgpu: Remove undefined amdgpu_device_parse_faked_did

From: Leo Li This forward declare was added for no apparent reason. Remove it to resolve this warning: drivers/gpu/drm//amd/amdgpu/amdgpu_device.c:131:13: warning: ‘amdgpu_device_parse_faked_did’ declared ‘static’ but never defined [-Wunused-function] static void

RE: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

Reviewed-by: Zhan Liu -Original Message- From: amd-gfx On Behalf Of sunpeng...@amd.com Sent: Monday, July 15, 2019 5:21 PM To: amd-gfx@lists.freedesktop.org Cc: Li, Sun peng (Leo) ; Kazlauskas, Nicholas Subject: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

Re: [PATCH] drm/amdgpu/: use VCN firmware offset for cache window

Acked-by: Alex Deucher From: amd-gfx on behalf of Liu, Leo Sent: Thursday, July 18, 2019 11:46 AM To: amd-gfx@lists.freedesktop.org Cc: Liu, Leo Subject: [PATCH] drm/amdgpu/: use VCN firmware offset for cache window Since we are using the signed FW now, and

[PATCH] drm/amdgpu: use VCN firmware offset for cache window

Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 --- 1 file changed, 3 deletions(-) diff

[PATCH] drm/amdgpu/: use VCN firmware offset for cache window

Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 --- 1 file changed, 3 deletions(-) diff

[PATCH] drm/amdkfd: Add DID for Navi12

Add device id for KFD Change-Id: I44e8e884d0dc86209de7c0b6f4784d06ee371079 Signed-off-by: shaoyunl --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index

Re: [PATCH 07/87] drm/amd/display: move bw calc code into helpers

On 2019-07-15 11:19 p.m., sunpeng...@amd.com wrote: > From: Eric Yang > > [Why] > For better readability and reusability > > [How] > Move snippets of BW calculation code into helpers. > > Signed-off-by: Eric Yang > Reviewed-by: Fatemeh Darbehani > Acked-by: Leo Li > --- > [...] > > diff

Re: [PATCH] drm/amdgpu: Prefer pcie_capability_read_word()

On Wed, Jul 17, 2019 at 9:08 PM Frederick Lawler wrote: > > Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") > added accessors for the PCI Express Capability so that drivers didn't > need to be aware of differences between v1 and v2 of the PCI > Express Capability. > >

Re: [PATCH 1/3] drm/amd/powerplay: remove mutex lock for smu_handle_task when smu late init

please hold on the mutex changes of patch1 and patch3. We need an overall thought over the smu mutex machinsim. Let us have some internal discussions first. 发件人: amd-gfx 代表 Chengming Gui 发送时间: Thursday, July 18, 2019 6:02:16 PM 收件人:

Re: [PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

1. In navi10_force_clk_levels, i think you need to compare the max level user requested with the peak limit and set the smaller one. 2. can you help me to understand why the change in apply_clock_rules is needed? 发件人: amd-gfx 代表 Chengming Gui 发送时间: Thursday,

RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

> -Original Message- > From: Wang, Kevin(Yang) > Sent: Thursday, July 18, 2019 5:43 PM > To: amd-gfx@lists.freedesktop.org > Cc: Feng, Kenneth ; Quan, Evan > ; Huang, Ray ; Xu, Feifei > ; Wang, Kevin(Yang) > Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format > for

Re: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

reviewed-by: Evan Quan 获取 Outlook for iOS 发件人: Feng, Kenneth 发送时间: Thursday, July 18, 2019 5:49:56 PM 收件人: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 抄送: Quan, Evan ; Huang, Ray ; Xu, Feifei 主题: RE: [PATCH v2] drm/amd/powerplay:

[PATCH 1/3] drm/amd/powerplay: remove mutex lock for smu_handle_task when smu late init

remove mutex lock when smu late init to call smu_handle_task Signed-off-by: Chengming Gui --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index

[PATCH 2/3] drm/amd/powerplay: force sclk limit for peak profile

force different GFX clocks with different SKUs for navi10: XL (other rev_id): 1625MHz XT (F1/C1): 1755MHz XTX(F0/C0): 1830MHz Signed-off-by: Chengming Gui --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 + drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +

[PATCH 3/3] drm/amd/powerplay: add mutex lock to protect dpm context resource

add mutex lock to protect dpm context resource Signed-off-by: Chengming Gui --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 +++-- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 3 files changed, 12 insertions(+), 2

RE: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

Reviewed-by: Kenneth Feng -Original Message- From: Wang, Kevin(Yang) Sent: Thursday, July 18, 2019 5:43 PM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Quan, Evan ; Huang, Ray ; Xu, Feifei ; Wang, Kevin(Yang) Subject: [PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx

[PATCH v2] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

v2: set average clock value on level 1 when current clock equal min or max clock (fine grained dpm support). the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show current dpm freq in sysfs pp_dpm_xxx Change-Id: I14daa6e30c52c89795708ec06660862bb4591036 Signed-off-by: Kevin

Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

Am 18.07.19 um 10:10 schrieb Cui, Flora: 1. skip test if there's no desired ring 2. clear shader buffer 3. update command buffer for gfx9 Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36 Signed-off-by: Flora Cui Acked-by: Christian König --- tests/amdgpu/basic_tests.c | 36

RE: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

Series is: Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Cui, Flora Sent: 2019年7月18日 16:11 To: amd-gfx@lists.freedesktop.org Cc: Cui, Flora Subject: [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test 1. perform gpu reset 2. perform

RE: [PATCH 4/4] drm/amdgpu: drop ras self test

Series is Reviewed-by: Feifei Xu -Original Message- From: amd-gfx On Behalf Of Hawking Zhang Sent: Thursday, July 18, 2019 4:20 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking Subject: [PATCH 4/4] drm/amdgpu: drop ras self test this function is not needed any more. error

Re: [PATCH 1/5] drm/amdgpu: allow direct submission in the VM backends

Am 17.07.19 um 22:31 schrieb Kuehling, Felix: On 2019-07-17 5:10, Christian König wrote: Am 16.07.19 um 18:40 schrieb Kuehling, Felix: On 2019-07-16 9:36 a.m., Christian König wrote: Am 02.07.19 um 21:35 schrieb Kuehling, Felix: This assumes that page tables are resident when a page fault is

Re: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

Hi Evan, 1. the other clock type also will check dpm fine grained support. 2. i will change code to v2 to avoid below case 0: 300M * 1: 300M 2: 1800M Best Regards, Kevin From: Quan, Evan Sent: Thursday, July 18, 2019 4:16:22 PM To: Wang,

RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

Reviewed-by: Kenneth Feng -Original Message- From: Wang, Kevin(Yang) Sent: Thursday, July 18, 2019 4:02 PM To: amd-gfx@lists.freedesktop.org Cc: Feng, Kenneth ; Quan, Evan ; Huang, Ray ; Xu, Feifei ; Wang, Kevin(Yang) Subject: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx

[PATCH 2/4] drm/amdgpu: disable GFX RAS by default

GFX RAS has not been stablized yet. disable GFX ras until it is fully funcitonal. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

[PATCH 1/4] drm/amdgpu: do not create ras debugfs/sysfs node for ASICs that don't have ras ability

driver shouldn't init any ras debugfs/sysfs node for ASICs that don't have ras hardware ability Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

[PATCH 3/4] drm/amdgpu: only allow error injection to UMC IP block

error injection to other IP blocks (except UMC) will be enabled until RAS feature stablize on those IP blocks Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

[PATCH 4/4] drm/amdgpu: drop ras self test

this function is not needed any more. error injection is the only way to validate ras but it can't be executed in amdgpu_ras_init, where gpu is even not initialized Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 --- 1 file changed, 7 deletions(-) diff --git

RE: [PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

1. Please commonilzie a new API e.g. smu_is_fine_grained_dpm which can be shared for other clocks in future. 2. if the current clock is same as min or max, the output will be a little strange 0: 300M * 1: 300M 2: 1800M Please check how raven handle this situation. Regards, Evan >

Re: [PATCH v2] drm/amdgpu: Default disable GDS for compute VMIDs

Am 17.07.19 um 22:09 schrieb Kuehling, Felix: On 2019-07-17 14:23, Greathouse, Joseph wrote: The GDS and GWS blocks default to allowing all VMIDs to access all entries. Graphics VMIDs can handle setting these limits when the driver launches work. However, compute workloads under HWS control

[PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test

1. skip test if there's no desired ring 2. clear shader buffer 3. update command buffer for gfx9 Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36 Signed-off-by: Flora Cui --- tests/amdgpu/basic_tests.c | 36 1 file changed, 28 insertions(+), 8

[PATCH libdrm 2/2] tests/amdgpu: add gpu reset test

1. perform gpu reset 2. perform dispatch test to verify gpu reset to a good state Change-Id: I4bba0d1b829288bba7b6885d7e68c8f69ef8f4b5 Signed-off-by: Flora Cui --- tests/amdgpu/amdgpu_test.c | 5 + tests/amdgpu/basic_tests.c | 38 ++ 2 files changed, 43

[PATCH] drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10

the navi10 gfxclk (sclk) support fine grained DPM, so use level 1 to show current dpm freq in sysfs pp_dpm_xxx Change-Id: Idae2424f8cc91fe94cebe7f3103e112b4f912fbc Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 41 +- 1 file changed, 33