Okay, I can limit it only for vega10 adapter
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, September 24, 2019 1:44 PM
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk
Subject: RE: [PATCH]
I'd suggest you create umc function to apply these workaround to VG10 only if
we are not sure this is a common hw bugs. You can refer to amdgpu_umc_funcs for
creating umc callback functions.
In addition, normally umc per channel registers will have constant offset, like
0x200 for vg10. You can
The patch is in high risk to break other VG series and MI series. Any
confidence this is a common hw bug across all UMC 6.x generations?
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Monk Liu
Sent: 2019年9月24日 11:39
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk
In HDMI 1.4 defines 4k modes without specific aspect ratio.
However, in HDMI 2.0, adds aspect ratio attribute to distinguish different
4k modes.
According to Appendix E of HDMI 2.0 spec, source should use VSIF to
indicate VIC mode only when the mode is one defined in HDMI 1.4b 4K modes.
To pair the latest SMU firmware.
Change-Id: I376b8c9d0c5a56a343d477a945d63ba894b984d3
Signed-off-by: Evan Quan
---
.../amd/powerplay/inc/smu11_driver_if_arcturus.h | 15 ---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
2 files changed, 9 insertions(+), 8 deletions(-)
issue:
the UMC h/w bug is that when MCLK is doing the switch
in the middle of a page access being preempted by high
priority client (e.g. DISPLAY) then UMC and the mclk switch
would stuck there due to deadlock
how:
fixed by disabling auto PreChg for UMC to avoid high
priority client preempting
From: Wang, Kevin(Yang)
Sent: Monday, September 23, 2019 5:25 PM
To: Liang, Prike ; amd-gfx@lists.freedesktop.org
Cc: arron@amd.com; Huang, Ray ; Quan, Evan
; Feng, Kenneth
Subject: Re: [PATCH 2/5] drm/amd/powerplay: add interface for forcing and
unforcing dpm limit value
comment
That's a good point for simplifying the code and will send another patch for
this.
Thanks,
Prike
From: Wang, Kevin(Yang)
Sent: Monday, September 23, 2019 5:22 PM
To: Liang, Prike ; amd-gfx@lists.freedesktop.org
Cc: arron@amd.com; Huang, Ray ; Quan, Evan
; Feng, Kenneth
Subject: Re:
A small nitpick: if this workaround is needed for all NAVi ASICs, can we make a
macro for this?
e.g. #define ASIC_IS_NAVI_SERIES(adev) (adev->asic_type >=
CHIP_NAVI10 && adev->asic_type <= NAVI12)
Then we can use
if (!adev->mman.buffer_funcs_enabled ||
when gfxoff is enabled, sdma hangs while entering desktop without this
workaround
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
Oops, you are right Evan. I'll send another patch.
It's a little counter-intuitive that asic type id of navi12 is larger than
navi14.
BR,
Xiaojie
From: Quan, Evan
Sent: Tuesday, September 24, 2019 10:09 AM
To: Yuan, Xiaojie;
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: Gong, Curry
> Sent: Tuesday, September 24, 2019 10:27 AM
> To: Liu, Aaron ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU
> RESET
>
> Hi Aaron:
>
> Help to review
Patch 1- 3 are reviewed-by: Evan Quan
-Original Message-
From: Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; arron@amd.com; Liang, Prike
Subject: [PATCH 3/5] drm/amd/powerplay: add interface
-Original Message-
From: Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; arron@amd.com; Liang, Prike
Subject: [PATCH 5/5] drm/amd/powerplay: implement interface
set_power_profile_mode()
Add
-Original Message-
From: Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; arron@amd.com; Liang, Prike
Subject: [PATCH 4/5] drm/amd/powerplay: add the interfaces for getting and
setting
Hi Aaron:
Help to review again.
-Original Message-
From: Liu, Aaron
Sent: Monday, September 23, 2019 2:41 PM
To: Gong, Curry ; amd-gfx@lists.freedesktop.org
Cc: Gong, Curry
Subject: RE: [PATCH 1/2] drm/amd/powerplay: Add mode2 mode for GPU RESET
Hi curry,
1. You can separate the
The patch makes me a little confusing.
According to asic type list,
CHIP_NAVI10,/* 25 */
CHIP_NAVI14,/* 26 */
CHIP_NAVI12,/* 27 */
CHIP_LAST,
before the sdma workaround applies only for Navi10 and Navi14(not Navi12).
However, it seems this patch reverse
Reviewed-by: Evan Quan
-Original Message-
From: Yuan, Xiaojie
Sent: Monday, September 23, 2019 9:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Xiao, Jack ;
Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH 2/2] drm/amdgpu/gfx10: enable
Series is: Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Zhou1, Tao
Sent: Monday, September 23, 2019 7:46 PM
To: amd-gfx@lists.freedesktop.org; Chen, Guchun ; Zhang,
Hawking ; Grodzovsky, Andrey
Cc: Zhou1, Tao
Subject: [PATCH 22/22] drm/amdgpu: add comments in
On Mon, Sep 23, 2019 at 5:14 PM Harry Wentland wrote:
>
> On 2019-09-23 4:58 p.m., Alex Deucher wrote:
> > It's apparently needed in some configurations.
>
> Curious which config fails and what compiler errors we get... Sounds
> like our includes are messed up somewhere.
Not sure exactly:
On 2019-09-23 4:58 p.m., Alex Deucher wrote:
> It's apparently needed in some configurations.
Curious which config fails and what compiler errors we get... Sounds
like our includes are messed up somewhere.
Harry
>
> Signed-off-by: Alex Deucher
> ---
>
It's apparently needed in some configurations.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
fetch both the vram type and width in one function call. This
avoids having to parse the same data table twice to get the two
pieces of data.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 34 +
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 4 +-
The index is stored in scratch register 4 after asic init. Use
that index. No functional change since all asics in a family
use the same type of vram (G5, G6, HBM) and that is all we use
at the monent, but if we ever need to query other info, we will
now have the proper index.
v2: module array
Hello,
on my new Acer Nitro 5 (AN515-43-R8BF) backlight and actual_backlight value
in sysfs mismatch. When backlight is 0 actual_backlight is still 5140.
root@nitro5:/sys/class/backlight/amdgpu_bl1# cat brightness
255
root@nitro5:/sys/class/backlight/amdgpu_bl1# cat actual_brightness
65535
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Zhao, Yong
Sent: Monday, September 23, 2019 4:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong
Subject: [PATCH 2/2] drm/amdkfd: Sync gfx10 kfd2kgd_calls function pointers
get_hive_id was
Currently this function pointer is missing for GFX10. Considering it is
a void function since GFX9, fix it by checking the function pointer
before dereferencing it.
Change-Id: I1dc8e5163f259251357bfaa42a91ff991fba6dd5
Signed-off-by: Yong Zhao
---
get_hive_id was not set. Also, adjust the function setting sequence.
Change-Id: I51962954cd0707ebe9aa6c85c71110dee98d6200
Signed-off-by: Yong Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
The index is stored in scratch register 4 after asic init. Use
that index. No functional change since all asics in a family
use the same type of vram (G5, G6, HBM) and that is all we use
at the monent, but if we ever need to query other info, we will
now have the proper index.
v2: module array
Okay, I will incorporate Shaoyun's input.
Yong
From: Liu, Shaoyun
Sent: Monday, September 23, 2019 10:27 AM
To: Zhao, Yong ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
Probably rename to
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^/\t/' -i */Kconfig
Signed-off-by: Krzysztof Kozlowski
---
drivers/gpu/drm/Kconfig | 10 +-
drivers/gpu/drm/amd/display/Kconfig | 20 ++--
On 9/23/19 2:14 AM, chen gong wrote:
> Signed-off-by: chen gong
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 58818761..0f639df9 100644
> ---
Probably rename to sdma_rlc to avoid the confusion of rlc used in
other amdgpu driver .
Regards
shaoyun.liu
On 2019-09-22 11:56 p.m., Zhao, Yong wrote:
> The old name is prone to confusion. The register offset is for a RLC queue
> rather than a SDMA engine. The value is not a base address,
Hellow collegues!
I am one of the developers of the Alt OS distribution
https://en.altlinux.org
https://en.wikipedia.org/wiki/ALT_Linux
for the computer BFK3.1
https://www.baikalelectronics.ru/products/bfk31/
Sorry that I missed to add Reviewed-by when push this patch.
Regards,
Ma Le
-Original Message-
From: Zhang, Hawking
Sent: Monday, September 23, 2019 9:58 PM
To: Ma, Le ; amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: RE: [PATCH 2/2] drm/amdgpu: correct condition check for psp rlc
when gfxoff is enabled, applying this workaround makes sdma hang while
entering desktop.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 082a0b3298a9..22406f56c818 100644
---
Please help to add simple description for both patches. with that fixed,
Series is Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Le Ma
Sent: 2019年9月23日 21:31
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: [PATCH 2/2] drm/amdgpu:
Change-Id: Ia91d0fb7179f6944214e892f370d7ef3d6b7d30e
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d359f1d..2aa1ae6
From: Hawking Zhang
Change-Id: I88649fc5dbc7376f3c90ec2114236294ca9189de
Signed-off-by: Hawking Zhang
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
Yeah, we already documented the dma_fence_array() behavior on that function.
But having another comment here would probably be a good idea.
Christian.
Am 23.09.19 um 14:35 schrieb Deucher, Alexander:
Maybe add a comment here in the code to avoid confusion in the future.
Alex
cpp[BytePerPlane] can't describe the 10bit data format correctly,
So we use bpp[BitPerPlane] to instead cpp.
Signed-off-by: Sandy Huang
---
drivers/gpu/drm/radeon/atombios_crtc.c | 10 +-
drivers/gpu/drm/radeon/r100.c | 4 ++--
drivers/gpu/drm/radeon/radeon_display.c
cpp[BytePerPlane] can't describe the 10bit data format correctly,
So we use bpp[BitPerPlane] to instead cpp.
Signed-off-by: Sandy Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Zhao, Yong
Sent: Monday, September 23, 2019 12:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong
Subject: [PATCH 3/3] drm/amdkfd: Remove unnecessary pm_init() for non HWS mode
The packet
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Zhao, Yong
Sent: Sunday, September 22, 2019 11:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong
Subject: [PATCH 2/2] drm/amdkfd: Use better name for sdma queue non HWS path
The old name is
Maybe add a comment here in the code to avoid confusion in the future.
Alex
From: Koenig, Christian
Sent: Saturday, September 21, 2019 7:32 AM
To: Navid Emamdoost
Cc: emamd...@umn.edu ; smcca...@umn.edu ;
k...@umn.edu ; Deucher, Alexander ;
Zhou,
add comments to clarify why checking GFX IP BLOCK for each ras interrupt
callback
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4
3 files changed, 14
simplify code logic and refine return value
v2: remove unused error source code
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +++-
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
I'll add a new patch.
Regards,
Tao
> -Original Message-
> From: Zhang, Hawking
> Sent: 2019年9月19日 22:48
> To: Chen, Guchun ; Zhou1, Tao
> ; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 05/21] drm/amdgpu: refine sdma4 ras_data_cb
>
> Let's add comments to clarifying why checking
> -Original Message-
> From: Chen, Guchun
> Sent: 2019年9月19日 21:59
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> Zhang, Hawking
> Subject: RE: [PATCH 05/21] drm/amdgpu: refine sdma4 ras_data_cb
>
>
>
>
> Regards,
> Guchun
>
> -Original Message-
> From: Zhou1, Tao
>
> -Original Message-
> From: Chen, Guchun
> Sent: 2019年9月19日 22:11
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> Zhang, Hawking
> Subject: RE: [PATCH 11/21] drm/amdgpu: add common gfx_ras_fini function
>
>
> -Original Message-
> From: Zhou1, Tao
> Sent: Thursday,
comment inline.
From: amd-gfx on behalf of Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: arron@amd.com ; Huang, Ray ;
Liang, Prike ; Quan, Evan ; Feng,
Kenneth
Subject: [PATCH 5/5] drm/amd/powerplay:
comment inline.
From: amd-gfx on behalf of Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: arron@amd.com ; Huang, Ray ;
Liang, Prike ; Quan, Evan ; Feng,
Kenneth
Subject: [PATCH 4/5] drm/amd/powerplay: add the
Reviewed-by: Kevin Wang
From: amd-gfx on behalf of Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: arron@amd.com ; Huang, Ray ;
Liang, Prike ; Quan, Evan ; Feng,
Kenneth
Subject: [PATCH 3/5] drm/amd/powerplay:
comment inline.
From: amd-gfx on behalf of Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: arron@amd.com ; Huang, Ray ;
Liang, Prike ; Quan, Evan ; Feng,
Kenneth
Subject: [PATCH 2/5] drm/amd/powerplay: add
the smu driver many place will use AMD_IS_APU flags,
i think we'd better add a new member "is_apu" in smu_context"
Best Regards,
kevin
From: amd-gfx on behalf of Liang, Prike
Sent: Monday, September 23, 2019 4:43 PM
To: amd-gfx@lists.freedesktop.org
Cc:
Patch #2 should be already in drm-next. Please drop it from the series when you
push them. The series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Le Ma
Sent: 2019年9月23日 14:29
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: [PATCH
For now APU has no smu_dpm_context structure for containing default/current
related dpm table,
thus will not initialize smu_dpm_context and aviod null pointer check guard for
APU.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 10 +++---
1 file changed, 7
Add set_power_profile_mode() for none manual dpm level case setting power
profile mode.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
implement get_profiling_clk_mask and force_clk_levels for forcing dpm clk to
limit value.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 83 ++
1 file changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
The workload type was got from the input of power profile mode.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
That's base function for forcing and unforcing dpm limit value.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
Reviewed-by: Kenneth Feng
-Original Message-
From: Wang, Kevin(Yang)
Sent: Monday, September 23, 2019 3:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Feng, Kenneth ;
Liang, Prike ; Wang, Kevin(Yang)
Subject: [PATCH] drm/amd/powerplay: remove duplicate macro of
Hi Michel,
Can you help illustrate more about using MRs to proceed libdrm changes? We can
use gitlab to merge the change from our local forked repository to drm master
repository?
Maybe one document is preferable for this.
Thanks.
Regards,
Guchun
-Original Message-
From: amd-gfx On
Thanks clean up the duplicate code. The patch is
Reviewed-by: Prike Liang
Thanks,
Prike
> -Original Message-
> From: Wang, Kevin(Yang)
> Sent: Monday, September 23, 2019 3:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Feng, Kenneth
> ; Liang, Prike ; Wang,
> Kevin(Yang)
remove duplicate macro of smu_get_uclk_dpm_states
fix commit:
drm/amd/powerplay: add the interface for getting ultimate frequency v3
Signed-off-by: Kevin Wang
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 --
1 file changed, 2 deletions(-)
diff --git
Hi curry,
1. You can separate the patch into 2 patches, one is workaround in smu_suspend
and another is the implementation of mode2_reset.
2. hwmgr.h is used for amdgpu_powerplay instead of amdgpu_smu. You can define
it directly in amdgpu_smu.h
BR,
Aaron Liu
> -Original Message-
>
Reviewed-by: Aaron Liu
BR,
Aaron Liu
> -Original Message-
> From: amd-gfx On Behalf Of chen
> gong
> Sent: Monday, September 23, 2019 2:14 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Gong, Curry
> Subject: [PATCH 2/2] drm/amdgpu: Use mode2 mode to perform GPU RESET
> for Renoir
>
>
Change-Id: I6b69bfba66aa12d5486527e29a7c322336c95dd5
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 5bec851..dbd790e 100644
---
Change-Id: Ibf137cd57659e70516bcbbe456a00ad77e60647c
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 7c7e9f5..5bec851 100644
---
Change-Id: I13a5f590d5a49655965a13eb7ce773d1efffcbd0
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index
Signed-off-by: chen gong
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 58818761..0f639df9 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++
Changes to function "smu_suspend" in amdgpu_smu.c is a workaround.
We should get real information about if baco is enabled or not, while we
always consider APU SMU feature as enabled in current code.
I know APU do not support baco mode for GPU reset, so I use
"adev->flags" to skip function
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