[AMD Public Use]
Hi, Guchun,
adev->grbm_idx_mutex is only used to protect the access to registers
whose instance switch is indexed by grbm_index.
Best Regards
Dennis Li
-Original Message-
From: Chen, Guchun
Sent: Sunday, January 19, 2020 11:40 AM
To: Li, Dennis ;
[AMD Public Use]
+ switch (adev->asic_type)
+ {
Please correct the coding style. '{' should stay at the same line of switch.
+ mutex_unlock(>grbm_idx_mutex);
+
+ gfx_v9_4_query_utc_edc_status(adev, err_data);
Is it necessary to move gfx_v9_4_query_utc_edc_status calling
[AMD Public Use]
Series is: Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Dennis Li
Sent: Sunday, January 19, 2020 11:03 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhou1, Tao ; Zhang, Hawking
; Chen, Guchun
Cc: Li, Dennis
Subject: [PATCH 2/2]
1. Add RAS support for MAM D(0~3)_MEM in mmhub.
2. Add RAS support for other mmhub ranges from 2 to 7.
Dennis Li (2):
drm/amdgpu: update mmhub 9.4.1 header files for Acrturus
drm/amdgpu: enable RAS feature for more mmhub sub-blocks of Acrturus
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c |
Add mask & shift definition of MAM_D(0~3)MEM for all mmhub
ranges.
Change-Id: I65c8a3040611198273a4b6da77c1a1ad2ffe7fd3
Signed-off-by: Dennis Li
---
.../asic_reg/mmhub/mmhub_9_4_1_sh_mask.h | 128 ++
1 file changed, 128 insertions(+)
diff --git
Compared with Vg20, the size of mmhub range is changed from 2 to 8.
Change-Id: I529c0ff0aaed200e5b102d482563ed9dc2278260
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 701 +++-
1 file changed, 695 insertions(+), 6 deletions(-)
diff --git
Implement functions to do the RAS error injection and
query EDC counter.
Change-Id: I4d947511331a19c1967551b9d42997698073f795
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 26 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c | 978
Refactor the ras related codes of vega20:
1. refine the security check for RAS functions.
2. abstract clearing edc counters to a separated function.
3. add ip prefix to ip related codes.
Implementation of RAS feature for Arcturus gfx:
1. add new register head files for gfx v9.4.1.
2. add codes to
To avoid calling RAS related functions when RAS feature isn't
supported in hardware. Change to check supported features, instead
of checking asic type.
v2: reuse amdgpu_ras_is_supported function, instead of introducing
a new flag for hardware ras feature.
Change-Id:
add reg headers to gc includes
v2: remove unused registers and fields in this patch set
Change-Id: If3476c0b0ed88e5d11bdb8bec1278ae10fc5af25
Signed-off-by: Dennis Li
---
.../amd/include/asic_reg/gc/gc_9_4_1_offset.h | 264 +++
.../include/asic_reg/gc/gc_9_4_1_sh_mask.h| 748
1. Add IP prefix for the IP related codes.
2. Refactor the code to clear EDC counter.
Change-Id: I1cd9ec304a7ace9a74480264d24368fd11a87833
Signed-off-by: Dennis Li
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 112 ++
1 file changed, 77 insertions(+), 35 deletions(-)
diff
Am 18.01.20 um 02:37 schrieb Felix Kuehling:
Use a more meaningful variable name for the invalidation request
that is distinct from the tmp variable that gets overwritten when
acquiring the invalidation semaphore.
Fixes: 00f607f38d82 ("drm/amdgpu: invalidate mmhub semaphore workaround in
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