I don't totally understand the stack trace but I do see a double free
bug.
drivers/gpu/drm/vgem/vgem_drv.c
186 static struct drm_gem_object *vgem_gem_create(struct drm_device *dev,
187struct drm_file *file,
188
[AMD Official Use Only - Internal Distribution Only]
Patch 1,2,3 work for me. See one comment inline, otherwise Reviewed-by: Oak
Zeng
Regards,
Oak
-Original Message-
From: amd-gfx On Behalf Of Rajneesh
Bhardwaj
Sent: Friday, January 31, 2020 10:37 PM
To:
So far the kfd driver implemented same routines for runtime and system
wide suspend and resume (s2idle or mem). During system wide suspend the
kfd aquires an atomic lock that prevents any more user processes to
create queues and interact with kfd driver and amd gpu. This mechanism
created problem
Changes in v2:
* Rebased on latest amd-staging-drm-next
* Addressed review comments from Felix, Oak and Alex for v1
* Removed 60 second hack for auto-suspend delay and simplified the
logic
* Dropped kfd debugfs patch
* Folded in Alex's patch from this series to enable and test with kfd.
From: Alex Deucher
Seems to work reliably on VI+.
[rajneesh] Picked https://patchwork.freedesktop.org/patch/335402/ to
enable runtime pm with baco for kfd. Also fixed a checkpatch warning and
dropped below patch from previous series in favor of Alex's patch.
amdgpu_device_suspend might return an error code since it can be called
from both runtime and system suspend flows. Add the missing return code
in case of a failure.
Reviewed-by: Alex Deucher
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++
1 file changed,
During system suspend the kfd driver aquires a lock that prohibits
further kfd actions unless the gpu is resumed. This adds some info which
can be useful while debugging.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 ++
1 file changed, 2 insertions(+)
diff
From: Joseph Gravenor
[why]
not turning off the mst hub before detection on reboot
causes us to not be able to light up displays with mst hook
[how]
on hw init, see if any displays are lit up. if so, turn them off
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet
From: Yongqiang Sun
[Why]
hyperV flag should be passed from dm to DC, and override the
nv12 flip workaround flag.
[How]
Add flag to phy address config struct and pass the value in dm.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Aric Cyr
[Why]
Engine can be NULL in some cases, so we must not acquire it.
[How]
Check for NULL engine before acquiring.
Signed-off-by: Aric Cyr
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1
From: Roman Li
[Why]
The break in apply_ctx_interdependent_lock() may potentially
lead to early break from the loop leaving update plane unlocked
[How]
Remove break
Signed-off-by: Roman Li
Reviewed-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
1 file changed, 1
From: Hersen Wu
[Why] old panel has been enabled for window driver but not linux.
[How] enable oled panel support for linux. this patch is dc part.
Signed-off-by: Hersen Wu
Reviewed-by: Harry Wentland
Reviewed-by: Hersen Wu
Acked-by: Bhawanpreet Lakha
---
From: Joseph Gravenor
[why/how]
We found out that the register we read actually gets reset by SMU
after we loose power, meaning this always returns true
Signed-off-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 --
From: Yongqiang Sun
[Why]
Underflow is observed when plug in a 4K@60 monitor with
1366x768 eDP due to DPPCLK is too low.
[How]
Limit minimum DPPCLK to 100MHz.
Signed-off-by: Yongqiang Sun
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
From: Isabel Zhang
[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.
[How]
Initializations added for PLL2 when
From: Eric Bernstein
[Why]
Diagnostics team reported various issues found when enabling warnings as errors
[How]
Fix implicit conversions
Signed-off-by: Eric Bernstein
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
From: Nicholas Kazlauskas
[Why]
The DMUB tracebuffer is useful for understanding DMCUB execution state.
[How]
Add a "show" attribute debugfs so we can loop through the buffer
and print the entries.
The structs for the entry format are defined in the debugfs since
the tracebuffer header no
From: Tony Cheng
[Why]
these registers should have been double buffered. SW workaround we will have SW
program the more aggressive (lower) values
whenever we are upating this register, so we will not have underflow at expense
of less optimzal request pattern.
[How]
there is a driver bug where
From: Anthony Koo
[Why]
Screen flickering when HDR switches between FP16 and ARGB2101010
[How]
Moved pipe_control_lock so stream update and plane update occur atomically
Signed-off-by: Anthony Koo
Signed-off-by: Lucy Li
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
From: Anthony Koo
[Why]
DSC updates only set type to FULL UPDATE, but doesn't
flag the change
[How]
Add DSC flag update flag
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ---
From: Sung Lee
[WHY & HOW]
Previously drain clk was unconstrained and fill clk was constrained on fclk.
We want to change it to fill clk unconstrained and drain clock constrained
to dcfclk.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Charlene Liu
[why]
new HW engine mapping requirment use in PSP
[how]
report stream_enc_inst
Signed-off-by: Charlene Liu
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
From: Nicholas Kazlauskas
[Why]
The General Purpose Interrupt is used on the DMCUB to pass lightweight
commands via a register to the DMCUB.
This is limited to 32-bit command and 32-bit response.
This will be used for shutting down the firmware in a clean manner.
[How]
Add the command IDs and
From: Sung Lee
[WHY & HOW]
Having watermark ranges saved inside clk_mgr to be
available for debug at all times would be useful.
Add it to the clk_mgr_internal struct for reference.
Only populated for Renoir, unused for other asics.
Signed-off-by: Sung Lee
Reviewed-by: Yongqiang Sun
Acked-by:
Summary Of Changes
*DMCUB changes
*psr frame calculation fix
*fix compile warnings
*refactor front end programing
*enable OLED support in DC
Anthony Koo (3):
drm/amd/display: Split program front end part that occur outside lock
drm/amd/display: Indicate dsc updates explicitly
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: David Galiffi
[WHY]
enum dc_log_type has more than 32 entries. User cannot set larger entries,
like LOG_DSC. Logs from LOG_GAMMA_DEBUG where being printed even though
flag was not enabled, because dal_logger_should_log check erroneously
passed.
[HOW]
Change struct dal_logger.mask and
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
From: Anthony Koo
[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.
[How]
Split out programming that is done post unlock.
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet
From: Eric Yang
[Why]
Previous logic is only good for 15W parts. Other configuration
need a smarter logic to match clk levels with pp table in the fuse.
[How]
Cache all 8 DPM level's clock data, find lvl that match each pstate
in the pp table and build input into DML base on that
From: Peikang Zhang
Description for DCHUBBUB_TEST_DEBUG_DATA is changed to avoid any future
confusions.
Signed-off-by: Peikang Zhang
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 63 +--
1 file changed, 3
From: Sung Lee
[WHY]
The optimized_require flag is needed to set watermarks and clocks lower
in certain conditions. This flag is set to true and then set to false
while programming front end in dcn20.
[HOW]
Do not set the flag to false while disabling plane.
Signed-off-by: Sung Lee
From: Roman Li
[Why]
Driver crash with psr feature enabled due to divide-by-zero error.
This is a regression after rework to calculate static screen frame
number entry time.
[How]
Correct order of operations to avoid divide-by-zero.
Signed-off-by: Roman Li
Reviewed-by: Zhan Liu
Acked-by:
From: Jing Zhou
[why]
Resume from modern standby, edp stream disabled
but abm keep enabled. External monitor select OTG
source 0 which ABM enabled.
[how]
Disable abm before disable crtc when reset path
mode not call core link disable stream.
Signed-off-by: Jing Zhou
Reviewed-by: Anthony Koo
From: Nicholas Kazlauskas
[Why]
The DMCUB may be currently executing commands when the reset is
triggered.
Before issuing a reset we should first wait for the DMCUB to finish
its work.
[How]
Send the GPINT command for halting the firmware before reset.
Get the ack for the command then wait
From: Wenjing Liu
[why]
hwss should not guess what type of pipe lock is needed.
The caller of the lock function should know
the right type of pipe lock.
Decouple the setup of global lock outside of pipe control lock
logic.
Signed-off-by: Wenjing Liu
Reviewed-by: Anthony Koo
Acked-by:
From: George Shen
[Why]
The call to dp_enable_link_phy are using default/invalid values for clock id
and link settings.
[How]
Move workaround code to after its parameter variables are determined.
Signed-off-by: George Shen
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
From: Aric Cyr
[Why]
After locking refactor GSL is not acquired properly
resulting in immediate flip issues.
[How]
Do not copy old GSL state anymore since GSL is acquired
earlier now.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index e8d126890d7e..d00b72df469a
From: Peikang Zhang
[Why]
int i can go out of boundary which will cause crash
[How]
Fixed the maximum value of i to avoid i going out of boundary
Signed-off-by: Peikang Zhang
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c | 2 +-
1
From: Wyatt Wood
[Why]
Must know psr version during runtime.
[How]
Add set psr version message structures.
Signed-off-by: Wyatt Wood
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
Thanks. I can confirm kernel 5.5rc7 improves things significantly. I'll post
this to the various channels I've asked in.
Josh
‐‐‐ Original Message ‐‐‐
On Friday, January 31, 2020 2:05 PM, Deucher, Alexander
wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> Please make
On 2020-01-31 3:24 p.m., Jerry (Fangzhi) Zuo wrote:
> Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
> real CRC value of the last edid data block, and write it back.
> Current edid CRC calculates routine adds the last CRC byte,
> and check if non-zero.
>
> This behavior is not
Unlike DP 1.2 edid corruption test, DP 1.4 requires to calculate
real CRC value of the last edid data block, and write it back.
Current edid CRC calculates routine adds the last CRC byte,
and check if non-zero.
This behavior is not accurate; actually, we need to return
the actual CRC value when
On 2020-01-31 1:47 p.m., Lin, Amber wrote:
[AMD Official Use Only - Internal Distribution Only]
It doesn't apply to this one because
1. It only has one set of attribute (dma32 or highmem) using the kobj_type, so it can set
the default_attrs. In my case, I have multiple queues/QIDs that share
[AMD Official Use Only - Internal Distribution Only]
Please make sure your kernel has this patch:
commit 46203a508f64b4bfa150a9d25eab1dc891e7e650
Author: Alex Deucher
Date: Tue Oct 29 17:14:15 2019 -0400
drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE
These were not
[AMD Official Use Only - Internal Distribution Only]
It doesn't apply to this one because
1. It only has one set of attribute (dma32 or highmem) using the kobj_type, so
it can set the default_attrs. In my case, I have multiple queues/QIDs that
share the same kobj_type while each of them has
Hi all,
I am trying to use a Radeon RX 5700XT via OpenCL with kernel 5.3.0 (I have also
tried kernel 5.3.18) on Ubuntu 18.04. I have noticed that this combination is
much slower than expected. I'm trying to find out why, and how to fix it.
If I'm in the wrong place to ask, would you be able to
You could save yourself the trouble of manually adding and removed
individual sysfs files by setting the default_attrs in the kobj_type.
See ttm_memory.c for an example how this is done.
More comments inline.
On 2020-01-31 8:45 a.m., Amber Lin wrote:
Provide compute queues information in
> -Original Message-
> From: amd-gfx On Behalf Of
> mikita.lip...@amd.com
> Sent: 2020/January/31, Friday 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Lipski, Mikita
> ; Wentland, Harry
> Subject: [PATCH] drm/amd/display: Fix a typo when computing dsc
>
From: Mikita Lipski
[why]
Remove a backslash symbol accidentally left in increase bpp function
when computing mst dsc configuration.
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Provide compute queues information in sysfs under /sys/class/kfd/kfd/proc.
The format is /sys/class/kfd/kfd/proc//queues//XX where
XX are size, type, and gpuid three files to represent queue size, queue
type, and the GPU this queue uses. folder and files underneath
are generated when a queue is
Am 30.01.20 um 23:11 schrieb Felix Kuehling:
On 2020-01-30 7:49, Christian König wrote:
For the root PD mask can be 0x as well which would
overrun to 0 if we don't cast it before we add one.
You're fixing parentheses, not braces.
Parentheses: ()
Brackets: []
Braces: {}
Yeah, I
If "speed" is zero then we use it as a divisor to find "prescale". It's
better to move the check for zero to the very start of the function.
Fixes: 9eeec26a1339 ("drm/amd/display: Refine i2c frequency calculating
sequence")
Signed-off-by: Dan Carpenter
---
*Hello Zhan,*
Here is it:
https://gist.githubusercontent.com/Kreyren/e35587d8710e63e511e69d8653fd996b/raw/628df1c76ff99adab1d2161e6a20f631de101d5c/gistfile1.txt
Note that I'm updating previous gists with new findings (
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7).
If
I'm sorry for the wrong link, this one should work
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7
I've manually compiled kernel-5.5 which results in this dmesg -
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