[AMD Official Use Only - Internal Distribution Only]
Hi, Felix,
amdgpu_gem_prime_export has different define in the old driver. I added
some comment in the below codes.
Best Regards
Dennis Li
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Tuesday, July 14,
- fix some styling issues
- fixes for kernel-doc type
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 61 +++
1 file changed, 25 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
[AMD Official Use Only - Internal Distribution Only]
Hi, Jack,
Please see the following comments.
Best Regards
Dennis Li
-Original Message-
From: amd-gfx On Behalf Of Jack Zhang
Sent: Tuesday, July 14, 2020 10:47 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian) ; Liu,
On Tue, 14 Jul 2020 at 14:09, Felix Kuehling wrote:
>
> Am 2020-07-13 um 11:28 p.m. schrieb Dave Airlie:
> > On Tue, 14 Jul 2020 at 13:14, Felix Kuehling wrote:
> >> This allows exporting and importing buffers. The API generates handles
> >> that can be used with the HIP IPC API, i.e. big
COUNT in linear write packet represents dword number - 1
Before fix:
navi10.sdma0.ring[ 0] == 0x0002.w. OPCODE: [WRITE], SUB-OPCODE: [0],
LINEAR_WRITE
navi10.sdma0.ring[ 1] == 0x00400a60... |---+ WORD [1]: DST_ADDR_LO:
0x00400a60
navi10.sdma0.ring[ 2] == 0x...
Am 2020-07-13 um 11:28 p.m. schrieb Dave Airlie:
> On Tue, 14 Jul 2020 at 13:14, Felix Kuehling wrote:
>> This allows exporting and importing buffers. The API generates handles
>> that can be used with the HIP IPC API, i.e. big numbers rather than
>> file descriptors.
> First up why? I get the
On Tue, 14 Jul 2020 at 13:14, Felix Kuehling wrote:
>
> This allows exporting and importing buffers. The API generates handles
> that can be used with the HIP IPC API, i.e. big numbers rather than
> file descriptors.
First up why? I get the how.
> + * @share_handle is a 128 bit random number
This allows exporting and importing buffers. The API generates handles
that can be used with the HIP IPC API, i.e. big numbers rather than
file descriptors.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 5 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c |
This API is used by MPI/UCX for efficiently sharing VRAM between MPI
ranks on the same node. It has been part of the ROCm DKMS branch for a
long time. This code is refactored to be less invasive for upstreaming.
As a result struct kfd_bo and the associated interval tree is not needed
upstream.
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch
to set the World Switch for MM appropriately. This patch add
the interface for mmsch_v3.0.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/mmsch_v3_0.h | 130
1 file changed, 130 insertions(+)
1.Skip decode_ring test in VF, because VCN in SRIOV does not
support direct register read/write.
2.Skip powergating configuration in hw fini because
VCN3.0 SRIOV doesn't support powergating.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4
For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
1.In early_init and for sriov, hardcode
harvest_config=0, enc_num=1
2.sw_init/fini
alloc & free mm_table for sriov
doorbell setting for sriov
3.hw_init/fini
Under sriov, add start_sriov to config mmsch
Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings.
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.
Signed-off-by: Jack Zhang
---
drivers/gpu/drm/amd/amdgpu/nv.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index
[AMD Official Use Only - Internal Distribution Only]
That's true.
Reviewed-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of chen gong
Sent: Monday, July 13, 2020 4:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gong, Curry
Subject: [PATCH] drm/amdgpu/powerplay: Modify SMC
Default value is auto, doesn't change
original reset method logic.
v2: change to use parameter reset_method
v3: add warn msg if specified mode isn't supported
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.
v2: add mode1 reset dpm interface
v3: change maro name
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
If we are in RAS triggered situation and
BACO isn't support, emergency restart is needed,
and this code is only needed for some specific
cases(vega20 with given smu fw version).
After we add smu mode1 reset for sienna cichlid, we
need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset,
so in
For sienna cichlid, add mode1 reset path for sGPU.
v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch
Signed-off-by: Likun Gao
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/nv.c | 19 ---
I'm running into this problem with the KFD EvictionTest. The log snippet
below looks like it ran out of GTT space for the eviction of a 64MB
buffer. But then it dumps the used and free space and shows plenty of
free space.
As I understand it, the per-page breakdown of used and free space shown
by
On Tue, 14 Jul 2020 at 02:39, Christian König wrote:
>
> Am 13.07.20 um 18:26 schrieb Daniel Vetter:
> > Hi Christian,
> >
> > On Wed, Jul 08, 2020 at 04:57:21PM +0200, Christian König wrote:
> >> Could we merge this controlled by a separate config option?
> >>
> >> This way we could have the
On Mon, Jul 13, 2020 at 9:48 AM Shashank Sharma wrote:
>
> The current hw_init code for si_dpm ignores the return value of the
> function attempting to initialize the thermal controller, which in
> turn sets the dpm_enabled status wrongly to true in hw_init, which
> should be actually false.
>
>
Am 13.07.20 um 18:26 schrieb Daniel Vetter:
Hi Christian,
On Wed, Jul 08, 2020 at 04:57:21PM +0200, Christian König wrote:
Could we merge this controlled by a separate config option?
This way we could have the checks upstream without having to fix all the
stuff before we do this?
Discussions
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Bhawanpreet Lakha
From: Nicholas Kazlauskas
Sent: July 13, 2020 11:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kazlauskas, Nicholas ; Lakha, Bhawanpreet
Subject: [PATCH 2/2] drm/amd/display:
Hi Christian,
On Wed, Jul 08, 2020 at 04:57:21PM +0200, Christian König wrote:
> Could we merge this controlled by a separate config option?
>
> This way we could have the checks upstream without having to fix all the
> stuff before we do this?
Discussions died out a bit, do you consider this a
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Bhawanpreet Lakha
From: Nicholas Kazlauskas
Sent: July 13, 2020 11:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kazlauskas, Nicholas ; Lakha, Bhawanpreet
Subject: [PATCH 1/2] drm/amd/display:
[Why]
When enabling the debugfs for CRC capture we hit assertions caused by
register address and field masks and shifts missing.
[How]
We want these registers programmed, so add in the SRI/SF entries for
this register.
Cc: Bhawanpreet Lakha
Signed-off-by: Nicholas Kazlauskas
---
[Why]
CRC capture doesn't work when the active plane count is 0 since we
currently tie both vblank and pageflip interrupts to active_plane_count
greater than 0.
[How]
The frontend is what generates the vblank interrupts while the backend
is what generates pageflip interrupts. Both have a
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c| 20
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan wrote:
>
> Preparing for coming code sharing around performance level
> setting.
>
> Change-Id: Iaa77af7a272121503f09ad5fbfbe9dff2d2597b1
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan wrote:
>
> Maximum the code sharing around smu V11.
>
> Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++
>
On Mon, Jul 13, 2020 at 4:34 AM chen gong wrote:
>
> I consulted Cai Land(chuntian@amd.com), he told me corresponding smc
> message name to fSMC_MSG_SetWorkloadMask() is
> "PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir.
>
> Strange though it may seem, but it's a fact.
Weird.
Am 13.07.20 um 15:34 schrieb Yuan, Xiaojie:
[AMD Official Use Only - Internal Distribution Only]
Hi Chris,
This was observed when I was trying to add a new debugfs file.
In this case please add the new file using debugfs_create_file()
directly and don't touch this old code.
Some
The current hw_init code for si_dpm ignores the return value of the
function attempting to initialize the thermal controller, which in
turn sets the dpm_enabled status wrongly to true in hw_init, which
should be actually false.
This patch:
- Adds the return value check for thermal controller
[AMD Official Use Only - Internal Distribution Only]
Hi Chris,
This was observed when I was trying to add a new debugfs file. Some similar
occurrences using ARRAY_SIZE() are:
- amdgpu_kms.c :: amdgpu_firmware_info_list
- amdgpu_pm.c :: amdgpu_debugfs_pm_info
- amdgpu_ttm.c ::
On 7/3/20 4:41 PM, Samuel Iglesias Gonsálvez wrote:
> Hi,
>
> In the last meeting, X.Org Foundation board has decided that XDC 2020
> will be a virtual conference, given the uncertain COVID-19 situation in
> Europe by September, including the possibility of a second wave,
> outbreaks and travel
Dear Dennis,
Am 10.07.20 um 10:39 schrieb Li, Dennis:
I used our internal tool to make GPU hang and do stress test.
Interesting. I want to have such a tool. ;-)
So you noticed it during testing with that tool, and not by somebody
experiencing this in production?
In kernel, when GPU
Am 13.07.20 um 07:59 schrieb Xiaojie Yuan:
to easily add new debugfs file w/o changing the hardcoded list count.
In general a good idea, but I would rather like to see
amdgpu_debugfs_add_files() completely removed and debugfs_create_file()
used directly instead.
Christian.
I consulted Cai Land(chuntian@amd.com), he told me corresponding smc
message name to fSMC_MSG_SetWorkloadMask() is
"PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir.
Strange though it may seem, but it's a fact.
Signed-off-by: chen gong
---
[AMD Public Use]
Good suggestion, will refine the name.
Brs
Wenhui
-Original Message-
From: Zhang, Hawking
Sent: Monday, July 13, 2020 1:55 PM
To: Sheng, Wenhui ; amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: RE: [PATCH 1/3] drm/amd/powerplay: add SMU mode1 reset
[AMD
[AMD Public Use]
Ok got it.
Brs
Wenhui
-Original Message-
From: Zhang, Hawking
Sent: Monday, July 13, 2020 1:52 PM
To: Sheng, Wenhui ; amd-gfx@lists.freedesktop.org
Cc: Gao, Likun
Subject: RE: [PATCH 3/3] drm/amdgpu: add module parameter choose reset mode
[AMD Public Use]
Hi Wenhui,
[AMD Public Use]
Hi Hawking,
Not sure If there is a situation that we pass through the physical device to a
vm, the condition check " if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
amdgpu_sriov_runtime(adev)) " in function amdgpu_mm_rreg should be true when
we call RREG32_SOC15, is it correct?
[AMD Public Use]
Hi, Hawking,
Got it. Thanks for your expiation. It looks good to me now.
Reviewed-by: Dennis Li
Best Regards
Dennis Li
-Original Message-
From: Zhang, Hawking
Sent: Monday, July 13, 2020 1:44 PM
To: Sheng, Wenhui ; Li, Dennis ;
amd-gfx@lists.freedesktop.org
[AMD Public Use]
HI Hawking
I have merged in_ras_intr & use_baco to the function
amdgpu_ras_need_emergency_restart, If I also move the check of reboot logic
code to the new added function, variable need_emergency_restart Couldn't be
used for the following if check in function
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Xiaojie Yuan
Sent: Monday, July 13, 2020 14:00
To: amd-gfx@lists.freedesktop.org
Cc: Yuan, Xiaojie
Subject: [PATCH] drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs files
to
to easily add new debugfs file w/o changing the hardcoded list count.
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 6 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c| 3 ++-
3 files changed, 8 insertions(+), 4
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