Cover the implementation details from outside(of power). Also preparing
for expanding this to swSMU.
Change-Id: I60072318d18926d196095123638d263bd4534b52
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 13
Enable mgpu fan boost feature on swSMU routines.
Change-Id: I2a48af3ed8b63cc1e601c8d6981e4d6bb3a0b7b8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c| 5 -
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 17 +
Support Navi1X mgpu fan boost enablement.
Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h | 4 +++-
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 21 +++
2 files changed, 24 insertions(+), 1
Support Sienna Cichlid mgpu fan boost enablement.
Change-Id: Ibcaeeff7c0accb490402a1714d23adbe1bb7804e
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
This patch adds a new trace event to track the PTE update
events. This specific event will provide information like:
- start and end of virtual memory mapping
- HW engine flags for the map
- physical address for mapping
This will be particularly useful for memory profiling tools
(like RMV) which
[AMD Official Use Only - Internal Distribution Only]
There is already a prompt in amdgpu_dpm_baco_reset() about the "GPU BACO reset".
dev_info(adev->dev, "GPU BACO reset\n");
So, debug prompts on the baco reset paths may be not needed.
BR
Evan
-Original Message-
From: amd-gfx On Behalf
[AMD Official Use Only - Internal Distribution Only]
Hi, Christian,
Re: I was wondering the same thing for the amdgpu_gem_va_ioctl() as well. We
shouldn't have any hardware access here, so taking the reset_sem looks like
overkill to me.
[Dennis Li] amdgpu_vm_bo_unmap,
[AMD Official Use Only - Internal Distribution Only]
Hi, Felix,
Re: It may be better to fix it the other way around in
amdgpu_amdkfd_alloc_gtt_mem. Always take the reset_sem inside the reservation.
Otherwise you will never be able to take the reset_sem while any BOs are
reserved. That's
[AMD Official Use Only - Internal Distribution Only]
Alex, Yes I saw the same clean up for gfxhub. Will do it when I get a chance.
Regards,
Oak
-Original Message-
From: Alex Deucher
Sent: Tuesday, August 11, 2020 2:56 PM
To: Zeng, Oak
Cc: amd-gfx list ; Deucher, Alexander
Subject:
On Tue, Aug 11, 2020 at 1:50 PM Oak Zeng wrote:
>
> Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
> implementation of most mmhub functions are called from a general
> function pointer, instead of calling different function for
> different ASIC. Simplify the code by deleting
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
implementation of most mmhub functions are called from a general
function pointer, instead of calling different function for
different ASIC. Simplify the code by deleting duplicate functions
Change-Id:
Am 11.08.20 um 18:04 schrieb Alex Deucher:
ACPI, ROM, PCI BAR, etc.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 28 ++--
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
Am 11.08.20 um 15:57 schrieb Felix Kuehling:
Am 2020-08-11 um 5:32 a.m. schrieb Dennis Li:
[ 653.902305] ==
[ 653.902928] WARNING: possible circular locking dependency detected
[ 653.903517] 5.6.0-deli-v5.6-2848-g3f3109b0e75f #1 Tainted: G
Acked-by: Nirmoy Das for both patches.
On 8/11/20 6:04 PM, Alex Deucher wrote:
When we reset the GPU, note what type of reset will be
used. This makes debugging different reset scenarios
more clear as the driver may use different reset
methods depending on conditions on the system.
ACPI, ROM, PCI BAR, etc.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 28 ++--
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index
When we reset the GPU, note what type of reset will be
used. This makes debugging different reset scenarios
more clear as the driver may use different reset
methods depending on conditions on the system.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/cik.c | 2 ++
[AMD Public Use]
Thanks for your fix. The patch is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Nirmoy Das
Sent: Tuesday, August 11, 2020 10:18 PM
To: amd-gfx@lists.freedesktop.org
Cc: Das, Nirmoy
Subject: [PATCH 1/1] drm/amdgpu: pass NULL
Fixes: c030f2e4166c3f55 (drm/amdgpu: add amdgpu_ras.c to support ras (v2))
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
Am 2020-08-11 um 2:27 a.m. schrieb Huang Rui:
> Renoir only has one sdma instance, it will get failed once query the
> sdma1 registers. So use switch-case instead of static register array.
>
> Signed-off-by: Huang Rui
> ---
> .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 31 +--
Am 2020-08-11 um 5:32 a.m. schrieb Dennis Li:
> [ 653.902305] ==
> [ 653.902928] WARNING: possible circular locking dependency detected
> [ 653.903517] 5.6.0-deli-v5.6-2848-g3f3109b0e75f #1 Tainted: G OE
> [ 653.904098]
There are a few cases when the flags can change, for example DCC can be
disabled due to a hw limitation in the 3d engine. Modifiers give the
misleading impression that they help with that, but they don't. They don't
really help with anything.
Marek
On Mon., Aug. 10, 2020, 08:30 Christian König,
[AMD Public Use]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Huang Rui
Sent: Tuesday, August 11, 2020 2:27 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Huang, Ray
Subject: [PATCH] drm/amdkfd: fix the wrong sdma instance query for
This patch will ignore non-fatal errors and try to
stop amdgpu's sw stack on fatal errors.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 56 -
1 file changed, 54 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
[AMD Public Use]
Acked-by: Alex Deucher
From: Quan, Evan
Sent: Monday, August 10, 2020 11:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: bump NAVI12 driver if version
To fit the latest SMU
[AMD Public Use]
Series is:
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Monday, August 10, 2020 11:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 1/2] drm/amd/powerplay: update the metrics table cache interval
Am 2020-08-11 um 7:45 a.m. schrieb Huang Rui:
> On Fri, Aug 07, 2020 at 11:00:38PM +0800, Kuehling, Felix wrote:
>> Am 2020-08-07 um 4:25 a.m. schrieb Huang Rui:
>>> We still have a few iommu issues which need to address, so force raven
>>> as "dgpu" path for the moment.
>>>
>>> Will enable
On Fri, Aug 07, 2020 at 11:00:38PM +0800, Kuehling, Felix wrote:
> Am 2020-08-07 um 4:25 a.m. schrieb Huang Rui:
> > We still have a few iommu issues which need to address, so force raven
> > as "dgpu" path for the moment.
> >
> > Will enable IOMMUv2 since the issues are fixed.
>
> Do you mean
[AMD Official Use Only - Internal Distribution Only]
Quick grep says it is protected like that ... can you pls paste the full build
error without {}?
-Daniel
[Dennis Li] hi, Daniel, the full build error as the following:
make: Entering directory
[ 653.902305] ==
[ 653.902928] WARNING: possible circular locking dependency detected
[ 653.903517] 5.6.0-deli-v5.6-2848-g3f3109b0e75f #1 Tainted: G OE
[ 653.904098] --
[
On Tue, Aug 11, 2020 at 10:57:02AM +0300, Dan Carpenter wrote:
> On Mon, Aug 10, 2020 at 08:41:14PM +0200, Marion & Christophe JAILLET wrote:
> >
> > Le 10/08/2020 à 17:42, Dan Carpenter a écrit :
> > > On Sun, Aug 09, 2020 at 10:34:06PM +0200, Christophe JAILLET wrote:
> > > > When '*sgt' is
[AMD Public Use]
Hi Christian,
Since it's out of amdgpu driver scope, so I just attached my patch in this
email thread instead of sending it by git sent-email.
Regards,
Guchun
-Original Message-
From: Koenig, Christian
Sent: Tuesday, August 11, 2020 3:52 PM
To: Chen, Guchun ; Li,
On Mon, Aug 10, 2020 at 08:41:14PM +0200, Marion & Christophe JAILLET wrote:
>
> Le 10/08/2020 à 17:42, Dan Carpenter a écrit :
> > On Sun, Aug 09, 2020 at 10:34:06PM +0200, Christophe JAILLET wrote:
> > > When '*sgt' is allocated, we must allocated 'sizeof(**sgt)' bytes instead
> > > of
Nice catch, it's not often that we stumble over something like this :)
Can you provide a patch to fix this? Problem is that we probably won't
be able to push it to the AMD servers, but I can probably merge it
through drm-misc-next.
Until this is fixed feel free to commit the patch with the
On Tue, Aug 11, 2020 at 9:40 AM Christian König
wrote:
>
> Am 11.08.20 um 09:36 schrieb Chen, Guchun:
> > [AMD Public Use]
> >
> >> -down_write(>reset_sem);
> >> +if (hive) {
> >> +down_write_nest_lock(>reset_sem, >hive_lock);
> >> +} else
> >> +
[AMD Public Use]
# define down_write_nest_lock(sem, nest_lock) \
do {\
typecheck(struct lockdep_map *, &(nest_lock)->dep_map); \
_down_write_nest_lock(sem, &(nest_lock)->dep_map); \
} while (0);
Am 11.08.20 um 09:36 schrieb Chen, Guchun:
[AMD Public Use]
- down_write(>reset_sem);
+ if (hive) {
+ down_write_nest_lock(>reset_sem, >hive_lock);
+ } else
+ down_write(>reset_sem);
Coding style nit pick: You should drop the {} here.
{} could
[AMD Public Use]
> - down_write(>reset_sem);
> + if (hive) {
> + down_write_nest_lock(>reset_sem, >hive_lock);
> + } else
> + down_write(>reset_sem);
Coding style nit pick: You should drop the {} here.
{} could not be dropped here, as down_write_nest_lock Is
On Tue, Aug 11, 2020 at 4:12 AM Dennis Li wrote:
>
> [ 584.110304]
> [ 584.110590] WARNING: possible recursive locking detected
> [ 584.110876] 5.6.0-deli-v5.6-2848-g3f3109b0e75f #1 Tainted: G OE
> [ 584.64]
Am 11.08.20 um 04:12 schrieb Dennis Li:
[ 584.110304]
[ 584.110590] WARNING: possible recursive locking detected
[ 584.110876] 5.6.0-deli-v5.6-2848-g3f3109b0e75f #1 Tainted: G OE
[ 584.64]
[AMD Public Use]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Sheng, Wenhui
Sent: Tuesday, August 11, 2020 14:30
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhang, Hawking ;
Clements, John ; Sheng, Wenhui
Subject: [PATCH 3/3] drm/amdgpu:
[AMD Public Use]
Series is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: Sheng, Wenhui
Sent: Tuesday, August 11, 2020 2:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun ; Zhang, Hawking ;
Clements, John ; Sheng, Wenhui
Subject: [PATCH 3/3] drm/amdgpu:
After amdgpu driver loading successfully, we can use
RAP debugfs interface /dri/xxx/rap_test
to trigger RAP test.
Currently only L0 validate test is supported.
v2: refine amdgpu_rap.h
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
Enable the RAP TA loading path and add RAP test
trigger interface.
v2: fix potential mem leak issue
Signed-off-by: Wenhui Sheng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 183 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 17 ++
The RAP TA contains tests used to verify if
RAP(Register Access Policy), or otherwise known
as Security Policy is applied correctly
by PSP BL
The RAP test is a measure to ensure that we reduce
the avenue of complexity and mistakes when dealing
with RAP in post-si execution, where debugging
Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.
Signed-off-by: Huang Rui
---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 31 +--
1 file changed, 22 insertions(+), 9 deletions(-)
diff
Change to dynamically create and release hive info object,
which help driver support more hives in the future.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8a55b0bc044a..fdfdc2f678c9 100644
---
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