Re: [PATCH] drm/amdgpu: ih reroute for newer asics than vega20

Am 2021-03-26 um 11:33 a.m. schrieb Alex Sierra: > Starting Arcturus, it supports ih reroute through mmio directly > in bare metal environment. This is also valid for newer asics > such as Aldebaran. > > Signed-off-by: Alex Sierra > Acked-by: Christian König > Reviewed-by: Hawking Zhang

[PATCH] drm/amd/display: Fix black screen with scaled modes on some eDP panels

[why] This was a regression introduced by commit c1218dbe223f - 'drm/amd/display: Skip modeset for front porch change' Due to the change how timing parameters were set, scaled modes would cause a black screen on some eDP panels. Would probably apply to other displays (i.e. even non-eDP) that

[PATCH 20/21] drm/amd/display: Disable MALL when SMU not present

From: Chris Park [Why] Bring-up purpose code to disable DMUB calling into SMU and timeout for MALL when SMU is not present. [How] Disable MALL when SMU is not present. Signed-off-by: Chris Park Reviewed-by: Nicholas Kazlauskas Acked-by: Anson Jacob ---

[PATCH 21/21] drm/amd/display: 3.2.129

From: Aric Cyr This version brings along following features/fixes: - LTTPR improvements - Disable MALL when SMU not present - Fix bug in HW that causes P-State to hang when DPG is enabled in certain conditions - Update code path for enabling DPG - Update display endpoint control path - Add

[PATCH 19/21] drm/amd/display: [FW Promotion] Release 0.0.58

From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

[PATCH 18/21] drm/amd/display: add log for automated test

From: Qingqing Zhuo [Why] Add log for easier debug purposes. Signed-off-by: Qingqing Zhuo Reviewed-by: Nicholas Kazlauskas Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 1 file changed, 4 insertions(+) diff --git

[PATCH 17/21] drm/amd/display: Set max TTU on DPG enable

From: Wesley Chalmers [WHY] There is a bug in HW that causes P-State to hang when DPG is enabled in certain conditions. [HOW] The solution is to force MIN_TTU_VBLANK register to maximum value whenever DPG has been enabled. Make stream do a full update on test pattern change, so that the TTUs

[PATCH 15/21] drm/amd/display: Update display endpoint control path.

From: Jimmy Kizito [Why] Some display endpoints may be dynamically mapped to the link encoders which drive them. [How] Update the code paths for display enabling/disabling to accommodate the dynamic association between links and link encoders. Signed-off-by: Jimmy Kizito Reviewed-by: Jun Lei

[PATCH 14/21] drm/amd/display: Add dynamic link encoder selection.

From: Jimmy Kizito [Why] Some display endpoints may be programmably mapped to compatible link encoders. The assignment of link encoders to links has to be dynamic to accommodate the increased flexibility in comparison to conventional display endpoints. [How] - Add link encoder assignment

[PATCH 16/21] drm/amd/display: New path for enabling DPG

From: Wesley Chalmers [WHY] We want to make enabling test pattern a part of the stream update code path. This change is the first step towards that goal. Signed-off-by: Wesley Chalmers Reviewed-by: Aric Cyr Reviewed-by: Tony Cheng Acked-by: Anson Jacob ---

[PATCH 13/21] drm/amd/display: Fix MST topology debugfs

From: Eryk Brol [why] The drm dump_topology function was previously called on all DP connectors. This resulted in empty topology dumps for those connectors which weren't root MST nodes. [how] Make sure we only dump topology from the root MST node. Signed-off-by: Eryk Brol Reviewed-by:

[PATCH 12/21] drm/amd/display: LTTPR config logic

From: Wesley Chalmers [WHY] Some systems can enable LTTPR through bits in BIOS, while other systems can be configured at boot to enable LTTPR. Some configs enable Non-Transparent mode, while others enable Transparent mode. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson

[PATCH 11/21] drm/amd/display: Enumerate LTTPR modes

From: Wesley Chalmers [WHY] There are three possible modes for LTTPR: - Non-LTTPR mode, where AUX timeout is 400 us and no per-hop link training is done - LTTPR Transparent mode, where AUX timeout is 3200 us and no per-hop link training is done - LTTPR Non-Transparent mode, where AUX timeout is

[PATCH 09/21] drm/amd/display: Rename fs_params to hdr_tm_params

From: Krunoslav Kovac [Why] Renaming structure to better indicate its meaning. Signed-off-by: Krunoslav Kovac Reviewed-by: Aric Cyr Acked-by: Anson Jacob Acked-by: Anthony Koo --- drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 +++---

[PATCH 10/21] drm/amd/display: Interface for LTTPR interop

From: Wesley Chalmers [WHY] The logic to toggle LTTPR transparent/non-transparent requires 2 flags provided by BIOS [HOW] Repurpose the interface to get dce caps so both LTTPR querying functions can use them. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson Jacob ---

[PATCH 08/21] drm/amd/display: Fix typo for variable name

From: Vladimir Stempen [why] Word "remainder" was misspelled as "reminder" in reduceSizeAndFraction method variable. [how] Fix the spelling. Signed-off-by: Vladimir Stempen Reviewed-by: Alexander Deucher Reviewed-by: Bindu R Acked-by: Anson Jacob ---

[PATCH 03/21] drm/amd/display: Fix static checker warnings on tracebuff_fb

From: "Leo (Hanghong) Ma" [Why] Static analysis on linux-next has found a potential null pointer dereference; [How] Refactor the function, add ASSERT and remove the unnecessary check. Signed-off-by: Leo (Hanghong) Ma Reviewed-by: Harry Wentland Acked-by: Anson Jacob ---

[PATCH 07/21] drm/amd/display: add mod hdcp interface for supporting encryption state query

From: Wenjing Liu Signed-off-by: Wenjing Liu Reviewed-by: George Shen Acked-by: Anson Jacob --- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 +++ .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 4 +- .../display/modules/hdcp/hdcp1_execution.c| 37 +++

[PATCH 05/21] drm/amd/display: enable DP DSC Compliance automation

From: Qingqing Zhuo [Why] Color depth data is not parsed during test requests. [How] Update display color depth according to color depth request from the test equipment. Signed-off-by: Qingqing Zhuo Reviewed-by: Nicholas Kazlauskas Acked-by: Anson Jacob ---

[PATCH 06/21] drm/amd/display: define mod_hdcp_display_disable_option struct

From: Wenjing Liu Signed-off-by: Wenjing Liu Reviewed-by: George Shen Acked-by: Anson Jacob --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 6 +++--- drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c| 4 ++-- drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 10

[PATCH 02/21] drm/amd/display: Add refresh rate trace

From: Rodrigo Siqueira When we have to debug VRR issues, we usually want to know the current refresh rate; for this reason, it is handy to have a way to check in real-time the refresh rate value. This commit introduces a kernel trace that can provide such information. Signed-off-by: Rodrigo

[PATCH 01/21] drm/amd/display: BIOS LTTPR Caps Interface

From: Wesley Chalmers [WHY] Some platforms will have LTTPR capabilities forced on by VBIOS flags; the functions added here will access those flags. Signed-off-by: Wesley Chalmers Reviewed-by: Jun Lei Acked-by: Anson Jacob --- .../drm/amd/display/dc/bios/bios_parser2.c| 139

[PATCH 04/21] drm/amd/display: Guard ASSR with internal display flag

From: Stylon Wang [Why] ASSR enabling only considers capability declared in DPCD. We also need to check whether the connector is internal. [How] ASSR enabling need to check both DPCD capability and internal display flag. Signed-off-by: Stylon Wang Reviewed-by: Harry Wentland Acked-by: Anson

[PATCH 00/21] DC Patches March 26, 2021

This patchset brings along following features/fixes: - LTTPR improvements - Disable MALL when SMU not present - Fix bug in HW that causes P-State to hang when DPG is enabled in certain conditions - Update code path for enabling DPG - Update display endpoint control path

RE: [PATCH] drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend

[AMD Public Use] > -Original Message- > From: amd-gfx On Behalf Of Alex > Deucher > Sent: 2021/March/26, Friday 4:58 PM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander > Subject: [PATCH] drm/amdgpu/vangogh: don't check for dpm in > is_dpm_running when in suspend > > Do the

RE: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on resume

[AMD Public Use] > -Original Message- > From: Alex Deucher > Sent: 2021/March/26, Friday 5:01 PM > To: Deucher, Alexander > Cc: Liu, Zhan ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on > resume > > Looks like RN is immune due to

Re: [PATCH v2] drm/mst: Enhance MST topology logging

pushed! thanks for the patch On Thu, 2021-03-25 at 14:06 -0400, Eryk Brol wrote: > [why] > MST topology print was missing fec logging and pdt printed > as an int wasn't clear. vcpi and payload info was printed as an > arbitrary series of ints which requires user to know the ordering > of the

Re: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on resume

Looks like RN is immune due to the way it's is_dpm_running function is implemented. Maybe something like this is a better solution: https://patchwork.freedesktop.org/patch/426293/ Alex On Fri, Mar 26, 2021 at 10:12 AM Deucher, Alexander wrote: > > [AMD Official Use Only - Internal Distribution

[PATCH] drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend

Do the same thing we do for Renoir. We can check, but since the sbios has started DPM, it will always return true which causes the driver to skip some of the SMU init when it shouldn't. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 5 + 1 file changed,

[PATCH v2 20/20] drm/dp_mst: Convert drm_dp_mst_topology.c to drm_err()/drm_dbg*()

And finally, convert all of the code in drm_dp_mst_topology.c over to using drm_err() and drm_dbg*(). Note that this refactor would have been a lot more complicated to have tried writing a coccinelle script for, so this whole thing was done by hand. v2: * Fix line-wrapping in

[PATCH v2 19/20] drm/dp_mst: Drop DRM_ERROR() on kzalloc() fail in drm_dp_mst_handle_up_req()

Checkpatch was complaining about this - there's no need for us to print errors when kzalloc() fails, as kzalloc() will already WARN for us. So, let's fix that before converting things to make checkpatch happy. Signed-off-by: Lyude Paul Cc: Robert Foss --- drivers/gpu/drm/drm_dp_mst_topology.c

[PATCH v2 18/20] drm/dp_dual_mode: Convert drm_dp_dual_mode_helper.c to using drm_err/drm_dbg_kms()

Next step in the conversion, move everything in drm_dp_dual_mode_helper.c over to using drm_err() and drm_dbg_kms(). This was done using the following cocci script: @@ expression list expr; @@ ( - DRM_DEBUG_KMS(expr); + drm_dbg_kms(dev, expr); | - DRM_ERROR(expr); +

[PATCH v2 16/20] drm/dp_mst: Pass drm_dp_mst_topology_mgr to drm_dp_get_vc_payload_bw()

Since this is one of the few functions in drm_dp_mst_topology.c that doesn't have any way of getting access to a drm_device, let's pass the drm_dp_mst_topology_mgr down to this function so that it can use drm_dbg_kms(). Signed-off-by: Lyude Paul --- drivers/gpu/drm/drm_dp_mst_topology.c |

[PATCH v2 17/20] drm/dp: Convert drm_dp_helper.c to using drm_err/drm_dbg_*()

Now that we've added a back-pointer to drm_device to drm_dp_aux, made drm_dp_aux available to any functions in drm_dp_helper.c which need to print to the kernel log, and ensured all of our logging uses a consistent format, let's do the final step of the conversion and actually move everything over

[PATCH v2 15/20] drm/dp_dual_mode: Pass drm_device to drm_lspcon_(get|set)_mode()

So that we can start using drm_dbg_*() throughout the DRM DP helpers. Signed-off-by: Lyude Paul --- drivers/gpu/drm/drm_dp_dual_mode_helper.c | 8 +--- drivers/gpu/drm/i915/display/intel_lspcon.c | 12 +++- include/drm/drm_dp_dual_mode_helper.h | 4 ++-- 3 files changed,

[PATCH v2 14/20] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_get_tmds_output()

Another function to pass drm_device * down to so we can start using the drm_dbg_*() in the DRM DP helpers. Signed-off-by: Lyude Paul --- drivers/gpu/drm/drm_dp_dual_mode_helper.c | 5 +++-- include/drm/drm_dp_dual_mode_helper.h | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff

[PATCH v2 13/20] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_max_tmds_clock()

Another function we need to pass drm_device down to in order to start using drm_dbg_*(). Signed-off-by: Lyude Paul --- drivers/gpu/drm/drm_dp_dual_mode_helper.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- include/drm/drm_dp_dual_mode_helper.h | 2 +- 3 files changed, 4

[PATCH v2 10/20] drm/dp: Always print aux channel name in logs

Since we're about to convert everything in drm_dp_helper.c over to using drm_dbg_*(), let's also make our logging more consistent in drm_dp_helper.c while we're at it to ensure that we always print the name of the AUX channel in question. Signed-off-by: Lyude Paul ---

[PATCH v2 11/20] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_detect()

Since we're about to be using drm_dbg_*() throughout the DP helpers, we'll need to be able to access the DRM device in the dual mode DP helpers as well. Note however that since drm_dp_dual_mode_detect() can be called with DDC adapters that aren't part of a drm_dp_aux struct, we need to pass down

[PATCH v2 12/20] drm/dp_dual_mode: Pass drm_device to drm_dp_dual_mode_set_tmds_output()

Another function that we'll need to pass a drm_device (and not drm_dp_aux) down to so that we can move over to using drm_dbg_*(). Signed-off-by: Lyude Paul --- drivers/gpu/drm/drm_dp_dual_mode_helper.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +--

[PATCH v2 09/20] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()

So that we can start using drm_dbg_*() for drm_dp_link_train_channel_eq_delay() and drm_dp_lttpr_link_train_channel_eq_delay(). Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- drivers/gpu/drm/drm_dp_helper.c

[PATCH v2 05/20] drm/dp: Add backpointer to drm_device in drm_dp_aux

This is something that we've wanted for a while now: the ability to actually look up the respective drm_device for a given drm_dp_aux struct. This will also allow us to transition over to using the drm_dbg_*() helpers for debug message printing, as we'll finally have a drm_device to reference for

[PATCH v2 06/20] drm/dp: Clarify DP AUX registration time

The docs we had for drm_dp_aux_init() and drm_dp_aux_register() were mostly correct, except for the fact that they made the assumption that all AUX devices were grandchildren of their respective DRM devices. This is the case for most normal GPUs, but is almost never the case with SoCs and display

[PATCH v2 08/20] drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()

So that we can start using drm_dbg_*() in drm_dp_link_train_clock_recovery_delay(). Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- drivers/gpu/drm/drm_dp_helper.c | 3 ++-

[PATCH v2 07/20] drm/print: Fixup DRM_DEBUG_KMS_RATELIMITED()

Since we're about to move drm_dp_helper.c over to drm_dbg_*(), we'll want to make sure that we can also add ratelimited versions of these macros in order to retain some of the previous debugging output behavior we had. However, as I was preparing to do this I noticed that the current rate limited

[PATCH v2 02/20] drm/tegra: Don't register DP AUX channels before connectors

As pointed out by the documentation for drm_dp_aux_register(), drm_dp_aux_init() should be used in situations where the AUX channel for a display driver can potentially be registered before it's respective DRM driver. This is the case with Tegra, since the DP aux channel exists as a platform

[PATCH v2 04/20] drm/nouveau/kms/nv50-: Move AUX adapter reg to connector late register/early unregister

Since AUX adapters on nouveau have their respective DRM connectors as parents, we need to make sure that we register then after their connectors. Signed-off-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_connector.c | 26 ++--- 1 file changed, 18 insertions(+), 8

[PATCH v2 03/20] drm/bridge/cdns-mhdp8546: Register DP aux channel with userspace

Just adds some missing calls to drm_dp_aux_register()/drm_dp_aux_unregister() for when we attach/detach the bridge. Signed-off-by: Lyude Paul --- drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git

[PATCH v2 01/20] drm/dp: Fixup kernel docs for struct drm_dp_aux

* Make sure that struct members are referred to using @, otherwise they won't be formatted as such * Make sure to refer to other struct types using & so they link back to each struct's definition * Make sure to precede constant values with % so they're formatted correctly Signed-off-by:

[PATCH v2 00/20] drm: Use new DRM printk funcs (like drm_dbg_*()) in DP helpers

Since it's been asked quite a few times on some of the various DP related patch series I've submitted to use the new DRM printk helpers, and it technically wasn't really trivial to do this before due to the lack of a consistent way to find a drm_device for an AUX channel, this patch series aims to

Re: [PATCH] drm/amdgpu/display: fix merge breakage

Nevermind, I think I screwed this up locally. Alex On Fri, Mar 26, 2021 at 4:07 PM Alex Deucher wrote: > > Looks like this got accidently dropped. > > Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of > https://gitlab.freedesktop.org/agd5f/linux into drm-next") > Signed-off-by:

[PATCH] drm/amdgpu/display: fix merge breakage

Looks like this got accidently dropped. Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next") Signed-off-by: Alex Deucher Cc: daniel.vet...@ffwll.ch --- drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c | 4

Re: [PATCH] drm/amdkfd: dqm fence memory corruption

Am 2021-03-26 um 5:38 a.m. schrieb Qu Huang: > On 2021/1/28 5:50, Felix Kuehling wrote: >> Am 2021-01-27 um 7:33 a.m. schrieb Qu Huang: >>> Amdgpu driver uses 4-byte data type as DQM fence memory, >>> and transmits GPU address of fence memory to microcode >>> through query status PM4 message.

RE: [pull] amdgpu, amdkfd, radeon drm-next-5.12

[AMD Public Use] On Thu, Feb 18, 2021 at 11:15 PM Alex Deucher wrote: >> >> Hi Dave, Daniel, >> >> Fixes for 5.12. >> >> The following changes since commit 4c3a3292730c56591472717d8c5c0faf74f6c6bb: >> >> drm/amd/display: fix unused variable warning (2021-02-05 09:49:44 >> +1000) >> >> are

Re: [PATCH v2] drm/mst: Enhance MST topology logging

[AMD Official Use Only - Internal Distribution Only] Hi Lyude, Yes, I would appreciate it if you could push this to drm-misc-next for me. Thank you for your comments and review! Best, Eryk From: Lyude Paul Sent: Thursday, March 25, 2021 6:30 PM To: Brol, Eryk ;

Re: [pull] amdgpu, amdkfd, radeon drm-next-5.12

On Thu, Feb 18, 2021 at 11:15 PM Alex Deucher wrote: > > Hi Dave, Daniel, > > Fixes for 5.12. > > The following changes since commit 4c3a3292730c56591472717d8c5c0faf74f6c6bb: > > drm/amd/display: fix unused variable warning (2021-02-05 09:49:44 +1000) > > are available in the Git repository at:

[PATCH] amd/display: allow non-linear multi-planar formats

Accept non-linear buffers which use a multi-planar format, as long as they don't use DCC. Tested on GFX9 with NV12. Signed-off-by: Simon Ser Cc: Alex Deucher Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Bas Nieuwenhuizen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11

Re: [PATCH] drm: Update MST First Link Slot Information Based on Encoding Format

On Thu, 2021-03-25 at 23:14 -0400, Fangzhi Zuo wrote: > 8b/10b encoding format requires to reserve the first slot for > recording metadata. Real data transmission starts from the second slot, > with a total of available 63 slots available. > > In 128b/132b encoding format, metadata is transmitted

[PATCH 1/1] drm/amdgpu: fix offset calculation in amdgpu_vm_bo_clear_mappings()

Offset calculation wasn't correct as start addresses are in pfn not in bytes. CC: sta...@vger.kernel.org Signed-off-by: Nirmoy Das Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH 1/1] drm/amdgpu: fix offset calculation amdgpu_vm_bo_clear_mappings()

Am 26.03.21 um 16:25 schrieb Nirmoy Das: Offset calculation wasn't correct as start addresses are in pfn not in bytes. Signed-off-by: Nirmoy Das Wow that code has been around for a while without noticing this. Really good catch. Patch is Reviewed-by: Christian König CC:

[PATCH] drm/amdgpu: ih reroute for newer asics than vega20

Starting Arcturus, it supports ih reroute through mmio directly in bare metal environment. This is also valid for newer asics such as Aldebaran. Signed-off-by: Alex Sierra Acked-by: Christian König Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 6 +++--- 1 file

[PATCH 1/1] drm/amdgpu: fix offset calculation amdgpu_vm_bo_clear_mappings()

Offset calculation wasn't correct as start addresses are in pfn not in bytes. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

Re: Need to support mixed memory mappings with HMM

Am 26.03.21 um 15:49 schrieb Felix Kuehling: Am 2021-03-26 um 4:50 a.m. schrieb Christian König: Am 25.03.21 um 17:28 schrieb Felix Kuehling: Am 2021-03-25 um 12:22 p.m. schrieb Christian König: My idea is to change the amdgpu_vm_update_mapping interface to use some high-bit in the

Re: [PATCH] drm/amd/display: Try YCbCr420 color when YCbCr444 fails

On 2021-03-24 4:23 p.m., Alex Deucher wrote: On Wed, Mar 17, 2021 at 11:25 AM Werner Sembach wrote: When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which

Re: 回复: [PATCH v3] drm/scheduler re-insert Bailing job to avoid memleak

Hi Monk, I can't disagree more. The fundamental problem here is that we have pushed a design without validating if it really fits into the concepts the Linux kernel mandates here. My mistake was that I haven't pushed back hard enough on the initial design resulting in numerous cycles of

Re: Need to support mixed memory mappings with HMM

Am 2021-03-26 um 4:50 a.m. schrieb Christian König: > > > Am 25.03.21 um 17:28 schrieb Felix Kuehling: >> Am 2021-03-25 um 12:22 p.m. schrieb Christian König: My idea is to change the amdgpu_vm_update_mapping interface to use some high-bit in the pages_addr array to

Re: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on resume

[AMD Official Use Only - Internal Distribution Only] Can someone double check this on RN/CZN with S3 and S0ix? Alex From: Liu, Zhan Sent: Friday, March 26, 2021 1:46 AM To: Deucher, Alexander ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject:

[PATCH] drm/amd/display: add DMCUB trace irq support for DCN302

Otherwise, below errors will be found on DIMGREY_CAVEFISH with DCN302. Error log observed in driver load: [drm:amdgpu_dm_irq_register_interrupt [amdgpu]] *ERROR* DM_IRQ: invalid irq_source: 0! Error observed in mode1_rest sequence: [ 27.265920] #PF: supervisor read access in kernel mode [

Re: [PATCH] drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers

On Fri, Mar 26, 2021 at 9:49 AM Tom St Denis wrote: > > Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher > --- > .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 6 ++ > .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h | 9 + > 2 files changed, 15

[PATCH] drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers

Signed-off-by: Tom St Denis --- .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 6 ++ .../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h | 9 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

Re: [PATCH] drm/amdkfd: dqm fence memory corruption

On 2021/1/28 5:50, Felix Kuehling wrote: Am 2021-01-27 um 7:33 a.m. schrieb Qu Huang: Amdgpu driver uses 4-byte data type as DQM fence memory, and transmits GPU address of fence memory to microcode through query status PM4 message. However, query status PM4 message definition and microcode

回复: [PATCH v3] drm/scheduler re-insert Bailing job to avoid memleak

[AMD Official Use Only - Internal Distribution Only] Hi Christian This is not correct or correct perspective, any design comes with its pros and cons, otherwise it wouldn't comes to kernel tree in the very beginning , it is just with time passed we have more and more requirement and feature

Re: [PATCH 3/4] Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"

Am 25.03.21 um 17:38 schrieb Oak Zeng: This reverts commit 34a33d4683cba7ba63c894132efb1998c0217631. We need a single sentence here why we do the revert and I think you need to reorder the patches. E.g. patch #3 should be #4 and #4 should be #3, otherwise you break the driver in between.

Re: [PATCH 1/4] drm/amdgpu: Macros for vram physical addr calculation

Am 25.03.21 um 17:38 schrieb Oak Zeng: Add one macro to calculate BO's GPU physical address. And another one to calculate BO's CPU physical address. Signed-off-by: Oak Zeng Suggested-by: Lijo Lazar Yeah, I though about doing that as well for a while. ---

Re: [PATCH v3] drm/scheduler re-insert Bailing job to avoid memleak

On 26/03/2021 02:04, Zhang, Jack (Jian) wrote: [AMD Official Use Only - Internal Distribution Only] Hi, Steve, Thank you for your detailed comments. But currently the patch is not finalized. We found some potential race condition even with this patch. The solution is under discussion and

Re: [PATCH v3] drm/scheduler re-insert Bailing job to avoid memleak

Hi guys, Am 26.03.21 um 03:23 schrieb Zhang, Jack (Jian): [AMD Official Use Only - Internal Distribution Only] Hi, Andrey, how u handle non guilty singnaled jobs in drm_sched_stop, currently looks like you don't call put for them and just explicitly free them as before Good point, I missed

Re: Need to support mixed memory mappings with HMM

Am 25.03.21 um 17:28 schrieb Felix Kuehling: Am 2021-03-25 um 12:22 p.m. schrieb Christian König: My idea is to change the amdgpu_vm_update_mapping interface to use some high-bit in the pages_addr array to indicate the page type. For the default page type (0) nothing really changes for the

RE: [PATCH] drm/amd/pm: Fix DPM level count on aldebaran

Reviewed-by: Feifei Xu From: Lazar, Lijo Sent: Friday, March 26, 2021 2:04 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Xu, Feifei ; Feng, Kenneth ; Wang, Kevin(Yang) Subject: [PATCH] drm/amd/pm: Fix DPM level count on aldebaran [AMD Public Use] Firmware returns zero-based

[PATCH] drm/amd/pm: Fix DPM level count on aldebaran

[AMD Public Use] Firmware returns zero-based max level, increment by one to get total levels. This fixes the issue of not showing all levels and current frequency when frequency is at max DPM level. Signed-off-by: Lijo Lazar lijo.la...@amd.com ---