SG BOs do not occupy space that is managed by TTM. So do not evict them.
This fixes unexpected evictions of KFD's userptr BOs. KFD only expects
userptr "evictions" in the form of MMU notifiers.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/ttm/ttm_bo.c | 4
1 file changed, 4
ttm_bo_swapout returns a non-0 value on success. Don't treat that as an
error in ttm_tt_populate.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/ttm/ttm_tt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index
Sriov gets suspend of IP block failed as return
value was not initialized.
v2: return 0 directly to align original code semantic before this
was broken out into a separate helper function instead of setting
initial values
Signed-off-by: Victor Zhao
---
[why]
DP 1.4a spec madates that if DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is
set, Extended Base Receiver Capability DPCD space must be used. Without
doing that, the three DPCD values that differ will be wrong, leading to
incorrect or limited functionality. MST link rate, for example, could
have a
Available with 68.18.0 and later PMFWs.
Change-Id: I0d7e61875101b476ab50f74ade6dc2aaf1e0bc24
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 13 -
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 +++
2 files changed, 11 insertions(+), 5
Supported by some latest ASICs.
Change-Id: I0bb26df87d10f1b356b5b9bf008a1422a8fe60d9
Signed-off-by: Evan Quan
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 62 +++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> -Original Message-
> From: Kasiviswanathan, Harish
> Sent: Tuesday, April 27, 2021 2:57 PM
> To: amd-gfx@lists.freedesktop.org; Greathouse, Joseph
>
> Cc: Kasiviswanathan, Harish
> Subject: [PATCH] drm/amdkfd: Add Aldebaran gws support
>
> v2: updated MEC FW version after validating
[why]
DP 1.4a spec madates that if DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is
set, Extended Base Receiver Capability DPCD space must be used. Without
doing that, the three DPCD values that differ will be wrong, leading to
incorrect or limited functionality. MST link rate, for example, could
have a
[AMD Official Use Only - Internal Distribution Only]
Hi,
drm/radeon/ part is still WIP (i.e. I doubt it'll work as is), but drm/i915 and
drm/nouveau/ should be OK. Would it be possible to test those while I'm
figuring out drm/radeon/ settings?
I'm pretty sure the follow-up change would affect
[why]
DP 1.4a spec madates that if DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT is
set, Extended Base Receiver Capability DPCD space must be used. Without
doing that, the three DPCD values that differ will be wrong, leading to
incorrect or limited functionality. MST link rate, for example, could
have a
v2: updated MEC FW version after validating gws with debugger
Signed-off-by: Harish Kasiviswanathan
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
Hi Dennis,
Should we check in the compute shader source codes? I only saw the shader
binaries. This will be helpful if people want to modify those shaders/fix
issues. The source code can be in a comment section above the binary.
Regards,
Oak
On 2021-04-27, 11:31 AM, "amd-gfx on behalf of
On 2021-04-27 10:51 a.m., Philip Yang wrote:
Add interface to remove address from fault filter ring by resetting
fault ring entry key, then future vm fault on the address will be
processed to recover.
Define fault key as atomic64_t type to use atomic read/set/cmpxchg key
to protect fault ring
On Tue, Apr 27, 2021 at 12:51 AM wrote:
>
> From: Pavan Kumar Ramayanam
>
> The runtime resume PM op disregards the return value from
> amdgpu_device_resume(), masking errors for failed resumes at the PM
> layer.
>
> Signed-off-by: Pavan Kumar Ramayanam
Subject should be prefixed with
Ok in this case looks good to me.
Christian.
Am 27.04.21 um 17:26 schrieb Zhang, Hawking:
[AMD Public Use]
This need to be done during reset as well.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: Tuesday, April 27, 2021 23:17
To: Zhang, Hawking ; Li, Dennis ;
[AMD Public Use]
This need to be done during reset as well.
Regards,
Hawking
-Original Message-
From: Christian König
Sent: Tuesday, April 27, 2021 23:17
To: Zhang, Hawking ; Li, Dennis ;
amd-gfx@lists.freedesktop.org; Deucher, Alexander ;
Kuehling, Felix ; Koenig, Christian
This is only done during bootup, isn't it?
Wouldn't it be better to use the normal IB pool instead of the direct
one? Or do we also need to do this during GPU reset?
Regards,
Christian.
Am 27.04.21 um 16:55 schrieb Zhang, Hawking:
[AMD Public Use]
Please split the following into another
This series is Acked-by: Oak Zeng
Regards,
Oak
On 2021-04-21, 9:31 PM, "dri-devel on behalf of Felix Kuehling"
wrote:
This patch series fixes DMA-mappings of system memory (GTT and userptr)
for KFD running on multi-GPU systems with IOMMU enabled. One SG-BO per
GPU is
Am 2021-04-27 um 10:29 a.m. schrieb Zeng, Oak:
> Regards,
> Oak
>
>
>
> On 2021-04-26, 11:56 PM, "Kuehling, Felix" wrote:
>
> Am 2021-04-26 um 8:35 p.m. schrieb Zeng, Oak:
> > Regards,
> > Oak
> >
> >
> >
> > On 2021-04-21, 9:31 PM, "amd-gfx on behalf of Felix
[AMD Public Use]
BTW, please explicitly call out aldebaran in either commit description or
subject since it is really aldebaran specific algorithm.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Tuesday, April 27, 2021 22:56
To: Li, Dennis ;
[AMD Official Use Only - Internal Distribution Only]
Good catch. I think we should probably just return 0 at the end to keep the
semantics of the original code before this was broken out into a separate
helper function.
Alex
From: amd-gfx on behalf of Victor
[AMD Public Use]
Please split the following into another patch when you commit the one. Other
than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
@@ -479,8 +710,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device
*adev,
die_id);
Add interface to remove address from fault filter ring by resetting
fault ring entry key, then future vm fault on the address will be
processed to recover.
Define fault key as atomic64_t type to use atomic read/set/cmpxchg key
to protect fault ring access by interrupt handler and interrupt
On Mon, 26 Apr 2021 13:38:49 -0400
Harry Wentland wrote:
> ## Introduction
>
> We are looking to enable HDR support for a couple of single-plane and
> multi-plane scenarios. To do this effectively we recommend new
> interfaces to drm_plane. Below I'll give a bit of background on HDR
> and why
The number of waves is changed to 8, so it is impossible to use old
solution to cover all sgprs.
Signed-off-by: Dennis Li
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index a2fe2dac32c1..2e6789a7dc46 100644
---
Regards,
Oak
On 2021-04-26, 11:56 PM, "Kuehling, Felix" wrote:
Am 2021-04-26 um 8:35 p.m. schrieb Zeng, Oak:
> Regards,
> Oak
>
>
>
> On 2021-04-21, 9:31 PM, "amd-gfx on behalf of Felix Kuehling"
wrote:
>
> Use DMABufs with dynamic attachment
On 2021-04-27 3:25 a.m., Christian
König wrote:
Am
26.04.21 um 23:26 schrieb Philip Yang:
Add interface to remove address from fault
filter ring by resetting
fault ring entry key, then future vm fault on the address will
In the documentation of functions, removed excess parameters, described
undocumented ones, and fixed syntax errors.
Signed-off-by: Fabio M. De Francesco
---
Changes from v1: Cc'ed all the maintainers.
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 12 ++--
Drop the last user of drm_mm_node.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index
This avoids reallocating scanout BOs on first pin in a lot of cases.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
Not used outside of that file.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
One of the last remaining uses of drm_mm_node.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
Now that we found the underlying problem we can re-apply this patch.
This reverts commit 867fee7f8821ff42e7308088cf0c3450ac49c17c.
v2: rebase on KFD changes
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 55 +-
[AMD Official Use Only - Internal Distribution Only]
Review-by: Emily Deng
>-Original Message-
>From: Jack Zhang
>Sent: Tuesday, April 27, 2021 6:03 PM
>To: amd-gfx@lists.freedesktop.org; Liu, Monk ; Deng,
>Emily ; Chen, JingWen
>Cc: Zhang, Jack (Jian)
>Subject: [PATCH]
Disable all ip's hw status to false before any hw_init.
Only set it to true until its hw_init is executed.
The old 5.9 branch has this change but somehow the 5.11 kernrel does
not have this fix.
Without this change, sriov tdr have gfx IB test fail.
Signed-off-by: Jack Zhang
---
Give initial values otherwise sriov will get suspend of
IP block failed
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
drm_modeset_lock_all() is not needed here, so it is replaced with
drm_modeset_lock(). The crtc list around which we are looping never
changes, therefore the only lock we need is to protect access to
crtc->state.
Suggested-by: Daniel Vetter
Suggested-by: Matthew Wilcox
Signed-off-by: Fabio M. De
On Mon, Apr 26, 2021 at 01:38:49PM -0400, Harry Wentland wrote:
>
> ## Introduction
>
> We are looking to enable HDR support for a couple of single-plane and
> multi-plane scenarios. To do this effectively we recommend new
> interfaces to drm_plane. Below I'll give a bit of background on HDR and
Am 26.04.21 um 23:26 schrieb Philip Yang:
Add interface to remove address from fault filter ring by resetting
fault ring entry key, then future vm fault on the address will be
processed to recover.
Define fault key as atomic64_t type to use atomic read/set/cmpxchg key
to protect fault ring
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