Acked-by: Christian König for the series.
Am 04.05.21 um 23:47 schrieb Luben Tuikov:
Classic normalization of a redundant variable.
There is no need to have two variables representing
the same quantity. Move up to the structure which
represents the object which determines their values.
Rename t
Am 04.05.21 um 17:03 schrieb Alex Deucher:
Change to 60s. This matches what we already do in virtualization.
Infinite timeout can lead to deadlocks in the kernel.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++-
drive
Reviewed-and-Tested by: Leo Liu
On 2021-05-04 9:27 p.m., Bas Nieuwenhuizen wrote:
Otherwise tiling modes that require the values form this field
(In particular _*_X) would be corrupted upon video decode.
Copied from the VCN v2 code.
Fixes: 99541f392b4d ("drm/amdgpu: add mc resume DPG mode for
Otherwise tiling modes that require the values form this field
(In particular _*_X) would be corrupted upon video decode.
Copied from the VCN v2 code.
Fixes: 99541f392b4d ("drm/amdgpu: add mc resume DPG mode for VCN3.0")
Signed-off-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
[AMD Public Use]
> Subject: [PATCH] platform/x86: Add missing LPS0 functions for AMD
Rafael might be willing to fix it up on commit, but if you end up needing to
re-spin
I think technically this subsystem prefix to match other stuff committed to
this file
should be:
"ACPI: PM: s2idle:"
>
> T
These are supposedly not required for AMD platforms,
but at least some HP laptops seem to require it to
properly turn off the keyboard backlight.
Based on a patch from Marcin Bachry .
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1230
Reviewed-by: Hans de Goede
Signed-off-by: Alex Deucher
Export the runtime-set "ras_hw_enabled" and
"ras_enabled" to debugfs, for debugging.
Cc: Alexander Deucher
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/driv
Remove redundant ras->supported, as this value
is also stored in adev->ras_features.
Use adev->ras_features, as that supercedes "ras",
since the latter is its member.
The dependency goes like this:
ras <== adev->ras_features <== hw_supported,
and is read as "ras depends on ras_features, which
dep
Rename,
ras_hw_supported --> ras_hw_enabled, and
ras_features --> ras_enabled,
to show that ras_enabled is a subset of
ras_hw_enabled, which itself is a subset
of the ASIC capability.
Cc: Alexander Deucher
Cc: John Clements
Cc: Hawking Zhang
Signed-off-by: Luben Tuikov
---
drivers/gpu
Move ras_hw_supported into struct amdgpu_dev.
The dependency is:
struct amdgpu_ras <== struct amdgpu_dev <== ASIC,
read as "struct amdgpu_ras depends on struct
amdgpu_dev, which depends on the hardware."
This can be loosely understood as, "if RAS is
supported, which is property of the ASIC (struct
Classic normalization of a redundant variable.
There is no need to have two variables representing
the same quantity. Move up to the structure which
represents the object which determines their values.
Rename to a consistent name, and export to debugfs
for debugging.
Luben Tuikov (4):
drm/amdgpu
Did you push this yet? I don't see it in drm-misc.
Thanks,
Alex
On Wed, Apr 28, 2021 at 5:06 AM Christian König
wrote:
>
> Well none. As I said I will push this upstream through drm-misc-next.
>
> Christian.
>
> Am 28.04.21 um 10:32 schrieb Deng, Emily:
>
> [AMD Official Use Only - Internal Di
On Wed, Apr 28, 2021 at 5:21 PM Alex Deucher wrote:
>
> On Tue, Apr 20, 2021 at 5:25 PM Alex Deucher wrote:
> >
> > On Fri, Apr 16, 2021 at 12:29 PM Mario Kleiner
> > wrote:
> > >
> > > Friendly ping to the AMD people. Nicholas, Harry, Alex, any feedback?
> > > Would be great to get this in soon
On Tue, Apr 27, 2021 at 5:45 AM Fabio M. De Francesco
wrote:
>
> drm_modeset_lock_all() is not needed here, so it is replaced with
> drm_modeset_lock(). The crtc list around which we are looping never
> changes, therefore the only lock we need is to protect access to
> crtc->state.
>
> Suggested-b
On Fri, Apr 30, 2021 at 2:05 PM wrote:
>
> From: Tom Rix
>
> Static analysis reports this problem
>
> amdgpu_pm.c:478:16: warning: The right operand of '<' is a garbage value
> for (i = 0; i < data.nums; i++) {
> ^ ~
>
> In some cases data is not set. Initialize to 0 an
On Mon, May 3, 2021 at 1:06 AM Kees Cook wrote:
>
> Hi,
>
> This is an attempt at fixing a bug[1] uncovered by the relocation of
> the slab freelist pointer offset, as well as some related clean-ups.
>
> I don't have hardware to do runtime testing, but it builds. ;)
>
> -Kees
>
> [1] https://bugzi
This reverts commit 96e27e8d919e52f30ea6b717e3cb70faa0b102cd.
This causes the SMU to fail to load the power state.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1583
Signed-off-by: Alex Deucher
Cc: Gustavo A. R. Silva
---
drivers/gpu/drm/radeon/si_dpm.c | 5 +++--
drivers/gpu/drm
Am 2021-04-28 um 11:11 a.m. schrieb Andrey Grodzovsky:
> Handle all DMA IOMMU gropup related dependencies before the
> group is removed.
>
> v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate
>
> Signed-off-by: Andrey Grodzovsky
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h
On 2021-05-04 3:03 a.m., Christian König wrote:
Am 03.05.21 um 22:43 schrieb Andrey Grodzovsky:
On 2021-04-29 3:08 a.m., Christian König wrote:
Am 28.04.21 um 17:11 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
v5: Drop IOMMU noti
On Tuesday, May 4th, 2021 at 11:43 AM, Bas Nieuwenhuizen
wrote:
> The builtin size check isn't really the right thing for AMD
> modifiers due to a couple of reasons:
>
> 1) In the format structs we don't do set any of the tilesize / blocks
> etc. to avoid having format arrays per modifier/GPU
>
Change to 60s. This matches what we already do in virtualization.
Infinite timeout can lead to deadlocks in the kernel.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 ++--
2 files changed, 5 insertions(+),
Good point. Thanks.
Eric
On 2021-05-04 10:30 a.m., Lazar, Lijo wrote:
[AMD Official Use Only - Internal Distribution Only]
Converting using pxm_to_node and then comparing against pxm value
looks a bit odd. Shouldn't the comparsion be between equals - node to
node or pxm to pxm?
Thanks,
L
[AMD Official Use Only - Internal Distribution Only]
Converting using pxm_to_node and then comparing against pxm value looks a bit
odd. Shouldn't the comparsion be between equals - node to node or pxm to pxm?
Thanks,
Lijo
From: Huang, JinHuiEric
Sent: Tuesday, M
[AMD Official Use Only - Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, May 4, 2021 22:02
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdg
On Mon, May 03, 2021 at 02:21:53PM -0400, Felix Kuehling wrote:
> Am 2021-05-01 um 1:03 p.m. schrieb Adrian Reber:
> > On Fri, Apr 30, 2021 at 09:57:45PM -0400, Felix Kuehling wrote:
> >> We have been working on a prototype supporting CRIU (Checkpoint/Restore
> >> In Userspace) for accelerated comp
On 1/9/21 7:42 AM, Mikhail Gavrilov wrote:
Hi folks!
I started to see this message every boot after replacing Radeon VII to 6900XT.
<...>
[6.333672] [drm] REG_WAIT timeout 1us * 10 tries -
mpc2_assert_idle_mpcc line:480
[6.335258] BUG: key 8b521bda9148 has not been registered!
[
Am 04.05.21 um 16:02 schrieb Alex Deucher:
Add emit mem sync callback for sdma_v5_0
In amdgpu sync object test, three threads created jobs
to send GFX IB and SDMA IB in sequence. After the first
GFX thread joined, sometimes the third thread will reuse
the same physical page to store the SDMA IB.
It's not needed here and has been added to the proper place
in the previous patch. This aligns with what we do for sdma 5.2.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5
Add emit mem sync callback for sdma_v5_0
In amdgpu sync object test, three threads created jobs
to send GFX IB and SDMA IB in sequence. After the first
GFX thread joined, sometimes the third thread will reuse
the same physical page to store the SDMA IB. There will
be a risk that SDMA will read GFX
Like I answer Oak's question,
"For GCD parsing, the relation of GCD to CCD is defined by AMD, generic
parsing in srat.c is considering a GCD as a new numa node which is not
suitable for our need."
GCD's pxm domain will get a wrong numa node which may be bigger than CCD
domains, so I have to d
On Fri, Apr 30, 2021 at 09:57:45PM -0400, Felix Kuehling wrote:
> We have been working on a prototype supporting CRIU (Checkpoint/Restore
> In Userspace) for accelerated compute applications running on AMD GPUs
> using ROCm (Radeon Open Compute Platform). We're happy to finally share
> this work pu
The builtin size check isn't really the right thing for AMD
modifiers due to a couple of reasons:
1) In the format structs we don't do set any of the tilesize / blocks
etc. to avoid having format arrays per modifier/GPU
2) The pitch on the main plane is pixel_pitch * bytes_per_pixel even
for tiled
[AMD Public Use]
> *numa_node > max_pxm
Why numa node number is compared to a proximity domain? Since you are already
using pxm_to_node() API, assume that should take care.
That also will avoid parsing ACPI_SRAT_TYPE_CPU_AFFINITY structs.
Thanks,
Lijo
-Original Message-
From: amd-gfx
On Mon, May 03, 2021 at 11:33:33AM +0300, Jani Nikula wrote:
> On Fri, 30 Apr 2021, Jani Nikula wrote:
> > On Thu, 29 Apr 2021, Lyude Paul wrote:
> >> JFYI Jani and Ben: I will be pushing this patch to drm-misc-next sometime
> >> today if there's no objections
> >
> > Thanks for the heads-up, I t
Am 03.05.21 um 22:43 schrieb Andrey Grodzovsky:
On 2021-04-29 3:08 a.m., Christian König wrote:
Am 28.04.21 um 17:11 schrieb Andrey Grodzovsky:
Handle all DMA IOMMU gropup related dependencies before the
group is removed.
v5: Drop IOMMU notifier and switch to lockless call to
ttm_tt_unpopul
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