Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs
v2: removed set functions for navi, renoir
v3: removed set function from arcturus
v4: added missing defines in drm_table and remove
uneeded goto label in navi10_ppt.c
Signed-off-by: David M Nieto
Reviewed-by: Lijo Lazar
Am 2021-05-17 um 10:39 a.m. schrieb Peng Ju Zhou:
> In SRIOV environment, KMD should access GC registers
> with RLCG if GC indirect access flag enabled.
>
> Signed-off-by: Peng Ju Zhou
This patch is
Reviewed-by: Felix Kuehling
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 42
Thanks. I will check and port this to powerplay code if necessary.
BR
Evan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Wednesday, May 19, 2021 10:13 AM
> To: Feng, Kenneth
> Cc: Deucher, Alexander ; Quan, Evan
> ; amd-gfx@lists.freedesktop.org
> Subject: Re:
On 2021-05-19 11:29 p.m., Felix Kuehling wrote:
Am 2021-05-19 um 11:20 p.m. schrieb Andrey Grodzovsky:
Use it to call disply code dependent on device->drv_data
before it's set to NULL on device unplug
v5:
Move HW finilization into this callback to prevent MMIO accesses
post cpi remove.
v7:
Match the order of definition to the structure's declaration to
help with locating included and missing functions of the API
Signed-off-by: Darren Powell
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 48 +++
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git
new powerplay enumeration pp_power_limit_level
modify hwmon show_power functions to use pp_power_limit_level
remove insertion of byte field into smu_get_power_level output arg "limit"
modify smu_get_power_level to use pp_power_limit_level
simplify logic of smu_get_power_level
* Test
=== Description ===
Modify smu_get_power_limit to implement Powerplay API
=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)
+ ISO(Ubuntu 20.04.1 LTS)
+ Kernel(5.11.0-custom-fdoagd5f)
=== Patch Summary ===
linux: (g...@gitlab.freedesktop.org:agd5f)
modify smu_get_power_limit to match Powerplay .get_power_limit signature
add smu_get_power_limit to swsmu_pm_funcs
simplify calling functions to use Powerplay API rather than direct call
* Test
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la
modify Powerplay API get_power_limit to use pp_power_limit_level
update Powerplay API get_power_limit calls to use pp_power_limit_level
modify pp_get_power_limit to use new Powerplay API
add new error return to pp_get_power_limit for unhandled pp_power_limit_level
* Test (non smu)
Test:
* Temporary insertion into Documentation/gpu/amdgpu.rst
START
Test Documentation
==
smu_get_power_limit
---
.. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
:identifiers: smu_get_power_limit
.. kernel-doc::
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou wrote:
>
> From: pengzhou
>
> In SRIOV environment, KMD should access GC registers
> with RLCG if GC indirect access flag enabled.
>
> Signed-off-by: pengzhou
Patches 1-8 are:
Reviewed-by: Alex Deucher
See my comments on patch 9.
Alex
> ---
>
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou wrote:
>
> KMD should not program these registers, the value were
> defined in the host, so skip them in the SRIOV environment.
>
> Signed-off-by: Peng Ju Zhou
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou wrote:
>
> use psp to program IH_RB_CNTL* if indirect access
> for ih enabled in SRIOV environment.
>
> Signed-off-by: Victor
> Signed-off-by: Peng Ju Zhou
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +--
>
I think this works for KFD userptr BOs. But this problem is probably not
specific to KFD. It's only most obvious with KFD because we rely so
heavily for userptrs.
I don't really understand why we're messing with TTM_PAGE_FLAG_SG in
amdgpu_ttm_tt_populate and amdgpu_ttm_tt_unpopulate. And why are
Signed-off-by: Jiawei Gu
---
src/app/CMakeLists.txt | 1 +
src/app/main.c | 8 +
src/app/vbios.c| 53 ++
src/lib/lowlevel/linux/query_drm.c | 11 +++
src/umr.h | 11 +++
Am 2021-05-19 um 11:20 p.m. schrieb Andrey Grodzovsky:
> Use it to call disply code dependent on device->drv_data
> before it's set to NULL on device unplug
>
> v5:
> Move HW finilization into this callback to prevent MMIO accesses
> post cpi remove.
>
> v7:
> Split kfd suspend from device exit to
On Wed, May 19, 2021 at 10:59 PM Jiawei Gu wrote:
>
> Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
>
> Provides a way for the user application to get the VBIOS
> information without having to parse the binary.
> It is useful for the user to be able to display in a simple way
Use it to call disply code dependent on device->drv_data
before it's set to NULL on device unplug
v5:
Move HW finilization into this callback to prevent MMIO accesses
post cpi remove.
v7:
Split kfd suspend from device exit to expdite HW related
stuff to amdgpu_pci_remove
v8:
Squash previous KFD
We have met memory corruption due to unexcepted swapout/swapin.
swapout function create one swap storage which is filled with zero. And
set ttm->page_flags as TTM_PAGE_FLAG_SWAPPED. But because userptr BO ttm
has no backend page at that time, no real data is swapout to swap
storage.
swapin
Hi Dave, Daniel,
New stuff for 5.14, same as last week, but with fixed up fixes tag.
The following changes since commit af8352f1ff54c4fecf84e36315fd1928809a580b:
Merge tag 'drm-msm-next-2021-04-11' of https://gitlab.freedesktop.org/drm/msm
into drm-next (2021-04-13 23:35:54 +0200)
are
Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info.
Provides a way for the user application to get the VBIOS
information without having to parse the binary.
It is useful for the user to be able to display in a simple way the VBIOS
version in their system if they happen to encounter an
[AMD Official Use Only]
I am not sure if we can create a ttm_bo_type_sg bo for userptr. But I have
another idea now. we can use flag AMDGPU_AMDKFD_CREATE_USERPTR_BO to create the
userptr bo.
发件人: Kuehling, Felix
发送时间: 2021年5月19日 23:11
收件人: Christian
[AMD Official Use Only]
swapout function create one swap storage which is filled with zero. And set
ttm->page_flags as TTM_PAGE_FLAG_SWAPPED. Just because ttm has no backend page
this time, no real data is swapout to this swap storage.
swapin function is called during populate as
Hi Dave, Daniel,
Fixes for 5.13.
The following changes since commit d07f6ca923ea0927a1024dfccafc5b53b61cfecc:
Linux 5.13-rc2 (2021-05-16 15:27:44 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.13-2021-05-19
for you to
[AMD Official Use Only - Internal Distribution Only]
Thanks Christian!
Happy to learn new tricks.
Best regards,
Jiawei
From: Christian König
Sent: Wednesday, May 19, 2021 9:23 PM
To: Deucher, Alexander ; Gu, JiaWei (Will)
; Nieto, David M ; Koenig, Christian
; amd-gfx@lists.freedesktop.org;
On 2021-05-19 4:59 p.m., Kazlauskas, Nicholas wrote:
On 2021-05-19 4:55 p.m., Aurabindo Pillai wrote:
[Why]
Conditions that end up modifying the global dc state must be locked.
However, during mst allocate payload sequence, lock is already taken.
With StarTech 1.2 DP hub, we get an HPD RX
On 2021-05-19 4:55 p.m., Aurabindo Pillai wrote:
[Why]
Conditions that end up modifying the global dc state must be locked.
However, during mst allocate payload sequence, lock is already taken.
With StarTech 1.2 DP hub, we get an HPD RX interrupt for a reason other
than to indicate down reply
[Why]
Conditions that end up modifying the global dc state must be locked.
However, during mst allocate payload sequence, lock is already taken.
With StarTech 1.2 DP hub, we get an HPD RX interrupt for a reason other
than to indicate down reply availability right after sending payload
allocation.
Reviewed-by: Aurabindo Pillai
On 2021-05-19 4:12 p.m., Nicholas Kazlauskas wrote:
[Why]
FS video support regressed GPU scaling and the scaled buffer ends up
stuck in the top left of the screen at native size - full, aspect,
center scaling modes do not function.
This is because
Treat it like ATIF and check both the dGPU and APU for
the method. This is required because ATCS may be hung
off of the APU in ACPI on A+A systems.
v2: add back accidently removed ACPI handle check.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 17 +---
[AMD Official Use Only]
Patch is
Reviewed-by: Boyuan Zhang
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: May 19, 2021 4:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
Subject: [PATCH] drm/amdgpu/vcn3: remove unused variable.
Not
Not used so remove it.
Fixes: a8ccb542539ff1 ("drm/amdgpu: stop touching sched.ready in the backend")
Signed-off-by: Alex Deucher
Cc: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Treat it like ATIF and check both the dGPU and APU for
the method. This is required because ATCS may be hung
off of the APU in ACPI on A+A systems.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 17 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 126
[Why]
FS video support regressed GPU scaling and the scaled buffer ends up
stuck in the top left of the screen at native size - full, aspect,
center scaling modes do not function.
This is because decide_crtc_timing_for_drm_display_mode() does not
get called when scaling is enabled.
[How]
Split
Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs
v2: removed set functions for navi, renoir
v3: removed set function from arcturus
Signed-off-by: David M Nieto
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 +++
Fill voltage fields in metrics table
v2: Removed dpm and freq ranges info
v3: Added check to ensure volrage offset is not zero
Signed-off-by: David M Nieto
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 82 +++
1 file changed, 65 insertions(+), 17
v2: removed static dpm and frequency ranges from table
expand metrics table with voltages and frequency ranges
Signed-off-by: David M Nieto
Reviewed-by: Lijo Lazar
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
Pushed out to drm-misc-next. Also fixed up Michel's name.
Alex
On Wed, May 19, 2021 at 11:56 AM Randy Dunlap wrote:
>
> On 5/19/21 1:15 AM, Mauro Carvalho Chehab wrote:
> > There are some places at drm that ended receiving a
> > REPLACEMENT CHARACTER U+fffd ('�'), probably because of
> > some
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
Add cancel_delayed_work_sync before set power gating state
to avoid race condition issue when power gating.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
[AMD Official Use Only]
For the case of virtualization, for example, the serial number has no relation
to the uuid. Which means that at least for virtualization the node needs to be
created. This may also be the case on other gpus.
From: Christian König
Sent:
On 5/19/21 1:15 AM, Mauro Carvalho Chehab wrote:
> There are some places at drm that ended receiving a
> REPLACEMENT CHARACTER U+fffd ('�'), probably because of
> some bad charset conversion.
>
> Fix them by using what it seems to be the proper
> character.
>
> Signed-off-by: Mauro
Am 2021-05-19 um 5:02 a.m. schrieb Chengzhe Liu:
> In sriov, cwsr is not stable
NAK. Without CWSR, ROCm is not stable. Any compute application with long
running waves can cause a hang.
Regards,
Felix
>
> Signed-off-by: Chengzhe Liu
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 24
Avoid changes to sienna_cichlid_force_clk_levels as well.
With that addressed patch is
Reviewed-by: Lijo Lazar
On 5/19/2021 11:32 AM, David M Nieto wrote:
Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs
Signed-off-by: David M Nieto
---
Add a check of non-zero offsets so that it doesn't show a static voltage
of 1.55v all the time. With that addressed the patch is
Reviewed-by: Lijo Lazar
On 5/19/2021 11:32 AM, David M Nieto wrote:
Fill voltage fields in metrics table
Signed-off-by: David M Nieto
---
Reviewed-by: Lijo Lazar
On 5/19/2021 11:32 AM, David M Nieto wrote:
expand metrics table with voltages and frequency ranges
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
2
Am 2021-05-19 um 6:04 a.m. schrieb Christian König:
> Am 19.05.21 um 07:45 schrieb Felix Kuehling:
>> SG BOs such as dmabuf imports and userptr BOs do not consume system
>> resources directly. Instead they point to resources owned elsewhere.
>> They typically get evicted by DMABuf move notifiers
Looks like we're creating the userptr BO as ttm_bo_type_device. I guess
we should be using ttm_bo_type_sg? BTW, amdgpu_gem_userptr_ioctl also
uses ttm_bo_type_device.
Regards,
Felix
Am 2021-05-19 um 6:01 a.m. schrieb Christian König:
> I'm scratching my head how that is even possible.
>
> See
Hi Horace,
that is correct, but also completely irrelevant.
What we do here is to wait for the TLB flush to avoid starting
operations with invalid cache data.
But a parallel FLR clears the cache anyway and also prevents any new
operation from starting, so it is perfectly valid to timeout
[AMD Official Use Only]
Hi Christian,
I think the problem is that a non-FLRed VF will not know that another VF got an
FLR, unless host triggered a whole GPU reset.
So in the worst situation, for example the VF0 to VF10 are all hang and will be
FLRed one by one, the VF11 will not know that
[AMD Official Use Only - Internal Distribution Only]
Ping on this series.
--
BW
Pengju Zhou
> -Original Message-
> From: amd-gfx On Behalf Of Zhou,
> Peng Ju
> Sent: Monday, May 17, 2021 10:50 PM
> To: Alex Deucher
Am 19.05.21 um 16:14 schrieb Andrey Grodzovsky:
Wait for all dependencies of a job to complete before
killing it to avoid data corruptions.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 5 +
1 file changed, 5
Wait for all dependencies of a job to complete before
killing it to avoid data corruptions.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/scheduler/sched_entity.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c
On Wed, May 19, 2021 at 4:48 AM Michel Dänzer wrote:
>
> On 2021-05-19 12:05 a.m., Alex Deucher wrote:
> > On Tue, May 18, 2021 at 10:11 AM Michel Dänzer wrote:
> >>
> >> On 2021-05-17 11:33 a.m., xgqt wrote:
> >>> Hello!
> >>>
> >>> I run a AMD laptop "81NC Lenovo IdeaPad S340-15API" - AMD
On Wed, May 19, 2021 at 12:34:05PM +0300, Pekka Paalanen wrote:
> On Wed, 12 May 2021 16:04:16 +0300
> Ville Syrjälä wrote:
>
> > On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
> > > Hello,
> > >
> > > In addition to the existing "max bpc", and "Broadcast RGB/output_csc" drm
>
Good point.
If you want to double check the alignment you can use something like
"pahole drivers/gpu/drm/amd/amdgpu/amdgpu.ko -C drm_amdgpu_info_vbios"
after building the kernel module.
Regards,
Christian.
Am 19.05.21 um 15:09 schrieb Deucher, Alexander:
[Public]
The structure is not 64
[Public]
The structure is not 64 bit aligned. I think you want something like:
> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u32 pad;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> +};
Am 19.05.21 um 13:51 schrieb Andrey Grodzovsky:
On 2021-05-19 7:46 a.m., Christian König wrote:
Am 19.05.21 um 13:03 schrieb Andrey Grodzovsky:
On 2021-05-19 6:57 a.m., Christian König wrote:
Am 18.05.21 um 20:48 schrieb Andrey Grodzovsky:
[SNIP]
Would this be the right way to do it ?
On 2021-05-19 7:46 a.m., Christian König wrote:
Am 19.05.21 um 13:03 schrieb Andrey Grodzovsky:
On 2021-05-19 6:57 a.m., Christian König wrote:
Am 18.05.21 um 20:48 schrieb Andrey Grodzovsky:
[SNIP]
Would this be the right way to do it ?
Yes, it is at least a start. Question is if we
Yeah, but you can't do that it will probably trigger the watchdog timer.
The usec_timeout is named this way because it is a usec timeout.
Anything large than 1ms is a no-go here.
When the other instances do a FLR we don't really need to wait for the
TLB flush anyway since any FLR will kill
Am 19.05.21 um 13:03 schrieb Andrey Grodzovsky:
On 2021-05-19 6:57 a.m., Christian König wrote:
Am 18.05.21 um 20:48 schrieb Andrey Grodzovsky:
[SNIP]
Would this be the right way to do it ?
Yes, it is at least a start. Question is if we can wait blocking
here or not.
We install a
On 2021-05-17 6:55 a.m., Christian König wrote:
Am 17.05.21 um 12:52 schrieb Lang Yu:
When amdgpu_ib_ring_tests failed, the reset logic called
amdgpu_device_ip_suspend twice, then deadlock occurred.
Deadlock log:
[ 805.655192] amdgpu :04:00.0: amdgpu: ib ring test failed (-110).
[
On 5/14/21 4:13 PM, Alex Deucher wrote:
On Fri, May 14, 2021 at 4:20 AM wrote:
From: changzhu
From: Changfeng
There is problem with 3DCGCG firmware and it will cause compute test
hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid
compute hang.
Change-Id:
On 5/19/21 5:14 AM, Huang, Ray wrote:
[Public]
I check the patch (below) to disable compute queues for raven is not
landed into drm-next. So actually all queues are enabled at this
moment. Nirmoy, can we get your confirmation?
I indeed didn't push the commit that disable all but one cu
[AMD Official Use Only]
We support 12 VF at most. In worst case, the first 11 all IDLE fail and do FLR,
it will need 11 * 500ms to switch to the 12nd VF,
so I set 12 * 500ms for the timeout.
-Original Message-
From: Christian König
Sent: Wednesday, May 19, 2021 6:08 PM
To: Liu, Cheng
On 2021-05-19 6:57 a.m., Christian König wrote:
Am 18.05.21 um 20:48 schrieb Andrey Grodzovsky:
[SNIP]
Would this be the right way to do it ?
Yes, it is at least a start. Question is if we can wait blocking here
or not.
We install a callback a bit lower to avoid blocking, so I'm pretty
Well I don't think generating an UUID in the kernel makes sense in general.
What we can do is to expose the serial number of the device, so that
userspace can create an UUID if necessary.
Christian.
Am 18.05.21 um 22:37 schrieb Nieto, David M:
[AMD Official Use Only]
I think the sysfs
Am 18.05.21 um 20:48 schrieb Andrey Grodzovsky:
[SNIP]
Would this be the right way to do it ?
Yes, it is at least a start. Question is if we can wait blocking here
or not.
We install a callback a bit lower to avoid blocking, so I'm pretty
sure that won't work as expected.
Christian.
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Tuesday, May 18, 2021 10:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Wang, Kevin(Yang) ; Liu, Aaron
Subject: [PATCH] drm/amdgpu: modify system reference clock
Am 19.05.21 um 11:32 schrieb Chengzhe Liu:
When there is 12 VF, we need to increase the timeout
NAK, 6 seconds is way to long to wait polling on a fence.
Why should an invalidation take that long? The engine are per VF just to
avoid exactly that problem.
Christian.
Signed-off-by:
Am 19.05.21 um 07:45 schrieb Felix Kuehling:
SG BOs such as dmabuf imports and userptr BOs do not consume system
resources directly. Instead they point to resources owned elsewhere.
They typically get evicted by DMABuf move notifiers of MMU notifiers.
If those notifiers don't need to wait for
On Wed, 19 May 2021 11:53:37 +0300
Pekka Paalanen wrote:
...
> TL;DR:
>
> I would summarise my comments so far into these:
>
> - Telling the kernel the color spaces and letting it come up with
> whatever color transformation formula from those is not enough,
> because it puts the render
I'm scratching my head how that is even possible.
See when a BO is created in the system domain it is just an empty hull,
e.g. without backing store and allocated pages.
So the swapout function will just ignore it.
Christian.
Am 19.05.21 um 07:07 schrieb Pan, Xinhui:
[AMD Official Use
On Wed, 12 May 2021 16:04:16 +0300
Ville Syrjälä wrote:
> On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
> > Hello,
> >
> > In addition to the existing "max bpc", and "Broadcast RGB/output_csc" drm
> > properties I propose 4 new properties:
> > "preferred pixel encoding",
When there is 12 VF, we need to increase the timeout
Signed-off-by: Chengzhe Liu
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
In sriov, cwsr is not stable
Signed-off-by: Chengzhe Liu
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index
On Tue, 18 May 2021 10:19:25 -0400
Harry Wentland wrote:
> On 2021-05-18 3:56 a.m., Pekka Paalanen wrote:
> > On Mon, 17 May 2021 15:39:03 -0400
> > Vitaly Prosyak wrote:
> >
> >> On 2021-05-17 12:48 p.m., Sebastian Wick wrote:
...
> >>> I suspect that this is not about tone mapping at
On 2021-05-19 12:05 a.m., Alex Deucher wrote:
> On Tue, May 18, 2021 at 10:11 AM Michel Dänzer wrote:
>>
>> On 2021-05-17 11:33 a.m., xgqt wrote:
>>> Hello!
>>>
>>> I run a AMD laptop "81NC Lenovo IdeaPad S340-15API" - AMD Ryzen 5 3500U
>>> with Radeon Vega 8 Graphics.
>>> Recently some
There are some places at drm that ended receiving a
REPLACEMENT CHARACTER U+fffd ('�'), probably because of
some bad charset conversion.
Fix them by using what it seems to be the proper
character.
Signed-off-by: Mauro Carvalho Chehab
---
drivers/gpu/drm/amd/include/atombios.h | 10
On Tue, 18 May 2021 10:32:48 -0400
Harry Wentland wrote:
> On 2021-05-17 4:34 a.m., Pekka Paalanen wrote:
> > On Fri, 14 May 2021 17:04:51 -0400
> > Harry Wentland wrote:
> >
> >> On 2021-04-30 8:53 p.m., Sebastian Wick wrote:
> >>> On 2021-04-26 20:56, Harry Wentland wrote:
> >
> >
Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 46 +++
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 8
Fill voltage fields in metrics table
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 58 +--
1 file changed, 41 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
expand metrics table with voltages and frequency ranges
Signed-off-by: David M Nieto
---
.../gpu/drm/amd/include/kgd_pp_interface.h| 69 +++
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 +
2 files changed, 72 insertions(+)
diff --git
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