[AMD Official Use Only - Internal Distribution Only]
Tested-by: Sathishkumar S
Reviewed-by: Sathishkumar S
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, May 26, 2021 8:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2]
Am 26.05.21 um 02:40 schrieb Luben Tuikov:
On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.
v2: Cancel pending delayed work at ras_fini().
Cc:
since vcn decoding ring is not required, so just disable it.
Cc: Alex.Deucher
Cc: Christian.Konig
Signed-off-by: Li.Xin.Justin
Signed-off-by: Frank.Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 25 ++---
2 files
Remove unused code related to shadow BO.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 29 --
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ---
2 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are shadowed,
so switch to shadow pointer of amdgpu_bo_vm.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 27 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 ++--
2 files
Shadow BOs are only needed by VM code so create it
directly within the vm code.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Add new BO subclass that will be used by amdgpu vm code.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 32 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 10 +++
2 files changed, 42 insertions(+)
diff --git
Allocate PD/PT entries while allocating VM BOs and use that
instead of allocating those entries separately.
v2: create a new var for num entries.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++---
1 file changed, 20 insertions(+), 14
Do the shadow bo validation in the VM code as
VM code knows/owns shadow BOs.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 23 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git
Use amdgpu_bo_vm subclass for creating BOs related to PD/PT.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 43 ++
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: John Clements
-Original Message-
From: Joshi, Mukul
Sent: Wednesday, May 26, 2021 4:20 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Clements, John
; Li, Dennis ; Joshi, Mukul
Subject: [PATCH] drm/amdgpu:
[AMD Official Use Only]
Reviewed-by: Tao Zhou mailto:tao.zh...@amd.com>>
From: Chengming Gui
Sent: Wednesday, May 26, 2021 3:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gui, Jack ; Zhou1, Tao ; Chen,
Jiansong (Simon) ; Zhang, Hawking
Subject: [PATCH]
Hi Robin,
Am 25.05.21 um 22:09 schrieb Robin Murphy:
On 2021-05-25 14:05, Alex Deucher wrote:
On Tue, May 25, 2021 at 8:56 AM Peter Geis wrote:
On Tue, May 25, 2021 at 8:47 AM Alex Deucher
wrote:
On Tue, May 25, 2021 at 8:42 AM Peter Geis
wrote:
Good Evening,
I am stress testing
[AMD Official Use Only]
Reviewed-by: Nirmoy Das
-Original Message-
From: Zhang, Morris
Sent: Wednesday, May 26, 2021 5:11 AM
To: amd-gfx@lists.freedesktop.org; Das, Nirmoy
Subject: [PATCH v2] drm/amdgpu: fix metadata_size for ubo ioctl queries
Although the
This patch is to retain the fine grain tuning parameters after resume for
legacy APU, it will cover Raven/Raven2/Picasso.
Signed-off-by: Xiaojian Du
---
.../amd/pm/powerplay/hwmgr/hardwaremanager.c | 3 ++-
.../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 21 +++
2 files
Hi Monk,
New patch submitted according to your suggestion
Best Regards,
JingWen Chen
-Original Message-
From: Liu, Monk
Sent: Wednesday, May 26, 2021 3:24 PM
To: Chen, JingWen ; amd-gfx@lists.freedesktop.org
Cc: Zhao, Victor ; Chen, JingWen
Subject: RE: [PATCH] drm/amd/amdgpu:save
From: Victor Zhao
[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.
[How]
Use a psp wptr cache machanism to aovid the change made by attack.
v2: unify change and add detailed reason
Change-Id:
[AMD Official Use Only]
>>+ ring->ring_wptr = psp_write_ptr_reg;
Put the cache mechanism into the callbacks please
>>+ ring->ring_wptr = 0;
It is not needed
At last, try to put more details in the comment to let people know why we need
this PSP WPTR cache mechanism
Thanks
[AMD Official Use Only]
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Jingwen
>Chen
>Sent: Wednesday, May 26, 2021 2:55 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Chen, JingWen ; Zhao, Victor
>; Liu, Monk
>Subject: [PATCH] drm/amd/amdgpu:save psp ring wptr in
[Public]
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, May 26, 2021 8:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/acpi: make ATPX/ATCS structures global
They are global ACPI methods, so maybe the
From: Victor Zhao
save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
MP0_SMN_C2PMSG_102 reg
Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
Signed-off-by: Victor Zhao
Signed-off-by: Jingwen Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
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