Do we need to consider backward compatibility?
Best wishes
Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Liu,
>Shaoyun
>Sent: Thursday, June 3, 2021 11:10 PM
>To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
>Cc: Luo, Zhigang
>Subject: RE: [PATCH 1/5] drm/amdgpu: remove
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning
by explicitly adding a break statement instead of letting the code fall
through to the next case.
Link: https://github.com/KSPP/linux/issues/115
Signed-off-by: Gustavo A. R. Silva
---
JFYI: We had thousands of these sorts
Also fix some coding issue reported from sparse.
Signed-off-by: Chen Li
---
drivers/gpu/drm/radeon/radeon_uvd.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
b/drivers/gpu/drm/radeon/radeon_uvd.c
index
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix this problem.
BTW, amdgpu has already
On Thu, Jun 3, 2021 at 9:37 PM Dave Airlie wrote:
>
> On Fri, 4 Jun 2021 at 07:20, Alex Deucher wrote:
> >
> > Please open a gitlab MR for these.
> >
>
> I'd really prefer these tests all get migrated out of here into igt. I
> don't think libdrm_amdgpu really should have tests that test the
>
Code review happens on gitlab now for libdrm.
Alex
On Thu, Jun 3, 2021 at 6:02 PM Grodzovsky, Andrey
wrote:
>
> Is libdrm on gitlab ? I wasn't aware of this. I assumed code reviews still go
> through dri-devel.
>
> Andrey
>
>
> From: Alex Deucher
> Sent: 03
Is libdrm on gitlab ? I wasn't aware of this. I assumed code reviews still go
through dri-devel.
Andrey
From: Alex Deucher
Sent: 03 June 2021 17:20
To: Grodzovsky, Andrey
Cc: Maling list - DRI developers ; amd-gfx
list ; Deucher, Alexander
; Christian König
On Fri, 4 Jun 2021 at 07:20, Alex Deucher wrote:
>
> Please open a gitlab MR for these.
>
I'd really prefer these tests all get migrated out of here into igt. I
don't think libdrm_amdgpu really should have tests that test the
kernel level infrastructure.
I know some people at AMD had issues in
On Thu, May 27, 2021 at 03:54:27PM -0400, Joshi, Mukul wrote:
...
> > Is that the same deferred interrupt which calls
> > amd_deferred_error_interrupt() ?
>
> Sorry picking this up after sometime. I thought I had replied to this email.
> Yes it is the same deferred interrupt which calls
>
Please open a gitlab MR for these.
Alex
On Tue, Jun 1, 2021 at 4:17 PM Andrey Grodzovsky
wrote:
>
> Adding some tests to acompany the recently added hot-unplug
> feature. For now the test suite is disabled until the feature
> propagates from drm-misc-next to drm-next.
>
> Andrey Grodzovsky (7):
On Thu, Jun 3, 2021 at 5:11 PM Daniel Vetter wrote:
>
> On Thu, Jun 03, 2021 at 10:22:37AM -0400, Andrey Grodzovsky wrote:
> > Ping
> >
> > Andrey
> >
> > On 2021-06-02 10:20 a.m., Andrey Grodzovsky wrote:
> > >
> > > On 2021-06-02 3:59 a.m., Daniel Vetter wrote:
> > > > On Tue, Jun 1, 2021 at
On Thu, Jun 03, 2021 at 10:22:37AM -0400, Andrey Grodzovsky wrote:
> Ping
>
> Andrey
>
> On 2021-06-02 10:20 a.m., Andrey Grodzovsky wrote:
> >
> > On 2021-06-02 3:59 a.m., Daniel Vetter wrote:
> > > On Tue, Jun 1, 2021 at 10:17 PM Andrey Grodzovsky
> > > wrote:
> > > > Adding some tests to
[AMD Official Use Only]
I will leave Hawking to comment on this serial .
Thanks
Shaoyun.liu
-Original Message-
From: Luo, Zhigang
Sent: Thursday, June 3, 2021 11:48 AM
To: Liu, Shaoyun ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 5/5] drm/amdgpu: allocate psp fw private
All new PSP release will have this feature. And it will not cause any failure
even the PSP doesn't have this feature yet.
Thanks,
Zhigang
-Original Message-
From: Liu, Shaoyun
Sent: June 3, 2021 11:15 AM
To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: RE:
Yeah, it will also init psp sos and asd mircrocode. But I think it's harmless.
Thanks,
Zhigang
-Original Message-
From: Liu, Shaoyun
Sent: June 3, 2021 11:13 AM
To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode
Applied. Thanks!
Alex
On Wed, Jun 2, 2021 at 4:58 PM Harry Wentland wrote:
>
> On 2021-06-02 4:45 p.m., Mario Kleiner wrote:
> > Testing on AMD Carizzo with DCE-11.0 display engine showed that
> > it doesn't like a 36 bpp linebuffer very much. The display just
> > showed a solid green.
> >
> >
Yes, I double checked all gfx9 ASICs with sriov supported.
-Original Message-
From: Liu, Shaoyun
Sent: June 3, 2021 11:11 AM
To: Luo, Zhigang ; amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: RE: [PATCH 2/5] drm/amdgpu: remove sriov vf gfxhub fb location
programming
[AMD
Am 2021-06-03 um 8:34 a.m. schrieb Colin King:
> From: Colin Ian King
>
> The variable k is being assigned a value that is never read, the
> assignment is redundant and can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King
Reviewed-by: Felix Kuehling
I'm
On Thu, Jun 3, 2021 at 3:35 AM Chen Li wrote:
>
>
> I met a gpu addr bug recently and the kernel log
> tells me the pc is memcpy/memset and link register is
> radeon_uvd_resume.
>
> As we know, in some architectures, optimized memcpy/memset
> may not work well on device memory. Trival
Defines smu_cmn_get_indep_throttler_status which performs ASIC
independent translation given a corresponding lookup table.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 +
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4
2 files changed, 17
Perform dependent to independent throttle status translation
for navi1x.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
Perform dependent to independent throttle status translation
for renoir.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Seperated
into four 16-bit types: power throttlers, current throttlers,
temperature, other.
Signed-off-by:
Perform dependent to independent throttle status translation
for arcturus.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ---
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
Perform dependent to independent throttle status translation
for sienna cichlid.
Signed-off-by: Graham Sider
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 ---
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git
Perform dependent to independent throttle status translation
for aldebaran.
Signed-off-by: Graham Sider
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 27 +++
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
Perform dependent to independent throttle status translation
for vangogh.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
This patch set adds support for a new ASIC independant u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to
v2_2) to add field.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/include/kgd_pp_interface.h|
Applied. Thanks!
Alex
On Thu, Jun 3, 2021 at 8:42 AM Colin King wrote:
>
> From: Colin Ian King
>
> The variable active_disp is being initialized with a value that
> is never read, it is being re-assigned immediately afterwards.
> Clean up the code by removing the need for variable
[AMD Official Use Only]
This one doesn't looks apply to XGMI TA only , it's for whole PSP init , can
you double check it ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo,
[AMD Official Use Only]
Looks ok to me .
-Original Message-
From: amd-gfx On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: [PATCH 3/5] drm/amdgpu: remove sriov vf mmhub system aperture and fb
location
[AMD Official Use Only]
This looks will affect other ASIC , Can you double check that ?
-Original Message-
From: amd-gfx On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: [PATCH 2/5] drm/amdgpu: remove sriov vf
[AMD Official Use Only]
Looks ok to me .
Reviewed-By : Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Zhigang Luo
Sent: Thursday, June 3, 2021 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Luo, Zhigang
Subject: [PATCH 1/5] drm/amdgpu: remove sriov vf checking from
Ping
Andrey
On 2021-06-02 10:20 a.m., Andrey Grodzovsky wrote:
On 2021-06-02 3:59 a.m., Daniel Vetter wrote:
On Tue, Jun 1, 2021 at 10:17 PM Andrey Grodzovsky
wrote:
Adding some tests to acompany the recently added hot-unplug
feature. For now the test suite is disabled until the feature
host driver programmed mmhub system aperture and fb location for vf, no
need to program in guest side.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 17 +++--
1 file changed, 3 insertions(+), 14 deletions(-)
diff --git
host driver programmed fb location registers for vf, no need to
check anymore.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
psp added new feature to check fw buffer address for sriov vf. the
address range must be in vf fb.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git
need to load xgmi ta for arcturus and aldebaran sriov vf.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index
host driver programmed the gfxhub fb location for vf, no need to
program in guest side.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
[AMD Official Use Only]
VR_*0/1 reflect the throttle status of separate voltage rails - availability of
both depends on board and FW capability to query their temperature.
Thanks,
Lijo
-Original Message-
From: Sider, Graham
Sent: Thursday, June 3, 2021 6:41 PM
To: Quan, Evan ;
Use vma_lookup() to find the VMA at a specific address. As vma_lookup()
will return NULL if the address is not within any VMA, the start address
no longer needs to be validated.
Signed-off-by: Liam R. Howlett
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
1 file changed, 2
Some ASICs use a single VR_MEM bit, whereas others split it into VR_MEM0 and
VR_MEM1. To avoid confusion, we've combined the VR_MEM0 and VR_MEM1 bits on
those ASICs. For consistency we did the same with LIQUID0 and LIQUID1.
-Original Message-
From: Quan, Evan
Sent: Wednesday, June 2,
On 6/3/2021 10:26 AM, Evan Quan wrote:
On driver loading, the ASIC is in D0 state. The bundled
audio function should be in the same state also.
Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++
1
On 6/3/2021 10:26 AM, Evan Quan wrote:
For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be cleared to pair that.
Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
Signed-off-by: Evan
The original code returns IP version of instantce_0 for every IP. This
implementation may be correct for most of IPs.
However, for certain IP block (VCN for example), it may have 2 instances and
both of them have the same hw_id, BUT they have different revision number (0
and 1).
In this case,
From: Bokun Zhang
In the past, we use MMSCH to determine whether a VCN is enabled or not.
This is not reliable since after a FLR, MMSCH may report junk data.
It is better to use IP discovery data.
Signed-off-by: Bokun Zhang
Signed-off-by: Peng Ju Zhou
---
On Thu, 03 Jun 2021, Daniel Vetter wrote:
> On Wed, Jun 02, 2021 at 03:32:34PM +0100, Lee Jones wrote:
> > Some off these patches have been knocking around for a while.
> >
> > Who will hoover them up please?
> >
> > This set is part of a larger effort attempting to clean-up W=1
> > kernel
From: Colin Ian King
The variable active_disp is being initialized with a value that
is never read, it is being re-assigned immediately afterwards.
Clean up the code by removing the need for variable active_disp.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
From: Colin Ian King
The variable k is being assigned a value that is never read, the
assignment is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
1 file changed, 1 insertion(+), 1
On Wed, Jun 02, 2021 at 03:32:34PM +0100, Lee Jones wrote:
> Some off these patches have been knocking around for a while.
>
> Who will hoover them up please?
>
> This set is part of a larger effort attempting to clean-up W=1
> kernel builds, which are currently overwhelmingly riddled with
>
On Wed, Jun 02, 2021 at 12:47:40PM -0400, Alex Deucher wrote:
> This patch set adds initial support for Yellow Carp, a new
> GPU from AMD.
Always happy to see the new GPU support. :-)
Series are Acked-by: Huang Rui
>
> I did not send out patch 1 due to its size (new register headers),
> but
For BACO scenario, PMFW will handle the dpm features disablement
and interaction with RLC properly. Driver involvement is unnecessary
and error prone.
Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
1 file
As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to
be incomplete. Another fix(see link below) has been sent out.
Link:
https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.q...@amd.com/
Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088
Signed-off-by: Evan Quan
---
Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the
Dstate change. Driver involvement for determining the timing for
BACO enter/exit is not needed.
Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
On driver loading, the ASIC is in D0 state. The bundled
audio function should be in the same state also.
Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++
1 file changed, 14 insertions(+)
diff --git
For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be cleared to pair that.
Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
Signed-off-by: Evan Quan
---
[Public]
I guess, you are suggesting to have levels to indicate limits/average and
types/class to indicate different levels. I'm fine with that.
enum pp_power_level
{
PP_PWR_LIMIT_MIN = -1,
PP_PWR_LIMIT_CURRENT,
PP_PWR_LIMIT_DEFAULT,
Hi Dave, Daniel,
Fixes for 5.13.
The following changes since commit 8124c8a6b35386f73523d27eacb71b5364a68c4c:
Linux 5.13-rc4 (2021-05-30 11:58:25 -1000)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.13-2021-06-02
for you to
On 2021-06-02 6:21 p.m., Alex Deucher wrote:
> Applied. Thanks!
Thank you. Note that this is needed for 5.13.
--
Earthling Michel Dänzer | https://redhat.com
Libre software enthusiast | Mesa and X developer
I met a gpu addr bug recently and the kernel log
tells me the pc is memcpy/memset and link register is
radeon_uvd_resume.
As we know, in some architectures, optimized memcpy/memset
may not work well on device memory. Trival memcpy_toio/memset_io
can fix this problem.
BTW, amdgpu has already
[Public]
I think both of those candidates have drawbacks
** option #1 has a clash with the limit_level
eg.
enum pp_power_limit_level limit_level;
enum pp_power_limit power_limit;
power_limit = PP_PWR_LIMIT_DEFAULT; // name clash
** option #2 doesn't describe the usage, and might as well
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