[PATCH] drm/amdgpu: Set ttm caching flags during bo allocation

The ttm caching flags (ttm_cached, ttm_write_combined etc) are used to determine a buffer object's mapping attributes in both CPU page table and GPU page table (when that buffer is also accessed by GPU). Currently the ttm caching flags are set in function amdgpu_ttm_io_mem_reserve which is called

RE: [PATCH 3/4] drm/amdkfd: report pcie bandwidth as number of lanes

[AMD Official Use Only] Ping on series. Note Patch 4 can be dropped. Runtime doesn't require an extra flag to determine direct connections. Thanks, Jon > -Original Message- > From: Kim, Jonathan > Sent: Monday, June 21, 2021 3:24 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhang,

[PATCH 1/3] drm/amd/pm: Simplify managed I2C transfer of Aldebaran

Simplify Aldebaran managed I2C transfer function to correctly play with the upper I2C layers. This gets it in line with Navi10, Acturus, and Sienna Cichlid. Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: John Clements Cc: Hawking Zhang Signed-off-by: Luben Tuikov

[PATCH 2/3] drm/amd/pm: Fix I2C controller port setting of Arcturus

Fix controller port setting of Arcturus from 1 (incorrect) to 0 (correct). This fixes a previous rework commit which introduced this typo. Cc: Alexander Deucher Signed-off-by: Luben Tuikov Fixes: 10e547e01291e1 ("drm/amdgpu/pm: rework i2c xfers on arcturus (v4)") Reviewed-by: Alexander Deucher

[PATCH 3/3] drm/amd/pm: Fix I2C controller port setting of Navi10

Fix controller port setting of Navi10 from 1 (incorrect) to 0 (correct). This fixes a previous rework commit which introduced this typo. Cc: Alexander Deucher Signed-off-by: Luben Tuikov Fixes: f3be7dda30f4b0 ("drm/amdgpu/pm: add smu i2c implementation for navi1x (v4)") Reviewed-by: Alexander

Re: [PATCH 3/3] drm/amd/pm: Fix I2C controller port setting of Navi10

On 2021-06-28 1:36 p.m., Alex Deucher wrote: > On Mon, Jun 28, 2021 at 1:26 PM Luben Tuikov wrote: >> Fix controller port setting of Navi10 from 1 >> (incorrect) to 0 (correct). >> >> This fixes a previous rework commit which >> introduced this typo. >> >> Cc: Alexander Deucher >> Signed-off-by:

[PATCH 2/3] drm/amd/pm: Fix I2C controller port setting of Arcturus

Fix controller port setting of Arcturus from 1 (incorrect) to 0 (correct). This fixes a previous rework commit which introduced this typo. Cc: Alexander Deucher Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 3/3] drm/amd/pm: Fix I2C controller port setting of Navi10

Fix controller port setting of Navi10 from 1 (incorrect) to 0 (correct). This fixes a previous rework commit which introduced this typo. Cc: Alexander Deucher Signed-off-by: Luben Tuikov --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH 1/3] drm/amd/pm: Simplify managed I2C transfer of Aldebaran

Simplify Aldebaran managed I2C transfer function to correctly play with the upper I2C layers. This gets it in line with Navi10, Acturus, and Sienna Cichlid. Cc: Alexander Deucher Cc: Andrey Grodzovsky Cc: Lijo Lazar Cc: John Clements Cc: Hawking Zhang Signed-off-by: Luben Tuikov ---

Re: AMDGPU error: "[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out!"

[Public] Thanks for narrowing this down. There is new PCO SDMA firmware available (attached). Can you try it? Thanks, Alex From: amd-gfx on behalf of Michel Dänzer Sent: Thursday, June 24, 2021 6:51 AM To: Alex Deucher Cc: xgqt ; amd-gfx list Subject:

Re: [PATCH v3 2/8] mm: remove extra ZONE_DEVICE struct page refcount

Am 2021-06-17 um 3:16 p.m. schrieb Ralph Campbell: > > On 6/17/21 8:16 AM, Alex Sierra wrote: >> From: Ralph Campbell >> >> ZONE_DEVICE struct pages have an extra reference count that >> complicates the >> code for put_page() and several places in the kernel that need to >> check the >>

Re: [PATCH v3] drm/radeon: Call radeon_suspend_kms() in radeon_pci_shutdown() for Loongson64

[Public] Applied. Thanks. For whatever reason, I never got this patch and couldn't find it in patchwork. Alex From: Koenig, Christian Sent: Wednesday, June 23, 2021 4:25 AM To: Tiezhu Yang ; Deucher, Alexander Cc: airl...@linux.ie ;

Re: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

[AMD Official Use Only] Hi Chris, amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, unsigned long offset, void *buf, int len, int write) the above function will be called from kernel side (likes 'get_user_pages' code path), and the function should accept non-aligned addresses. without

Re: [PATCH 2/2] drm/amd/display: fix null pointer access in gpu reset

On 2021-06-28 5:27 a.m., Guchun Chen wrote: > During GPU reset, when receiving a DMCUB OUTBUX0 interrupt, > DAL code will set it to be OUTBOX interrupt and sets hw interrupt. > However, OUTBOX interrupt is not registered yet, so a NULL pointer > access will be executed. > > Call Trace: >

Re: [PATCH 3/3] drm/amd/pm: Fix I2C controller port setting of Navi10

On Mon, Jun 28, 2021 at 1:26 PM Luben Tuikov wrote: > > Fix controller port setting of Navi10 from 1 > (incorrect) to 0 (correct). > > This fixes a previous rework commit which > introduced this typo. > > Cc: Alexander Deucher > Signed-off-by: Luben Tuikov For patches 2 and 3, please add a

Re: [PATCH v4 03/17] drm/uAPI: Add "active bpc" as feedback channel for "max bpc" drm property

Am 18.06.21 um 11:11 schrieb Werner Sembach: > Add a new general drm property "active bpc" which can be used by graphic > drivers to report the applied bit depth per pixel back to userspace. > > While "max bpc" can be used to change the color depth, there was no way to > check which one actually

Re: [PATCH] drm/amdgpu/dc: Really fix DCN3.1 Makefile for PPC64

Applied. Thanks! Alex On Fri, Jun 25, 2021 at 4:14 PM Harry Wentland wrote: > > On 2021-06-23 6:30 a.m., Michal Suchanek wrote: > > Also copy over the part that makes old gcc handling cross-platform. > > > > Fixes: df7a1658f257 ("drm/amdgpu/dc: fix DCN3.1 Makefile for PPC64") > > Fixes:

Re: [PATCH] drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)

On Sun, Jun 27, 2021 at 10:55 PM Aaron Liu wrote: > > Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1 > by default for all asic. On Raven/Renoir, the sdma goldsetting > changes SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0. > This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1. > >

Re: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

Hi Kevin, the primary use of amdgpu_device_vram_access() is to gate direct kernel access to VRAM using the MM_INDEX/MM_DATA registers or aperture. It should by design never deal with data sizes != 4 bytes. The amdgpu_ttm_access_memory() is for debug access to the backing store of BOs and

Re: [PATCH 1/2] drm/amdgpu: return early for preempt type BOs

Am 25.06.21 um 19:28 schrieb Nirmoy Das: Return early for AMDGPU_PL_PREEMPT BOs so that we don't pass wrong pointer to amdgpu_gtt_mgr_has_gart_addr() which assumes ttm_resource argument to be TTM_PL_TT type BO's. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5

Re: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

Am 25.06.21 um 05:24 schrieb Kevin Wang: 1. add non-aligned address support in amdgpu_device_vram_access() 2. reduce duplicate code in amdgpu_ttm_access_memory() because the MM_INDEX{HI}/DATA are protected register, it is not working in sriov environment when mmio protect feature is enabled (in

RE: [PATCH 2/2] drm/amd/display: fix null pointer access in gpu reset

[AMD Official Use Only] Series is reviewed-and-tested-by: Evan Quan > -Original Message- > From: amd-gfx On Behalf Of > Guchun Chen > Sent: Monday, June 28, 2021 5:28 PM > To: amd-gfx@lists.freedesktop.org; Siqueira, Rodrigo > ; Pillai, Aurabindo > ; Wentland, Harry > ; Yin, Tianci

[PATCH 1/2] drm/amd/display: fix incorrrect valid irq check

valid DAL irq should be < DAL_IRQ_SOURCES_NUMBER. Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/display/dc/irq_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h index

[PATCH 2/2] drm/amd/display: fix null pointer access in gpu reset

During GPU reset, when receiving a DMCUB OUTBUX0 interrupt, DAL code will set it to be OUTBOX interrupt and sets hw interrupt. However, OUTBOX interrupt is not registered yet, so a NULL pointer access will be executed. Call Trace: dal_irq_service_set+0x30/0x90 [amdgpu]

RE: [PATCH] drm/amd/pm: skip PrepareMp1ForUnload message in s0ix

[AMD Official Use Only] Thanks update this patch and remove APU flag for avoiding over protection in this case. Reviewed-by: Prike Liang > -Original Message- > From: amd-gfx On Behalf Of > Shyam Sundar S K > Sent: Monday, June 28, 2021 3:55 PM > To: Deucher, Alexander ; Koenig,

[PATCH] drm/amdgpu: rectify line endings in umc v8_7_0 IP headers

Commit 6b36fa6143f6 ("drm/amdgpu: add umc v8_7_0 IP headers") adds the new file ./drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_7_0_sh_mask.h with DOS line endings, which is very uncommon for the kernel repository. Rectify the line endings in this file with dos2unix. Identified by a checkpatch

[PATCH] drm/amd/pm: skip PrepareMp1ForUnload message in s0ix

The documentation around PrepareMp1ForUnload message says that anything sent to SMU after this command would be stalled as the PMFW would not be in a state to take further job requests. Technically this is right in case of S3 scenario. But, this might not be the case during s0ix as the PMC driver

Re: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

On 6/28/2021 8:14 AM, Wang, Kevin(Yang) wrote: [AMD Official Use Only] *From:* Lazar, Lijo *Sent:* Friday, June 25, 2021 9:28 PM *To:* Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org *Cc:* Deucher, Alexander ;

RE: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

[AMD Official Use Only] Add @Min, Frank for the review. Regards, Hawking From: amd-gfx On Behalf Of Wang, Kevin(Yang) Sent: Monday, June 28, 2021 10:44 To: Lazar, Lijo ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian Subject: Re: [PATCH]

Re: [Mesa-dev] XDC 2021: Registration & Call for Proposals now open!

One week! Don't forget to submit your proposals! Sam On Tue, 2021-06-08 at 12:38 +0200, Samuel Iglesias Gonsálvez wrote: > Kind reminder. Deadline is Sunday, 4 July 2021 :-) > > Sam > > On Thu, 2021-05-20 at 10:01 +, Szwichtenberg, Radoslaw wrote: > > Hello! > >   > > Registration & Call

[PATCH] drm/amdgpu: enable sdma0 tmz for Raven/Renoir(V2)

Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1 by default for all asic. On Raven/Renoir, the sdma goldsetting changes SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0. This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1. Signed-off-by: Aaron Liu Acked-by: Luben Tuikov ---

Re: [PATCH] drm/amdgpu: add non-aligned address supported in amdgpu_device_vram_access()

[AMD Official Use Only] From: Lazar, Lijo Sent: Friday, June 25, 2021 9:28 PM To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Koenig, Christian Subject: Re: [PATCH] drm/amdgpu: add non-aligned address supported in

Re: [PATCH v4 05/27] drm/armada: Don't set struct drm_device.irq_enabled

Am 25.06.21 um 10:22 schrieb Thomas Zimmermann: The field drm_device.irq_enabled is only used by legacy drivers with userspace modesetting. Don't set it in armada. Signed-off-by: Thomas Zimmermann R-b'ed by Laurent via IRC --- drivers/gpu/drm/armada/armada_drv.c | 2 -- 1 file