[AMD Public Use]
Hi Christian,
> And where is the patch to switch i915 and remove the Intel copy of this?
Creating a patch for the switch.
> In general I think that every public function here needs a kerneldoc
> description what it is all about.
Making a kernel doc description for each public
[AMD Public Use]
Hi Alex,
I will fix the name and send a document in my next version.
Thanks,
Arun
-Original Message-
From: Alex Deucher
Sent: Tuesday, September 21, 2021 12:54 AM
To: Paneer Selvam, Arunpravin
Cc: Maling list - DRI developers ; Intel
Graphics Development ; amd-gfx
[AMD Public Use]
Hi Christian,
Thanks for the review, I will the send the next version fixing all issues.
Regards,
Arun
-Original Message-
From: Christian König
Sent: Wednesday, September 22, 2021 12:18 PM
To: Paneer Selvam, Arunpravin ; Koenig,
Christian ;
[AMD Official Use Only]
That is not how the register works. The *16 has nothing to do with cu counts.
This is to address the upper and lower 16 bits in the register as each half of
the register programs a separate SH.
From: Huang, Ray
Sent: Thursday,
Update golden setting to enable full compute units for cyan_skillfish.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index
We should use the real compute unit number for shader array mask. Some
asic doesn't have 16 compute units per shader array.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On 9/22/2021 9:47 PM, Alex Deucher wrote:
On Wed, Sep 22, 2021 at 5:08 AM Lazar, Lijo wrote:
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Allow us to query instances versions more cleanly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
Update the current state as boot state during dpm initialization.
During the subsequent initialization, set_power_state gets called to
transition to the final power state. set_power_state refers to values
from the current state and without current state populated, it could
result in NULL pointer
On Wed, Sep 22, 2021 at 09:52:07PM +0200, Borislav Petkov wrote:
> On Wed, Sep 22, 2021 at 05:30:15PM +0300, Kirill A. Shutemov wrote:
> > Not fine, but waiting to blowup with random build environment change.
>
> Why is it not fine?
>
> Are you suspecting that the compiler might generate
[AMD Official Use Only]
Fixed locally. Thanks!
Alex
From: Kuehling, Felix
Sent: Wednesday, September 22, 2021 12:58 PM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery
table
On Wed, Sep 22, 2021 at 3:54 AM Christian König
wrote:
>
> OMFG what mother of all patch sets.
>
> Patches #1-#6, #12, #14-#15, #27, #31, #35-#36, #59-#60, #64, #66 are
> Reviewed-by: Christian König
>
> Patches #7-#11, #13, #16-#26, #29-#30, #33-#34, #37-#50, #53, #55-#56,
> #58, #62, #65 are
On Wed, Sep 22, 2021 at 05:30:15PM +0300, Kirill A. Shutemov wrote:
> Not fine, but waiting to blowup with random build environment change.
Why is it not fine?
Are you suspecting that the compiler might generate something else and
not a rip-relative access?
--
Regards/Gruss,
Boris.
[AMD Official Use Only]
> -Original Message-
> From: Borislav Petkov
> Sent: Wednesday, September 22, 2021 7:41 AM
> To: Joshi, Mukul
> Cc: linux-e...@vger.kernel.org; x...@kernel.org; linux-ker...@vger.kernel.org;
> mi...@redhat.com; mche...@kernel.org; Ghannam, Yazen
> ;
On Aldebaran, GPU driver will handle bad page retirement
even though UMC is host managed. As a result, register a
bad page retirement handler on the mce notifier chain to
retire bad pages on Aldebaran.
Signed-off-by: Mukul Joshi
---
v1->v2:
- Use smca_get_bank_type() to determine MCA bank.
-
On 2021-09-22 13:58, praful.swarna...@amd.com wrote:
> From: Praful Swarnakar
>
> [Why]
> ASSR is dependent on Signed PSP Verstage to enable Content
> Protection for eDP panels. Unsigned PSP verstage is used
> during development phase causing ASSR to FAIL.
> As a result, link training is
From: Praful Swarnakar
[Why]
ASSR is dependent on Signed PSP Verstage to enable Content
Protection for eDP panels. Unsigned PSP verstage is used
during development phase causing ASSR to FAIL.
As a result, link training is performed with
DP_PANEL_MODE_DEFAULT instead of DP_PANEL_MODE_EDP for
eDP
On Wed, Sep 22, 2021 at 04:27:34PM +, Deucher, Alexander wrote:
> > On Sun, Sep 12, 2021 at 10:13:10PM -0400, Mukul Joshi wrote:
> > > Export smca_get_bank_type for use in the AMD GPU driver to determine
> > > MCA bank while handling correctable and uncorrectable errors in GPU
> > > UMC.
> > >
[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from
On Wed, Sep 22, 2021 at 12:16 PM Felix Kuehling wrote:
>
>
> Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> > Once we claim all 0x1002 PCI display class devices, we will
> > need to filter out devices owned by radeon.
> Could this list be built from radeon_PCI_IDS and r128_PCI_IDs in
>
Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Prerequisite for using IP versions in the driver rather
> than asic type.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git
Am 2021-09-21 um 2:07 p.m. schrieb Alex Deucher:
> rather than asic type.
I think this works as a first step. I'd like to clean up KFD and replace
a lot of the asic_family-based conditions with IP-version-based
conditions in a follow-up patch series.
Regards,
Felix
>
> Signed-off-by: Alex
[AMD Official Use Only]
> -Original Message-
> From: Borislav Petkov
> Sent: Wednesday, September 22, 2021 12:44 PM
> To: Deucher, Alexander
> Cc: Joshi, Mukul ; Alex Deucher
> ; linux-e...@vger.kernel.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; mi...@redhat.com;
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Borislav Petkov
> Sent: Wednesday, September 22, 2021 7:34 AM
> To: Joshi, Mukul ; Alex Deucher
>
> Cc: linux-e...@vger.kernel.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; mi...@redhat.com; mche...@kernel.org;
>
On Wed, Sep 22, 2021 at 5:08 AM Lazar, Lijo wrote:
>
>
>
> On 9/21/2021 11:37 PM, Alex Deucher wrote:
> > Allow us to query instances versions more cleanly.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
> >
Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Once we claim all 0x1002 PCI display class devices, we will
> need to filter out devices owned by radeon.
Could this list be built from radeon_PCI_IDS and r128_PCI_IDs in
drm/drm_pciids.h to avoid duplication? It also looks like your list is
[Public]
Fixed locally.
From: Lazar, Lijo
Sent: Wednesday, September 22, 2021 4:16 AM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version
checking
On 9/21/2021 11:37 PM, Alex
On Wed, Sep 22, 2021 at 3:54 AM Lazar, Lijo wrote:
>
>
>
> On 9/21/2021 11:36 PM, Alex Deucher wrote:
> > Hardcode the IP versions for asics without IP discovery tables
> > and then enumerate the asics based on the IP versions.
> >
> > TODO: fix SR-IOV support
> >
> > Signed-off-by: Alex Deucher
[AMD Official Use Only]
Fixed locally.
Alex
From: Lazar, Lijo
Sent: Wednesday, September 22, 2021 3:37 AM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking
On 9/21/2021
[Public]
Fixed locally. Thanks!
From: Lazar, Lijo
Sent: Wednesday, September 22, 2021 3:32 AM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking
On 9/21/2021 11:36 PM, Alex
On 2021-09-22 04:31, Pekka Paalanen wrote:
> On Tue, 21 Sep 2021 14:05:05 -0400
> Harry Wentland wrote:
>
>> On 2021-09-21 09:31, Pekka Paalanen wrote:
>>> On Mon, 20 Sep 2021 20:14:50 -0400
>>> Harry Wentland wrote:
>>>
...
>
>> Did anybody start any CM doc patches in Weston or
On Wed, Sep 22, 2021 at 3:32 AM Lazar, Lijo wrote:
>
>
>
> On 9/21/2021 11:36 PM, Alex Deucher wrote:
> > Use IP versions rather than asic_type to differentiate
> > IP version specific features.
> >
> > Signed-off-by: Alex Deucher
> > ---
> > drivers/gpu/drm/amd/amdgpu/nv.c | 75
[AMD Official Use Only]
Fixed locally. Thanks!
From: Lazar, Lijo
Sent: Wednesday, September 22, 2021 12:41 AM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs
On 9/21/2021 11:36
On 2021-09-20 20:14, Harry Wentland wrote:
> On 2021-09-15 10:01, Pekka Paalanen wrote:> On Fri, 30 Jul 2021 16:41:29 -0400
>> Harry Wentland wrote:
>>
>>> +If a display's maximum HDR white level is correctly reported it is trivial
>>> +to convert between all of the above representations of
On Wed, Sep 22, 2021 at 08:40:43AM -0500, Tom Lendacky wrote:
> On 9/21/21 4:58 PM, Kirill A. Shutemov wrote:
> > On Tue, Sep 21, 2021 at 04:43:59PM -0500, Tom Lendacky wrote:
> > > On 9/21/21 4:34 PM, Kirill A. Shutemov wrote:
> > > > On Tue, Sep 21, 2021 at 11:27:17PM +0200, Borislav Petkov
+ Harry, Leo
Can you guys get someone to clean this up?
Alex
On Wed, Sep 22, 2021 at 7:10 AM Jani Nikula wrote:
>
> On Tue, 21 Sep 2021, Nathan Chancellor wrote:
> > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> >> DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >>
On 9/21/21 4:58 PM, Kirill A. Shutemov wrote:
On Tue, Sep 21, 2021 at 04:43:59PM -0500, Tom Lendacky wrote:
On 9/21/21 4:34 PM, Kirill A. Shutemov wrote:
On Tue, Sep 21, 2021 at 11:27:17PM +0200, Borislav Petkov wrote:
On Wed, Sep 22, 2021 at 12:20:59AM +0300, Kirill A. Shutemov wrote:
I
On Sun, Sep 12, 2021 at 10:13:11PM -0400, Mukul Joshi wrote:
> On Aldebaran, GPU driver will handle bad page retirement
> even though UMC is host managed. As a result, register a
> bad page retirement handler on the mce notifier chain to
> retire bad pages on Aldebaran.
>
> v1->v2:
> - Use
On Sun, Sep 12, 2021 at 10:13:10PM -0400, Mukul Joshi wrote:
> Export smca_get_bank_type for use in the AMD GPU
> driver to determine MCA bank while handling correctable
> and uncorrectable errors in GPU UMC.
>
> v1->v2:
> - Drop the function is_smca_umc_v2().
> - Drop the patch to introduce a
On Tue, 21 Sep 2021, Nathan Chancellor wrote:
> On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
>> DP 2.0 brings some new DPCD addresses for PHY repeaters.
>>
>> Cc: dri-de...@lists.freedesktop.org
>> Reviewed-by: Manasi Navare
>> Signed-off-by: Jani Nikula
>> ---
>>
[AMD Official Use Only]
Might be better call the function is_poison_mode_supported. Other than that the
series is
Reviewed-by: Hawking Zhang
-Original Message-
From: Zhou1, Tao
Sent: Wednesday, September 22, 2021 18:33
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Clements,
[AMD Official Use Only]
Let's replace " RAS poison mode " with "poison is created, no user action is
needed" other than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Wednesday, September 22, 2021 18:33
To:
In ras poison mode, umc uncorrectable error will be ignored until
the corrupted data consumed by another ras module (such as gfx, sdma).
v2: simplify the debug message and replace dev_warn with dev_info.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 33
Add ras poison mode query interface for UMC.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 1 +
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 34 +
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
Add RAS poison supported flag and tell PSP RAS TA about the info.
v2: rename poison_mode to poison_supported, we can also disable poison
mode even we support it.
print poison_supported value if ras feature enablement fails.
Signed-off-by: Tao Zhou
---
On 9/22/2021 11:38 AM, Chen, Guchun wrote:
[Public]
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(5, 2, 0):
adev->sdma.num_instances = 4;
break;
Isn't the instance count also expected from discovery table?
This will be addressed
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Allow us to query instances versions more cleanly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 262 +-
On 9/22/2021 2:06 PM, Lazar, Lijo wrote:
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Use the instance to increment the entry in the table.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Use the instance to increment the entry in the table.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
On Tue, 21 Sep 2021 14:05:05 -0400
Harry Wentland wrote:
> On 2021-09-21 09:31, Pekka Paalanen wrote:
> > On Mon, 20 Sep 2021 20:14:50 -0400
> > Harry Wentland wrote:
> >
> >> On 2021-09-15 10:01, Pekka Paalanen wrote:> On Fri, 30 Jul 2021 16:41:29
> >> -0400
> >>> Harry Wentland wrote:
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 22 +++
1 file changed, 13 insertions(+), 9 deletions(-)
diff
On 9/21/2021 11:37 PM, Alex Deucher wrote:
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++-
1 file changed, 18 insertions(+), 23 deletions(-)
diff
OMFG what mother of all patch sets.
Patches #1-#6, #12, #14-#15, #27, #31, #35-#36, #59-#60, #64, #66 are
Reviewed-by: Christian König
Patches #7-#11, #13, #16-#26, #29-#30, #33-#34, #37-#50, #53, #55-#56,
#58, #62, #65 are Acked-by: Christian König
Comment for patch #28:
Doesn't this
On 9/21/2021 11:36 PM, Alex Deucher wrote:
Hardcode the IP versions for asics without IP discovery tables
and then enumerate the asics based on the IP versions.
TODO: fix SR-IOV support
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 --
On 9/21/2021 11:36 PM, Alex Deucher wrote:
Hardcode the IP versions for asics without IP discovery tables
and then enumerate the asics based on the IP versions.
TODO: fix SR-IOV support
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 417 --
On 9/21/2021 11:36 PM, Alex Deucher wrote:
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++
1 file changed, 109 insertions(+), 85 deletions(-)
diff
On 9/21/2021 11:36 PM, Alex Deucher wrote:
Use IP versions rather than asic_type to differentiate
IP version specific features.
v2: rebase
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 94 +--
1 file changed, 55 insertions(+), 39
On 9/21/2021 11:36 PM, Alex Deucher wrote:
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 75 +
1 file changed, 38 insertions(+), 37 deletions(-)
diff
Am 20.09.21 um 21:20 schrieb Arunpravin:
Port Intel buddy system manager to drm root folder
Add CPU mappable/non-mappable region support to the drm buddy manager
And where is the patch to switch i915 and remove the Intel copy of this?
In general I think that every public function here needs a
Am 21.09.21 um 17:51 schrieb Paneer Selvam, Arunpravin:
[AMD Public Use]
Hi Christian,
Please find my comments.
A better mail client might be helpful for mailing list communication. I
use Thunderbird, but Outlook with appropriate setting should do as well.
Thanks,
Arun
-Original
[Public]
> + switch (adev->ip_versions[SDMA0_HWIP]) {
> + case IP_VERSION(5, 2, 0):
> adev->sdma.num_instances = 4;
> break;
Isn't the instance count also expected from discovery table?
This will be addressed in patch 54 of the series.
Regards,
Guchun
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