On Sat, Oct 02, 2021 at 01:05:47AM +0300, Ville Syrjälä wrote:
> On Fri, Oct 01, 2021 at 04:48:15PM -0400, Sean Paul wrote:
> > On Fri, Oct 01, 2021 at 10:00:50PM +0300, Ville Syrjälä wrote:
> > > On Fri, Oct 01, 2021 at 02:36:55PM -0400, Sean Paul wrote:
> > > > On Fri, Sep 24, 2021 at 08:43:07AM
On Fri, Oct 01, 2021 at 04:48:15PM -0400, Sean Paul wrote:
> On Fri, Oct 01, 2021 at 10:00:50PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 01, 2021 at 02:36:55PM -0400, Sean Paul wrote:
> > > On Fri, Sep 24, 2021 at 08:43:07AM +0200, Fernando Ramos wrote:
> > > > Hi all,
> > > >
> > > > One of
On Fri, Oct 01, 2021 at 10:00:50PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 01, 2021 at 02:36:55PM -0400, Sean Paul wrote:
> > On Fri, Sep 24, 2021 at 08:43:07AM +0200, Fernando Ramos wrote:
> > > Hi all,
> > >
> > > One of the things in the DRM TODO list ("Documentation/gpu/todo.rst") was
> >
On Wed, Sep 29, 2021 at 03:39:25PM -0400, Mark Yacoub wrote:
> From: Mark Yacoub
>
> [Why]
> 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
> or Degamma props in the new CRTC state, allowing any invalid size to
> be passed on.
> 2. Each driver has its own LUT size,
On 10/1/21 12:48 PM, Alex Deucher wrote:
Check was missing for cyan skillfish.
Fixes: 82d96c34b0d49b ("drm/amd/display: add cyan_skillfish display support")
Reported-by: Randy Dunlap
Signed-off-by: Alex Deucher
Acked-by: Randy Dunlap # build-tested
Thanks.
---
On Wed, Sep 29, 2021 at 03:39:26PM -0400, Mark Yacoub wrote:
> From: Mark Yacoub
>
> [Why]
> drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
> sizes. There is no need to check it within amdgpu_dm_atomic_check.
>
> [How]
> Remove the local call to verify LUT sizes and
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 136 ++
1 file changed, 71 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
Check was missing for cyan skillfish.
Fixes: 82d96c34b0d49b ("drm/amd/display: add cyan_skillfish display support")
Reported-by: Randy Dunlap
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
Depends on DRM_AMDGPU_SI and DRM_AMD_DC
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 7dffc04a557e..127667e549c1 100644
---
On 10/1/21 12:09 AM, Stephen Rothwell wrote:
Hi all,
News: there will be no linux-next release on Monday.
Changes since 20210930:
on i386:
ERROR: modpost: "dm_ip_block" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
Full randconfig file is attached.
--
~Randy
config-r5146.gz
On Fri, Oct 01, 2021 at 02:36:55PM -0400, Sean Paul wrote:
> On Fri, Sep 24, 2021 at 08:43:07AM +0200, Fernando Ramos wrote:
> > Hi all,
> >
> > One of the things in the DRM TODO list ("Documentation/gpu/todo.rst") was to
> > "use DRM_MODESET_LOCAL_ALL_* helpers instead of boilerplate". That's
On Fri, Sep 24, 2021 at 08:43:07AM +0200, Fernando Ramos wrote:
> Hi all,
>
> One of the things in the DRM TODO list ("Documentation/gpu/todo.rst") was to
> "use DRM_MODESET_LOCAL_ALL_* helpers instead of boilerplate". That's what this
> patch series is about.
>
> You will find two types of
Hi,
It looks like Nicholas Choi tested your patch, and it fixed the issue.
Reviewed-by: Rodrigo Siqueira
Thanks
On 10/01, Alex Deucher wrote:
> Missing 4.1.2.
>
> Fixes: 30bce8c7213829 ("drm/amdgpu: add initial IP discovery support for vega
> based parts")
> Signed-off-by: Alex Deucher
>
Missing 4.1.2.
Fixes: 30bce8c7213829 ("drm/amdgpu: add initial IP discovery support for vega
based parts")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: 2021/October/01, Friday 10:31 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into
> DRM_AMD_DC_DCN
>
> No need for a separate
Applied. Thanks!
Alex
On Fri, Oct 1, 2021 at 6:16 AM Christian König wrote:
>
> Am 01.10.21 um 12:13 schrieb Guo Zhengkui:
> > Remove two repeated includings in line 46 and 47.
> >
> > Signed-off-by: Guo Zhengkui
>
> Acked-by: Christian König
>
> > ---
> >
[Public]
Got your point. Will send a new patch to address this.
Regards,
Guchun
-Original Message-
From: Grodzovsky, Andrey
Sent: Friday, October 1, 2021 10:29 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Koenig,
Christian ; Pan, Xinhui ;
Deucher, Alexander
Subject: Re:
From what I see here you supposed to have actual deadlock and not only
warning, sched_fence->finished is first signaled from within
hw fence done callback (drm_sched_job_done_cb) but then again from
within it's own callback (drm_sched_entity_kill_jobs_cb) and so
looks like same fence object is
On Wed, Sep 29, 2021 at 10:30:13PM -0400, Alex Deucher wrote:
> Hi Dave, Daniel,
>
> Fixes for 5.15.
>
> The following changes since commit 05812b971c6d605c00987750f422918589aa4486:
>
> Merge tag 'drm/tegra/for-5.15-rc3' of
> ssh://git.freedesktop.org/git/tegra/linux into drm-fixes
On Fri, Oct 01, 2021 at 12:50:35PM +0200, Christian König wrote:
> Hey, Andrey.
>
> while investigating some memory management problems I've got the logdep
> splat below.
>
> Looks like something is wrong with drm_sched_entity_kill_jobs_cb(), can you
> investigate?
Probably needs more irq_work
On Wed, Sep 29, 2021 at 12:17:35AM +0300, Oded Gabbay wrote:
> On Tue, Sep 28, 2021 at 8:36 PM Jason Gunthorpe wrote:
> >
> > On Sun, Sep 12, 2021 at 07:53:09PM +0300, Oded Gabbay wrote:
> > > From: Tomer Tayar
> > >
> > > Implement the calls to the dma-buf kernel api to create a dma-buf
> > >
On Thu, Sep 30, 2021 at 03:46:35PM +0300, Oded Gabbay wrote:
> After reading the kernel iommu code, I think this is not relevant
> here, and I'll add a comment appropriately but I'll also write it
> here, and please correct me if my understanding is wrong.
>
> The memory behind this specific
From: "Leo (Hanghong) Ma"
[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;
[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
From: Jimmy Kizito
[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.
The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
-
From: "Leo (Hanghong) Ma"
[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45
From: Aric Cyr
This version brings along following fixes:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix
From: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Hansen
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu
Acked-by: Solomon Chiu
Signed-off-by: Hansen
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33
From: Nikola Cornij
[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1
Reviewed-by: Zhan Liu
Acked-by: Solomon Chiu
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Jake Wang
[Why & How]
Added root clock optimization debug flags for future debugging.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Solomon Chiu
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 18 ++
1 file changed, 18 insertions(+)
diff --git
From: Charlene Liu
[why]
dc->config.disable_dmcu set to true, but it still need create
dmcub based abm.
[how]
check to dc->caps.dmcub_support check.
Reviewed-by: Aric Cyr
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 +-
1 file
From: Aric Cyr
[Why]
3DLUT not updated due to missing condition
[How]
Check if 3DLUT update is needed
Reviewed-by: Anthony Koo
Acked-by: Solomon Chiu
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Qingqing Zhuo
[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.
[How]
Move FPU code for DCN2x to dml/dcn20.
Reviewed-by: Rodrigo Siqueira
Acked-by: Solomon Chiu
Signed-off-by: Qingqing Zhuo
---
From: George Shen
[Why]
Overriding link setting inside override_training_settings
result in fallback link settings being ignored. This can
potentially cause link training to always fail and consequently
result in an infinite loop of link training to occur in
dp_verify_link_cap during detection.
From: Charlene Liu
[why]
fix NULL pointer in irq_service_dcn201
[how]
initialize proper num of irq source for linu
Reviewed-by: Sung joon Kim
Acked-by: Solomon Chiu
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
From: Wyatt Wood
[Why]
Running into bugchecks during stress test where rptr is 0x.
Typically this is caused by a hard hang, and can come from HW outside
of DCN.
[How]
To prevent bugchecks when writing the DMUB rptr, fist check that the
rptr is valid.
Reviewed-by: Nicholas Kazlauskas
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection
No need for a separate kconfig option at this point.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 9 -
drivers/gpu/drm/amd/display/dc/Makefile | 2 --
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile | 2 --
No, scheduler restart and device unlock must take place
inamdgpu_pci_resume (see struct pci_error_handlers for the various
states of PCI recovery). So just add a flag (probably in amdgpu_device)
so we can remember what pci_channel_state_t we came from (unfortunately
it's not passed to us in
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, October 1, 2021 08:26
> To: Lazar, Lijo
> Cc: amd-gfx list ; Deucher, Alexander
> ; Limonciello, Mario
> ; Zhang, Hawking ;
> Wang, Yang(Kevin) ; Quan, Evan
>
> Subject: Re: [PATCH] drm/amdgpu: During s0ix don't wait
On Fri, Oct 1, 2021 at 6:16 AM Lijo Lazar wrote:
>
> In the rare event when GFX IP suspend coincides with a s0ix entry, don't
> schedule a delayed work, instead signal PMFW immediately to allow GFXOFF
> entry. GFXOFF is a prerequisite for s0ix entry. PMFW needs to be
> signaled about GFXOFF
Remove two repeated includings in line 46 and 47.
Signed-off-by: Guo Zhengkui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index
-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/trix-redhat-com/drm-amdkfd-match-the-signatures-of-the-real-and-stub-kgd2kfd_probe/20211001-043648
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
02d5e016800d082058b3d3b7c3ede136cdc6ddcb
Hey, Andrey.
while investigating some memory management problems I've got the logdep
splat below.
Looks like something is wrong with drm_sched_entity_kill_jobs_cb(), can
you investigate?
Thanks,
Christian.
[11176.741052]
[11176.741056] WARNING:
In the rare event when GFX IP suspend coincides with a s0ix entry, don't
schedule a delayed work, instead signal PMFW immediately to allow GFXOFF
entry. GFXOFF is a prerequisite for s0ix entry. PMFW needs to be
signaled about GFXOFF status before amd-pmc module passes OS HINT
to PMFW telling that
Am 01.10.21 um 12:13 schrieb Guo Zhengkui:
Remove two repeated includings in line 46 and 47.
Signed-off-by: Guo Zhengkui
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 --
1 file changed, 2 deletions(-)
diff --git
[Public]
Hi Andrey,
Do you mean to move the code of drm_sched_resubmit_jobs and drm_sched_start in
amdgpu_pci_resume to amdgpu_pci_error_detected, under the case
pci_channel_io_frozen?
Then leave amdgpu_pci_resume as a null function, and in this way, we can drop
the acquire/lock write lock
It means that you should modify your patch, yes.
Regards,
Christian.
Am 01.10.21 um 05:02 schrieb 郭正奎:
So, it means I need to make another commit?
Zhengkui
*From:*guozheng...@vivo.com *On Behalf Of
*Christian K?nig
*Sent:* Thursday, September 30, 2021 7:56 PM
*To:* Guo Zhengkui ; Simon
On Tuesday, 14 September 2021 2:16:02 AM AEST Alex Sierra wrote:
> Device Public type uses device memory that is coherently accesible by
> the CPU. This could be shown as SP (special purpose) memory range
> at the BIOS-e820 memory enumeration. If no SP memory is supported in
> system, this could
On Friday, 24 September 2021 1:52:47 AM AEST Sierra Guiza, Alejandro (Alex)
wrote:
>
> On 9/21/2021 12:14 AM, Alistair Popple wrote:
> > On Tuesday, 21 September 2021 6:05:30 AM AEST Sierra Guiza, Alejandro
> > (Alex) wrote:
> >> On 9/20/2021 3:53 AM, Alistair Popple wrote:
> >>> On Tuesday, 14
So, it means I need to make another commit?
Zhengkui
From: guozheng...@vivo.com On Behalf Of Christian K?nig
Sent: Thursday, September 30, 2021 7:56 PM
To: Guo Zhengkui ; Simon Ser
Cc: Deucher, Alexander ; Pan, Xinhui
; David Airlie ; Daniel Vetter
; Chen, Guchun ; Zhou, Peng Ju
; Zhang,
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