This patch seems to change z8 - not that I know what z8 or z9 are
On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez
wrote:
>
> From: Eric Yang
>
> [Why]
> Z9 latency is higher than when we originally tuned the watermark
> parameters, causing underflow. Increasing the value until the latency
> issu
From: Roman Li
[Why]
On renoir usb-c port stops functioning on resume after f/w update.
New dmub firmware caused regression due to conflict with dmcu.
With new dmub f/w dmcu is superseded and should be disabled.
[How]
- Disable dmcu for all dcn21.
Check dmesg for dmub f/w version.
The old firmw
On 2021-10-15 11:11 a.m., Jonathan Kim wrote:
ROCr needs to be able to identify all devices that have direct access to
fine grain memory, which should include CPUs that are connected to GPUs
over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the
CPU is part of the hive.
v3: av
On Fri, Oct 15, 2021 at 10:33:29PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 09:24:06PM +0200, Claudio Suarez wrote:
> > On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> > > On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > > > According to the document
On Fri, Oct 15, 2021 at 09:24:06PM +0200, Claudio Suarez wrote:
> On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > > According to the documentation, drm_add_edid_modes
> > > "... Also fills out the &drm_display_in
On Fri, Oct 15, 2021 at 03:03:13PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> > According to the documentation, drm_add_edid_modes
> > "... Also fills out the &drm_display_info structure and ELD in @connector
> > with any information which can be
On Fri, Oct 15, 2021 at 06:18:34PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Ville Syrjälä wrote:
> > On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
> >> On Fri, 15 Oct 2021, Claudio Suarez wrote:
> >> > Once EDID is parsed, the monitor HDMI support information is available
>
From: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++---
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 30 +--
.../amd/display/dc/dcn10/dc
From: Aric Cyr
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added m
This reverts commit 50ac5b14c74c5706796cb6378f25a2121dba5b2d.
This patch introduced a couple of dmesg warnings, this is not a valid
approach anymore. For this reason, we are reverting this patch, and we
need to revert the workaround patch.
Cc: Hanghong Ma
Cc: Mark Broadworth
Signed-off-by: Agus
This reverts commit 4e605d4b6a510f751b22df4d13829aefb8a0ccec.
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 6db611f9f554.
From: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/d
From: Nikola Cornij
[why]
The original latencies were causing underflow in some modes
[how]
Replace with the up-to-date watermark values based on new measurments
Reviewed-by: Ahmad Othman
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nikola Cornij
---
.../amd/display/dc/clk_mgr/dcn31/d
From: Jake Wang
[Why]
bios_golden_init will override dccg_init during init_hw.
[How]
Move dccg_init to after bios_golden_init.
Reviewed-by: Aric Cyr
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c |
From: Nevenko Stupar
[Why]
V3_4 is latest in use.
[How]
Add bios parser support for firmware_info_v3_4 along
with some relevant fields it is also retrieving from dce_info
and smu_info.
Reviewed-by: Jun Lei
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nevenko Stupar
---
.../drm/amd/dis
From: Jake Wang
[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h| 9 +++--
drivers/gpu/drm/amd/display/dc/dcn31/dcn
From: Jake Wang
[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 15 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
From: Jake Wang
[Why & How]
Z10 save is done during PSR and bootup.
DSC disable does not need to save for Z10.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4
1 file changed, 4 deletions(-)
From: Eric Yang
[Why]
Z9 latency is higher than when we originally tuned the watermark
parameters, causing underflow. Increasing the value until the latency
issues is resolved.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Eric Yang
---
drivers/gpu/drm/a
From: Jake Wang
[Why & How]
Disable root clock for dsc when not being used.
Reviewed-by: Nikola Cornij
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 16 -
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 72 +++
From: Nicholas Kazlauskas
[Why]
Immediate flip can be enabled dynamically and has higher BW requirements
when validating which voltage mode to use.
If we validate when it's not set then potentially DCFCLK will be too low
and we will underflow.
[How]
DM always requires support so always require
From: Mikita Lipski
[why]
PSR_STATE2b was introduced on DMCUB side, but not on the driver side,
which caused convert_psr_state helper function to return
PSR_STATE_INVALID. That caused visual lagging during state transition.
[how]
Add PSR_STATE2b to dc_psr_state and convert_psr_state
Reviewed-by
From: Hansen
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused
Reviewed-by: Nicholas Kazlauskas
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Hansen
---
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 17 +
1 file changed, 17 insertions(+)
diff --git a
From: Nicholas Kazlauskas
[Why]
Prefetch BW calculated is lower than the DML reference because of a
porting error that's excluding cursor and row bandwidth from the
pixel data bandwidth.
[How]
Change the dml_max4 to dml_max3 and include cursor and row bandwidth
in the same calculation as the res
From: "Lai, Derek"
[Why]
Error message on Linux when booting.
[How]
Removed power down on boot from DCN31 HW init
to match DCN10 HW init.
Reviewed-by: Anthony Koo
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Derek Lai
---
.../drm/amd/display/dc/dcn31/dcn31_hwseq.c| 43
From: Nikola Cornij
[why]
The requirement is that image width up to 4096 shall be supported
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Nikola Cornij
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Aric Cyr
[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.
[How]
Validate that src and dst rects are valid before using for scaling
calculations.
Reviewed-by: Josip Pavic
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
---
drive
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
From: Wenjing Liu
Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control. However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
Si
From: Wenjing Liu
[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.
Reviewed-by: George Shen
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/dis
From: Jimmy Kizito
[Why]
When rapidly plugging and unplugging a DP sink, detection link
training can be mistakenly skipped.
This is due to the hotplug processing occurring before the
encoder assignment logic has had a chance to process the removal
of a stream. The encoder that would be used for
From: Jimmy Kizito
[Why]
When copying a stream, the encoder assigned to it is copied too.
Encoder assignment should only happen when executing the encoder
assignment function link_encs_assign().
[How]
Clear the link encoder pointer for copied stream.
Reviewed-by: Meenakshikumar Somasundaram
Re
From: Michael Strauss
[WHAT]
One of the current VPG power on calls is unnecessary
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwse
From: Jake Wang
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 41 ++-
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state
From: Wenjing Liu
Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control. However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.
Reviewed-by: Ariel Bernstein
Acked-by: Agustin Gutierrez Sanchez
Si
From: Aric Cyr
[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.
[How]
Validate that src and dst rects are valid before using for scaling
calculations.
Reviewed-by: Josip Pavic
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Aric Cyr
---
drive
From: Wenjing Liu
[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.
Reviewed-by: George Shen
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/dis
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Aric Cyr
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 d
From: Michael Strauss
[WHAT]
One of the current VPG power on calls is unnecessary
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Michael Strauss
---
drivers/gpu/drm/amd/display/dc/core/dc.c| 10 --
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwse
From: Jimmy Kizito
[Why]
When rapidly plugging and unplugging a DP sink, detection link
training can be mistakenly skipped.
This is due to the hotplug processing occurring before the
encoder assignment logic has had a chance to process the removal
of a stream. The encoder that would be used for
From: Jimmy Kizito
[Why]
When copying a stream, the encoder assigned to it is copied too.
Encoder assignment should only happen when executing the encoder
assignment function link_encs_assign().
[How]
Clear the link encoder pointer for copied stream.
Reviewed-by: Meenakshikumar Somasundaram
Re
From: Jake Wang
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang
Acked-by: Agustin Gutierrez Sanchez
Signed-off-by: Jake Wang
---
.../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 5 ++-
.../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 41 ++-
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state
On Fri, Oct 15, 2021 at 03:30:49PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 01:37:13PM +0200, Claudio Suarez wrote:
> > Once EDID is parsed, the monitor HDMI support information is available
> > through drm_display_info.is_hdmi. Retriving the same information with
> > drm_detect_hdmi_m
On Fri, 15 Oct 2021, Ville Syrjälä wrote:
> On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
>> On Fri, 15 Oct 2021, Claudio Suarez wrote:
>> > Once EDID is parsed, the monitor HDMI support information is available
>> > through drm_display_info.is_hdmi. Retriving the same information
On 2021-10-15 07:37, Claudio Suarez wrote:
> a) Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. The amdgpu driver still calls
> drm_detect_hdmi_monitor() to retrieve the same information, which
> is less efficient. Change to drm_display_
ROCr needs to be able to identify all devices that have direct access to
fine grain memory, which should include CPUs that are connected to GPUs
over xGMI. The GPU hive ID can be mapped onto the CPU hive ID since the
CPU is part of the hive.
v3: avoid quadratic search by doing linear list read ins
[AMD Official Use Only]
Would it better create a function to interpret the RAS TA error? I expect more
error status is available soon?
Regards,
Hawking
-Original Message-
From: Zhou1, Tao
Sent: Friday, October 15, 2021 17:11
To: amd-gfx@lists.freedesktop.org; Clements, John ;
Zhang, H
On Fri, Oct 15, 2021 at 03:44:48PM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Claudio Suarez wrote:
> > Once EDID is parsed, the monitor HDMI support information is available
> > through drm_display_info.is_hdmi. Retriving the same information with
> > drm_detect_hdmi_monitor() is less effic
On Fri, 15 Oct 2021, Claudio Suarez wrote:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi where possible.
>
> This i
On Fri, Oct 15, 2021 at 01:37:13PM +0200, Claudio Suarez wrote:
> Once EDID is parsed, the monitor HDMI support information is available
> through drm_display_info.is_hdmi. Retriving the same information with
> drm_detect_hdmi_monitor() is less efficient. Change to
> drm_display_info.is_hdmi where
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Use this value instead of calling
drm_detect_hdmi_monitor() to avoid a second parse.
This is a TODO task in Documentation/gpu/todo.rst
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/vc4/v
According to the documentation, drm_add_edid_modes
"... Also fills out the &drm_display_info structure and ELD in @connector
with any information which can be derived from the edid."
drm_add_edid_modes accepts a struct edid *edid parameter which may have a
value or may be null. When it is not null
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/tegra/hdmi.c | 6 +-
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information is less
efficient. Change to drm_display_info.is_hdmi
This is a TODO task in Documentation/gpu/todo.rst
Also, correct an inacurracy or bug in
radeon_connector_ge
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/msm/hdmi/hdmi_connector.c
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c |
a) Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. The amdgpu driver still calls
drm_detect_hdmi_monitor() to retrieve the same information, which
is less efficient. Change to drm_display_info.is_hdmi
This is a TODO task in Documentation/gpu
Copy&paste from the TODO document Documentation/gpu/todo.rst
===
Replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi
---
Once EDID is parsed, the monitor HDMI support information is available through
drm_display_info.is_hdmi
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/sti/sti_hdmi.c | 10 +
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/rockchip/inno_hdmi.c |
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/zte/zx_hdmi.c | 4 ++--
1
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi where possible
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/bridge/adv
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/nouveau/dispnv50/disp.c
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi where possible.
This is a TODO task in Documentation/gpu/todo.rst
Signed-off
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/gma500/cdv_intel_hdmi.c |
Once EDID is parsed, the monitor HDMI support information is available
through drm_display_info.is_hdmi. Retriving the same information with
drm_detect_hdmi_monitor() is less efficient. Change to
drm_display_info.is_hdmi
Signed-off-by: Claudio Suarez
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 6
On Fri, Oct 15, 2021 at 01:36:59PM +0200, Claudio Suarez wrote:
> According to the documentation, drm_add_edid_modes
> "... Also fills out the &drm_display_info structure and ELD in @connector
> with any information which can be derived from the edid."
>
> drm_add_edid_modes accepts a struct edid
[AMD Official Use Only]
> -Original Message-
> From: Borislav Petkov
> Sent: Thursday, October 14, 2021 5:01 PM
> To: Quan, Evan
> Cc: Alex Deucher ; amd-gfx list g...@lists.freedesktop.org>; LKML ; Deucher,
> Alexander ; Pan, Xinhui
> ; Chen, Guchun
> Subject: Re: bf756fb833cb ("drm
Output a warning message if RAS TA returns UNSUPPORTED_ERROR_INJ status.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h | 7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdg
Actually, cu_mask has been copied to mqd memory and
don't have to persist in queue_properties. Remove it
from queue_properties.
Use struct queue_update_info to wrap queue_properties
and cu mask, then pass it to update queue operation.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdkfd/kfd_ch
Currently, queue is updated with data stored in queue_properties.
And all allocated resource in queue_properties will not be freed
until the queue is destroyed.
But some properties(e.g., cu mask) bring some memory management
headaches(e.g., memory leak) and make code complex. Actually they
don't h
[AMD Official Use Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Tao Zhou
Sent: Friday, October 15, 2021 15:28
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ;
Clements, John ; Yang, Stanley
Cc: Zhou1, Tao
Subject: [PATCH] drm/amdgp
Some registers' access will fail without PSP RL after resume.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2bfe0682e0e6..88274
On Thu, Oct 14, 2021 at 10:39:27AM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
>
> Signed-of
On Thu, Oct 14, 2021 at 10:39:27AM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> There are several places where ZONE_DEVICE struct pages assume a reference
> count == 1 means the page is idle and free. Instead of open coding this,
> add a helper function to hide this detail.
>
> Signed-of
On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> ZONE_DEVICE struct pages have an extra reference count that complicates the
> code for put_page() and several places in the kernel that need to check the
> reference count to see that a page is not being used
show() must not use snprintf() when formatting the value to be
returned to user space.
Fix the following coccicheck warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:427:
WARNING: use scnprintf or sprintf.
Signed-off-by: Qing Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +-
1 file c
On Thu, Oct 14, 2021 at 10:35:27AM -0700, Ralph Campbell wrote:
> I ran xfstests-dev using the kernel boot option to "fake" a pmem device
> when I first posted this patch. The tests ran OK (or at least the same
> tests passed with and without my patch).
Hmm. I know nothing of xfstests but
test
On Thu, Oct 14, 2021 at 10:39:28AM -0500, Alex Sierra wrote:
> From: Ralph Campbell
>
> ZONE_DEVICE struct pages have an extra reference count that complicates the
> code for put_page() and several places in the kernel that need to check the
> reference count to see that a page is not being used
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