As there is no internal cache for enabled ppfeatures now. Thus the 2nd
parameter will be not needed any more.
Signed-off-by: Evan Quan
Change-Id: I0c1811f216c55d6ddfabdc9e099dc214c21bdf2e
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
As the enabled ppfeatures are just retrieved ahead. We can use
that directly instead of retrieving again and again.
Signed-off-by: Evan Quan
Change-Id: I08827437fcbbc52084418c8ca6a90cfa503306a9
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +-
1 file changed, 9 insertions(+), 1
The following scenarios make the driver cache for enabled ppfeatures
outdated and invalid:
- Other tools interact with PMFW to change the enabled ppfeatures.
- PMFW may enable/disable some features behind driver's back. E.g.
for sienna_cichild, on gfxoff entering, PMFW will disable gfx
Use uint64_t instead of an array of uint32_t. This can avoid
some non-necessary intermediate uint32_t -> uint64_t conversions.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Change-Id: I4e217357203a23440f058d7e25f55eaebd15c5ef
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
The supported features should be retrieved just after EnableAllDpmFeatures
message
complete. And the check(whether some dpm feature is supported) is only needed
when we
decide to enable or disable it.
Signed-off-by: Evan Quan
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
Instead of having two which do the same thing.
Signed-off-by: Evan Quan
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f
--
v1->v2:
- use SMU IP version check rather than an asic type check(Alex)
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 2 +-
As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: I9e845ba84dd45d0826506de44ef4760fa851a516
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.
Only allow ASICs which support GMC CG features accessing
related registers. As some ASICs support GMC CG but cg_flags
are not set. Use GC IP
Fix uninitialized variable use
warning: variable 'reg_access_ctrl' is uninitialized when used here
[-Wuninitialized]
scratch_reg0 = (void __iomem *)adev->rmmio + 4 *
reg_access_ctrl->scratch_reg0;
Fixes: 51263163eb3f("drm/amdgpu: add helper for rlcg indirect reg
access")
Reported-by:
The allow_fb_modifiers flag is unnecessary since it has been replaced
with fb_modifiers_not_supported flag.
v3:
- change the order as follows:
1. add fb_modifiers_not_supported flag
2. add default modifiers
3. remove allow_fb_modifiers flag
v5:
- keep a sanity check in plane init func
The LINEAR modifier is advertised as default if a driver doesn't specify
modifiers.
v2:
- rebase to the latest master branch (5.16.0+)
+ "drm/plane: Make format_mod_supported truly optional" patch [1]
[1] https://patchwork.freedesktop.org/patch/467940/?series=98255=3
v3:
- change the
If only linear modifier is advertised, since there are many drivers that
only linear supported, the DRM core should handle this rather than
open-coding in every driver. However, there are legacy drivers such as
radeon that do not support modifiers but infer the actual layout of the
underlying
Some drivers whose planes only support linear layout fb do not support format
modifiers.
These drivers should support modifiers, however the DRM core should handle this
rather than open-coding in every driver.
In this patch series, these drivers expose format modifiers based on the
following
v2:
- remove unnecessary comments and Id
[Why]
External displays take priority over internal display when there are fewer
display controllers than displays.
[How]
The root cause is because of that number of the crtc is not correct.
The number of the crtc on the 3250c is 3, but on the 3500c is
[AMD Official Use Only]
Ping...
> -Original Message-
> From: Zhou1, Tao
> Sent: Wednesday, January 26, 2022 7:05 PM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Yang, Stanley ; Chai,
> Thomas ; Clements, John ;
> Lazar, Lijo
> Cc: Zhou1, Tao
> Subject: [PATCH] drm/amdgpu:
[Public]
After giving it a second thought, I will apply a similar patch on internal
branch first, then get it promoted to external branch. This patch is abandoned.
Thanks,
Zhan
> -Original Message-
> From: Liu, Zhan
> Sent: 2022/January/27, Thursday 9:51 PM
> To:
[Public]
[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume. However, we still need to keep Vdd on
at S3 resume. Turning eDP Vdd off at resume will result in black
screen at S3 resume.
[How]
Don't turn eDP Vdd off when there is an existing eDP
[AMD Official Use Only]
The error message is from HIQ dequeue procedure, not from HCQ, so no doorbell
writing.
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477067] Call Trace:
Jan 25 16:10:58 lnx-ci-node kernel: [18161.477072] dump_stack+0x7d/0x9c
Jan 25 16:10:58 lnx-ci-node kernel:
Am 2022-01-20 um 18:13 schrieb Philip Yang:
Output user queue eviction and restore event. User queue eviction may be
triggered by migration, MMU notifier, TTM eviction or device suspend.
User queue restore may be rescheduled if eviction happens again while
restore.
Signed-off-by: Philip Yang
Am 2022-01-20 um 18:13 schrieb Philip Yang:
After migration is finished, output timestamp when migration starts,
duration of migration, svm range address and size, GPU id of
migration source and destination and svm range attributes,
Migration trigger could be prefetch, CPU or GPU page fault
Andrew,
We're somehow new on this procedure. Are you referring to rebase this
patch series to
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
<5.17-rc1 tag>?
Regards,
Alex Sierra
Alex Deucher,
Just a quick heads up. This patch series contains changes to the amdgpu
driver
Am 2022-01-20 um 18:13 schrieb Philip Yang:
Output timestamp when GPU recoverable fault starts, ends and duration to
recover the fault, if migration happened or only GPU page table is
updated, fault address, read or write fault.
Signed-off-by: Philip Yang
---
Am 2022-01-20 um 18:13 schrieb Philip Yang:
Process receive event from same process by default. Add a flag to be
able to receive event from all processes, this requires super user
permission.
Event with pid 0 send to all processes, to keep the default behavior of
existing SMI events.
On Wed, 26 Jan 2022 21:09:39 -0600 Alex Sierra wrote:
> This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
> owned by a device that can be mapped into CPU page tables like
> MEMORY_DEVICE_GENERIC and can also be migrated like
> MEMORY_DEVICE_PRIVATE.
Some more reviewer input
Applied. Thanks!
Alex
On Wed, Jan 26, 2022 at 4:48 AM wrote:
>
> From: huangqu
>
> Wrong order for config and counter_id parameters was passed, when calling
> df_v3_6_pmc_set_deferred and df_v3_6_pmc_is_deferred functions.
>
> Signed-off-by: huangqu
> ---
>
Applied. Thanks!
Alex
On Thu, Jan 27, 2022 at 3:45 AM tangmeng wrote:
>
> There is a spelling mistake. Fix it.
>
> Signed-off-by: tangmeng
> ---
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
[Public]
Thanks for the review. I'm only going to merge 2-4 initially though.
The reporter on 1 has some questionable results, and I have a follow up patch
for them to try.
If that combined with 1 looks good I'll bring that patch for review.
From: Deucher, Alexander
Sent: Thursday, January
On Thu, Jan 27, 2022 at 1:54 PM Luben Tuikov wrote:
>
> Expose the FRU SMU I2C bus.
Maybe rework the commit message a bit. Something like:
Expose both SMU i2c buses. Some boards use the same bus for both the
RAS and FRU EEPROMs others use different buses. This enables the
additional i2c bus
Enable the FRU EEPROM I2C bus for Sienna Cichlid
server boards, for which it is enabled by checking
the VBIOS version.
Cc: Roy Sun
Cc: Alex Deucher
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff
Expose the FRU SMU I2C bus.
Cc: Roy Sun
Co-developed-by: Alex Deucher
Signed-off-by: Luben Tuikov
---
.../gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c| 6 +-
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 14 ++--
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 80 ---
On Wed, Jan 26, 2022 at 8:56 AM Aditya Garg wrote:
>
> From: Aun-Ali Zaidi
>
> The eDP link rate reported by the DP_MAX_LINK_RATE dpcd register (0xa) is
> contradictory to the highest rate supported reported by
> EDID (0xc = LINK_RATE_RBR2). The effects of this compounded with commit
>
Reviewed-by: Luben Tuikov
Regards,
Luben
On 1/27/22 12:23, Alex Deucher wrote:
> Return an error if someone tries to use the i2c bus when the
> SMU is not running. Otherwise we can end up sending commands
> to the SMU which will either get ignored or could cause other
> issues depending on
Check if the identifer is defined.
Cc: victor.z...@amd.com
Reported-by: kernel test robot
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
Return an error if someone tries to use the i2c bus when the
SMU is not running. Otherwise we can end up sending commands
to the SMU which will either get ignored or could cause other
issues depending on what state the GPU and SMU are in.
Cc: luben.tui...@amd.com
Signed-off-by: Alex Deucher
---
The hang you're seeing is the result of a command submission of an
UNMAP_QUEUES and QUERY_STATUS command to the HIQ. This is done using a
doorbell. KFD writes commands to the HIQ and rings a doorbell to wake up
the HWS (see kq_submit_packet in kfd_kernel_queue.c). Why does this
doorbell not
[Public]
Series is:
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Mario
Limonciello
Sent: Wednesday, January 26, 2022 5:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liang, Prike ; Limonciello, Mario
Subject: [PATCH v6 4/4] drm/amd: Only run s3 or s0ix
[AMD Official Use Only]
Hi Jun,
In RAS code, we have this special handling for Vega10. Can you elaborate it
please? Any problem you have observed?
Regards,
Guchun
-Original Message-
From: Ma, Jun
Sent: Thursday, January 27, 2022 7:47 PM
To: amd-gfx@lists.freedesktop.org;
[AMD Official Use Only]
Pushed out, with your Rb.
From: Alex Deucher
Sent: Thursday, January 27, 2022 09:11
To: Newton, Jeremy
Cc: amd-gfx@lists.freedesktop.org; StDenis, Tom
Subject: Re: FIx for UMR arm build
Reviewed-by: Alex Deucher
On Thu, Jan
Please use C style comments /* */. WIth that fixed:
Reviewed-by: Alex Deucher
On Thu, Jan 27, 2022 at 3:12 AM RyanLin wrote:
>
> [Why]
> External displays take priority over internal display when there are fewer
> display controllers than displays.
>
> [How]
> The root cause is because of
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
v2(Matthew Auld):
- replace spinlock with mutex as we call kmem_cache_zalloc
(..., GFP_KERNEL) in drm_buddy_alloc() function
- lock drm_buddy_block_trim() function as it calls
Move shared vram inline functions and structs
into a header file
Signed-off-by: Arunpravin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 51
1 file changed, 51 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
diff --git
On contiguous allocation, we round up the size
to the *next* power of 2, implement a function
to free the unused pages after the newly allocate block.
v2(Matthew Auld):
- replace function name 'drm_buddy_free_unused_pages' with
drm_buddy_block_trim
- replace input argument name
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915
Reviewed-by: Alex Deucher
On Thu, Jan 27, 2022 at 8:39 AM Newton, Jeremy wrote:
>
> [AMD Official Use Only]
>
>
> Sorry I think I forgot to attach the patch
>
> From: Newton, Jeremy
> Sent: January 27, 2022 8:39 AM
> To: amd-gfx@lists.freedesktop.org
> Cc:
[AMD Official Use Only]
Sorry I think I forgot to attach the patch
From: Newton, Jeremy
Sent: January 27, 2022 8:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: FIx for UMR arm build
I know we only technically only care about x86, but this
[AMD Official Use Only]
I know we only technically only care about x86, but this just fixes a syntax
issue if you build on arm.
Remove vega10 from the ras support check function.
Base on this change, the ras initial function is optimized.
Signed-off-by: majun
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 38 +
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git
Thanks, I have splitit.
--Reply to Message--
On Thu, Jan 27, 2022 18:06 PM Daniel Vetterhttp://blog.ffwll.ch
OnThu,Jan27,2022at02:51:56PM+0800,tangmengwrote:
Replacedisbalewithdisableandreplaceunavaibalewithunavailable.
Signed-off-by:tangmeng
On Thu, Jan 27, 2022 at 07:56:05AM +0100, Greg KH wrote:
> On Thu, Jan 27, 2022 at 02:51:56PM +0800, tangmeng wrote:
> > Replace disbale with disable and replace unavaibale with unavailable.
> >
> > Signed-off-by: tangmeng
> > ---
> > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
> >
On Thu, Jan 27, 2022 at 12:25:36PM +0900, Tomohito Esaki wrote:
> Some drivers whose planes only support linear layout fb do not support format
> modifiers.
> These drivers should support modifiers, however the DRM core should handle
> this
> rather than open-coding in every driver.
>
> In this
Am 27.01.22 um 08:52 schrieb Aaron Liu:
The below patch causes system hang for harvested ASICs.
d015e9861e55 drm/amdgpu: improve debug VRAM access performance using sdma
The root cause is that GTT buffer should be allocated after GC SA harvest
programming completed.
That doesn't make much
Replace disbale with disable and replace unavaibale with unavailable.
Signed-off-by: tangmeng
---
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
drivers/pcmcia/rsrc_nonstatic.c | 2 +-
drivers/usb/chipidea/udc.c| 2 +-
4 files
On Thu, Jan 27, 2022 at 02:51:56PM +0800, tangmeng wrote:
> Replace disbale with disable and replace unavaibale with unavailable.
>
> Signed-off-by: tangmeng
> ---
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
> drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
> drivers/pcmcia/rsrc_nonstatic.c
There is a spelling mistake. Fix it.
Signed-off-by: tangmeng
---
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index aef9d059ae52..a642c04cf17d 100644
---
[Why]
External displays take priority over internal display when there are fewer
display controllers than displays.
[How]
The root cause is because of that number of the crtc is not correct.
The number of the crtc on the 3250c is 3, but on the 3500c is 4.
On the source code, we can see that
[Public]
> Should we set *flags = 0 before we return?
That will clear other bit masks. Actually, the caller initialize flags to 0, we
can just return.
Or just *flags &= ~( AMD_CG_SUPPORT_XXX) before we return.
Regards,
Lang
From: Deucher, Alexander
Sent: Thursday, January 27, 2022 4:27 AM
Am 25.01.22 um 19:18 schrieb Tom St Denis:
Newer hardware has a discovery table in hardware that the kernel will
rely on instead of header files for things like IP offsets. This
sysfs entry adds a simple to parse table of IP instances and segment
offsets.
Produces output that looks like:
$
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