Hi Dave, Daniel,
New stuff for 5.19. Mostly new IP block support.
The following changes since commit 3da2c38231a4c62dafdbd762a199cfacaccd0533:
drm/amdgpu: Free user pages if amdgpu_cs_parser_bos failed (2022-04-28
17:49:04 -0400)
are available in the Git repository at:
Alex Sierra writes:
[...]
> diff --git a/mm/rmap.c b/mm/rmap.c
> index fedb82371efe..d57102cd4b43 100644
> --- a/mm/rmap.c
> +++ b/mm/rmap.c
> @@ -1995,7 +1995,8 @@ void try_to_migrate(struct folio *folio, enum ttu_flags
> flags)
> TTU_SYNC)))
>
From: Tim Huang
Add the entry to set the ppt functions for SMU IP v13.0.4.
Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Xiaojian Du
This patch will add SMU v13.0.4 into the IP discovery list.
Signed-off-by: Xiaojian Du
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Tim Huang
Add swsmu ppt files for SMU IP v13.0.4.
Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile |3 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 1044 +
Set the default reset method to mode2 for SMU IP v13.0.4
Signed-off-by: Tim Huang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index
From: Tim Huang
Enable the SMU IP v13.0.4 GFXOFF control
Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
From: Tim Huang
The SMU needs this message to trigger IMU initialization.
Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Tim Huang
Add some common ppt functions that will be used by SMU IP v13.0.x
and drop the not used function smu_v13_0_mode2_reset.
Signed-off-by: Tim Huang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 9 +-
Add initial support for SMU (System Management Unit)
version 13.0.4. The SMU handles power management and
other tasks on the GPU. Patch 1 adds large new header
files so I didn't send them to the list.
Alex Deucher (1):
drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
Huang Rui (1):
From: Jack Xiao
Due to gfxoff on, cpu accessing registers is not expected.
v2: remove bug-on, fix the vmhub check
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 49 +-
1 file changed, 48
From: Jack Xiao
Use the correct Memory Queue Descriptor (MQD)
structure for GC 11.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff
From: Jack Xiao
Select the correct microengine (me) when using the
map_queue packet. There are different me's for GFX,
compute, and scheduling.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 7 +--
1 file
"Sierra Guiza, Alejandro (Alex)" writes:
> @apop...@nvidia.com Could you please check this patch? It's somehow related
> to migrate_device_page() for long term device coherent pages.
>
> Regards,
> Alex Sierra
>> -Original Message-
>> From: amd-gfx On Behalf Of Alex
>> Sierra
>>
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466
Marek
On Fri, May 6, 2022 at 9:35 AM Alex Deucher wrote:
> On Fri, May 6, 2022 at 7:23 AM Christian König
> wrote:
> >
> > Increase the minor version number to indicate that the new flags are
> > avaiable.
>
> typo: available.
On 2022-05-11 05:44, Lang Yu wrote:
MMIO/DOORBELL BOs' backing resources(bus address resources that are
used to talk to the GPU) are not managed by GTT manager, but they
are counted by GTT manager. That makes no sense.
With AMDGPU_GEM_CREATE_PREEMPTIBLE flag, such BOs will be managed by
PREEMPT
3rd question: Is it worth using this on APUs?
Thanks,
Marek
On Wed, May 11, 2022 at 5:58 PM Marek Olšák wrote:
> Will the kernel keep all discardable buffers in VRAM if VRAM is not
> overcommitted by discardable buffers, or will other buffers also affect the
> placement of discardable buffers?
Will the kernel keep all discardable buffers in VRAM if VRAM is not
overcommitted by discardable buffers, or will other buffers also affect the
placement of discardable buffers?
Do evictions deallocate the buffer, or do they keep an allocation in GTT
and only the copy is skipped?
Thanks,
Marek
On 2022-05-11 11:39, Christian König wrote:
Am 11.05.22 um 17:35 schrieb Andrey Grodzovsky:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um
On Thu, May 05, 2022 at 04:34:36PM -0500, Alex Sierra wrote:
> diff --git a/mm/memory.c b/mm/memory.c
> index 76e3af9639d9..892c4cc54dc2 100644
> +++ b/mm/memory.c
> @@ -621,6 +621,13 @@ struct page *vm_normal_page(struct vm_area_struct *vma,
> unsigned long addr,
> if
Ok sounds good.
Marek
On Wed., May 11, 2022, 03:43 Christian König, <
ckoenig.leichtzumer...@gmail.com> wrote:
> It really *is* a NOALLOC feature. In other words there is no latency
> improvement on reads because the cache is always checked, even with the
> noalloc flag set.
>
> The only thing
On Wed, May 11, 2022 at 2:20 PM Lyude Paul wrote:
>
> Many DRM drivers feature a 'modeset' argument, which can be used to
> enable/disable the entire driver (as opposed to passing nomodeset to the
> kernel, which would disable modesetting globally and make it difficult to
> load amdgpu
Many DRM drivers feature a 'modeset' argument, which can be used to
enable/disable the entire driver (as opposed to passing nomodeset to the
kernel, which would disable modesetting globally and make it difficult to
load amdgpu afterwards). Apparently amdgpu is actually missing this
however, so
Hi Dave, Daniel,
Fixes for 5.18.
The following changes since commit 5727375215b0915f28806c337a7ba9835efd340b:
Merge tag 'drm-msm-fixes-2022-04-30' of
https://gitlab.freedesktop.org/drm/msm into drm-fixes (2022-05-06 11:22:03
+1000)
are available in the Git repository at:
On 2022-05-11 12:49, Felix Kuehling wrote:
Am 2022-05-11 um 09:49 schrieb Andrey Grodzovsky:
[snip]
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f1a225a20719..4b789bec9670 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++
Am 2022-05-11 um 09:49 schrieb Andrey Grodzovsky:
[snip]
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index f1a225a20719..4b789bec9670 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@
On 2022-05-11 11:39, Christian König wrote:
Am 11.05.22 um 17:35 schrieb Andrey Grodzovsky:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um
On 2022-05-11 11:46, Lazar, Lijo wrote:
On 5/11/2022 9:13 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:37, Lazar, Lijo wrote:
On 5/11/2022 9:05 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43
On 5/11/2022 9:13 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:37, Lazar, Lijo wrote:
On 5/11/2022 9:05 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11
On 2022-05-11 11:37, Lazar, Lijo wrote:
On 5/11/2022 9:05 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53
Am 11.05.22 um 17:35 schrieb Andrey Grodzovsky:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
[SNIP]
E.g. in
On 5/11/2022 9:05 PM, Andrey Grodzovsky wrote:
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
[SNIP]
E.g.
On Tue, May 10, 2022 at 4:45 PM David Zhang wrote:
>
> changes in v2:
> ---
> - set vsc_packet_rev2 for PSR1 which is safer
> - add exposure of AMD specific DPCD regs for PSR-SU-RC (rate-control)
> - add DC/DM change related to amdgpu PSR-SU-RC
>
>
> David Zhang (18):
>
On 2022-05-11 11:20, Lazar, Lijo wrote:
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
[SNIP]
E.g. in the reset code (either before or after the
I've applied it with the change to the commit message. Sorry for the confusion.
Alex
On Wed, May 11, 2022 at 12:05 AM Haohui Mai wrote:
>
> It should be an identical patch except for the commit message. Do you
> want me to send out a new one? Either way is fine with me.
>
> ~Haohui
>
> On Tue,
On Mon, May 09, 2022 at 05:01:33PM +0200, Christian König wrote:
> Am 09.05.22 um 16:31 schrieb Daniel Vetter:
> > On Wed, May 04, 2022 at 09:47:32AM +0200, Christian König wrote:
> > > [SNIP]
> > > +/* Make sure we have enough room and add an object the container */
> > > +static int
On 5/11/2022 7:28 PM, Christian König wrote:
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
[SNIP]
E.g. in the reset code (either before or after the reset, that's
debatable) you do something like
Am 11.05.22 um 15:43 schrieb Andrey Grodzovsky:
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
[SNIP]
E.g. in the reset code (either before or after the reset, that's
debatable) you do something like this:
for (i = 0; i < num_ring; ++i)
On 2022-05-11 03:38, Christian König wrote:
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
On 2022-05-10 13:19, Christian König wrote:
Am 10.05.22 um 19:01 schrieb Andrey Grodzovsky:
On 2022-05-10 12:17, Christian König wrote:
Am 10.05.22 um 18:00 schrieb Andrey Grodzovsky:
[SNIP]
create smartshift sysfs attributes from dGPU device even
on smartshift 1.0 platform to be consistent. Do not populate
the attributes on platforms that have APU only but not dGPU
or vice versa.
Suggested-by: Alex Deucher
Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
---
On 5/11/2022 5:27 PM, Lazar, Lijo wrote:
On 5/11/2022 5:16 PM, Sathishkumar S wrote:
smartshift apu and dgpu power boost are reported as percentage
with respect to their power limits. adjust the units of power before
calculating the percentage of boost.
Signed-off-by: Sathishkumar S
---
This is enough to get gputop working :)
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
index
Convert fdinfo format to one documented in drm-usage-stats.rst.
It turned out that the existing implementation was actually completely
nonsense. The calculated percentages indeed represented the usage of the
engine, but with varying time slices.
So 10% usage for application A could mean
Am 11.05.22 um 11:05 schrieb Mikhail Gavrilov:
On Fri, Apr 15, 2022 at 1:04 PM Christian König
wrote:
No, I just couldn't find time during all that bug fixing :)
Sorry for the delay, going to take a look after the eastern holiday here.
Christian.
The message is just for history. The issue
On 5/11/2022 4:27 PM, Sathishkumar S wrote:
smartshift apu and dgpu power boost are reported as percentage with
respect to their power limits. This value[0-100] reflects the boost
for the respective device.
Signed-off-by: Sathishkumar S
Reviewed-by: Lijo Lazar
Thanks,
Lijo
---
On 5/11/2022 5:16 PM, Sathishkumar S wrote:
smartshift apu and dgpu power boost are reported as percentage
with respect to their power limits. adjust the units of power before
calculating the percentage of boost.
Signed-off-by: Sathishkumar S
---
smartshift apu and dgpu power boost are reported as percentage
with respect to their power limits. adjust the units of power before
calculating the percentage of boost.
Signed-off-by: Sathishkumar S
---
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 60 ++-
1 file changed, 44
smartshift apu and dgpu power boost are reported as percentage with
respect to their power limits. This value[0-100] reflects the boost
for the respective device.
Signed-off-by: Sathishkumar S
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 60 ++-
1 file changed, 44
MMIO/DOORBELL BOs' backing resources(bus address resources that are
used to talk to the GPU) are not managed by GTT manager, but they
are counted by GTT manager. That makes no sense.
With AMDGPU_GEM_CREATE_PREEMPTIBLE flag, such BOs will be managed by
PREEMPT manager(for preemptible contexts,
On 5/11/2022 2:18 PM, Sathishkumar S wrote:
always create smartshift attributes from dgpu device even on SS1.0.
consider units of power in metrics table and convert if necessary.
powershift value is in percentage and values to range between 0-100.
Suggested-by: Alex Deucher
Signed-off-by:
On Fri, Apr 15, 2022 at 1:04 PM Christian König
wrote:
>
> No, I just couldn't find time during all that bug fixing :)
>
> Sorry for the delay, going to take a look after the eastern holiday here.
>
> Christian.
The message is just for history. The issue was fixed between
b253435746d9a4a and
Am 11.05.22 um 10:04 schrieb Tvrtko Ursulin:
On 10/05/2022 17:55, Christian König wrote:
From: Tvrtko Ursulin
Feels like you should take over owenrship since you wrote a lot of
new, amdgpu specific code here.
Yeah, probably.
Convert fdinfo format to one documented in
always create smartshift attributes from dgpu device even on SS1.0.
consider units of power in metrics table and convert if necessary.
powershift value is in percentage and values to range between 0-100.
Suggested-by: Alex Deucher
Signed-off-by: Sathishkumar S
Acked-by: Alex Deucher
---
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable (Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo)
v5: remove
[AMD Official Use Only - General]
Series is Reviewed-by: Kenneth Feng
mailto:kenneth.f...@amd.com>>
Best wishes
Kenneth Feng
发件人: amd-gfx 代表 Yang Wang
日期: 星期三, 2022年5月11日 13:09
收件人: amd-gfx@lists.freedesktop.org
抄送: Wang, Yang(Kevin)
主题: [PATCH 1/2] drm/amd/pm: add smu feature map
[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>
Best wishes
Kenneth Feng
发件人: amd-gfx 代表 Yang Wang
日期: 星期三, 2022年5月11日 15:01
收件人: amd-gfx@lists.freedesktop.org
抄送: Wang, Yang(Kevin)
主题: [PATCH] drm/amd/pm: add smu power_limit callback for
On 5/11/2022 1:14 PM, Lazar, Lijo wrote:
On 5/11/2022 12:51 PM, Sathishkumar S wrote:
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable
(Lijo)
v3: avoid calculations that result in -ve values and skip
On 10/05/2022 17:55, Christian König wrote:
This is enough to get gputop working :)
Super cool! So I guess it's time for me to cleanup that code base a bit.
Regards,
Tvrtko
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 7 +++
1 file changed, 3
On 10/05/2022 17:55, Christian König wrote:
From: Tvrtko Ursulin
Feels like you should take over owenrship since you wrote a lot of new,
amdgpu specific code here.
Convert fdinfo format to one documented in drm-usage-stats.rst.
It turned out that the existing implementation was
On 5/11/2022 12:51 PM, Sathishkumar S wrote:
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable (Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit
It really *is* a NOALLOC feature. In other words there is no latency
improvement on reads because the cache is always checked, even with the
noalloc flag set.
The only thing it affects is that misses not enter the cache and so
don't cause any additional pressure on evicting cache lines.
You
Am 10.05.22 um 20:53 schrieb Andrey Grodzovsky:
On 2022-05-10 13:19, Christian König wrote:
Am 10.05.22 um 19:01 schrieb Andrey Grodzovsky:
On 2022-05-10 12:17, Christian König wrote:
Am 10.05.22 um 18:00 schrieb Andrey Grodzovsky:
[SNIP]
That's one of the reasons why we should have
Bypass means that the contents of the cache are ignored, which decreases
latency at the cost of no coherency between bypassed and normal memory
requests. NOA (noalloc) means that the cache is checked and can give you
cache hits, but misses are not cached and the overall latency is higher. I
don't
support reading smartshift apu and dgpu power for smu11 based asic
v2: add new version of SmuMetrics and make calculation more readable (Lijo)
v3: avoid calculations that result in -ve values and skip related checks
v4: use the current power limit on dGPU and exclude smu 11_0_7 (Lijo)
Ok, since I don't get any objects I'm pushing this patch to
drm-misc-next now.
Regards,
Christian.
Am 09.05.22 um 09:48 schrieb Christian König:
Harry, Nicholas once more a gentle ping on this.
Any objections/comments? Otherwise I'm going to push this through
drm-misc-next.
Thanks,
OK that sounds good.
Marek
On Wed, May 11, 2022 at 2:04 AM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:
> Hi Marek,
>
> Am 10.05.22 um 22:43 schrieb Marek Olšák:
>
> A better flag name would be:
> AMDGPU_GEM_CREATE_BEST_PLACEMENT_OR_DISCARD
>
>
> A bit long for my taste and I
- get_power_limit
- set_power_limit
add above callback functions to enable power_cap hwmon node.
Signed-off-by: Yang Wang
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 39 +++
1 file changed, 39 insertions(+)
diff --git
On 5/11/2022 11:36 AM, Christian König wrote:
Mhm, it doesn't really bypass MALL. It just doesn't allocate any MALL
entries on write.
How about AMDGPU_VM_PAGE_NO_MALL ?
One more - AMDGPU_VM_PAGE_LLC_* [ LLC = last level cache, * = some sort
of attribute which decides LLC behaviour]
Mhm, it doesn't really bypass MALL. It just doesn't allocate any MALL
entries on write.
How about AMDGPU_VM_PAGE_NO_MALL ?
Christian.
Am 10.05.22 um 23:21 schrieb Marek Olšák:
A better name would be:
AMDGPU_VM_PAGE_BYPASS_MALL
Marek
On Fri, May 6, 2022 at 7:23 AM Christian König
wrote:
Hi Marek,
Am 10.05.22 um 22:43 schrieb Marek Olšák:
A better flag name would be:
AMDGPU_GEM_CREATE_BEST_PLACEMENT_OR_DISCARD
A bit long for my taste and I think the best placement is just a side
effect.
Marek
On Tue, May 10, 2022 at 4:13 PM Marek Olšák wrote:
Does this really
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