[+amd-gfx]
On 2022-06-03 15:37, Felix Kuehling wrote:
On 2022-06-03 06:46, Christian König wrote:
Resources about to be destructed are not tied to BOs any more.
I've been seeing a backtrace in that area with a patch series I'm
working on, but didn't have enough time to track it down yet.
On 2022-06-03 06:52, Ramesh Errabolu wrote:
Extend current kernel config requirements of amdgpu by adding config
HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer
communication between AMD GPU devices over PCIe bus
Signed-off-by: Ramesh Errabolu
This patch is
On 2022-06-03 06:52, Ramesh Errabolu wrote:
Extend KFD device topology to surface peer-to-peer links among
GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is
REQUIRED to surface peer-to-peer links.
Prior to this KFD did not expose to user mode any P2P links or
indirect links
On 2022-06-03 06:52, Ramesh Errabolu wrote:
Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
From: Aric Cyr
This version brings along the following:
- DPP DTO fix
- Transient encoder fix
- Restrict the reading of LTTPR capabilities in LTTPR mode
- Increase maximum stages for BB
- Distinguish HDMI DTO from DP DTO
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
---
From: Chris Park
[Why]
For Pixel Rate control, when on HDMI, HDMI DTO
should be selected instead of DP DTO.
[How]
Add HDMI member to dtbclk_dto_params, so it can be used tell apart HDMI
and DP DTO in the future.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Chris Park
---
From: Jimmy Kizito
[Why]
LTTPR capable devices on the DisplayPort path may assume that
extended LTTPR AUX timeouts will be used after LTTPR capabilities
are read.
When DPTX operates in non-LTTPR mode, AUX timeouts are not
extended and this can result in AUX transactions timing out.
[How]
Use
From: "Lei, Jun"
[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).
[how]
Change maximum stages from 9 to 20.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Jun Lei
---
drivers/gpu/drm/amd/display/dc/dc.h
From: Duncan Ma
[Why]
When switching from 1 pipe to 4to1 mpc combine,
DppDtoClk aren't enabled for the disabled pipes
pior to programming the pipes. Upon optimizing
bandwidth, DppDto are enabled causing intermittent
underflow.
[How]
Update dppclk dto whenever pipe are flagged to
enable.
From: Jimmy Kizito
[Why]
In some scenarios it is possible for the encoder assignment module to be
set to "transient" mode even though there are no new encoder
assignments.
This can lead to incorrect results when querying encoder assignment,
which in turn can cause incorrect displays to be
From: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Hamza Mahfooz
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
From: Aric Cyr
This version brings along the following:
- Optimized blank calculations
- More robust DP MST hotplug support
- eDP bug fix relating to ODM
- Revert a patch that caused a regression with DP
- min comp buffer size fix
- Make DP easier to debug
- Calculate the maximum OLED brightness
From: Hansen Dsouza
[why and how]
3 plane MPO is a new feature missing in a few resource files
Enable 3 plane MPO by setting slave planes to 2
Reviewed-by: Krunoslav Kovac
Reviewed-by: Aric Cyr
Acked-by: Hamza Mahfooz
Signed-off-by: Hansen Dsouza
---
From: Wenjing Liu
[why]
1. When HPD deassertion is pulled in the middle of
enabe stream link training, we will abort current training
and turn off PHY. This causes current link settings
to be zeroed this causes later stream enablement
sequence to fail as we prefer to carry on enablement
process
From: Duncan Ma
[Why]
In 3-way mpo pipes, there is a case that we
overbook the CRB buffer size. At rare instances,
overbooking the crb will cause underflow. This only
happens when det_size changes dynamically
based on pipe_cnt.
[How]
Set min compbuff size to 1 segment when preparing BW.
From: Roman Li
[Why]
For OLED eDP the Display Manager uses max_cll value as a limit
for brightness control.
max_cll defines the content light luminance for individual pixel.
Whereas max_fall defines frame-average level luminance.
The user may not observe the difference in brightness in between
From: Duncan Ma
[Why]
For panels with pixel clock > 1200MHz that require ODM
in pre-OS, when driver is disabled in OS, odm is enabled.
Upon driver enablement, corruption is seen if
odm was originally enabled. DP_PIXEL_COMBINE and
pixelclk must be programmed prior to programming the
optc-odm
From: Wayne Lin
[Why]
Once mst topology is constructed, later on new connected monitors
are reported to source by CSN message. Within CSN, there is no
carried info of DPCD_REV comparing to LINK_ADDRESS reply. As the
result, we might leave some ports connected to DP but without DPCD
revision
From: Nicholas Kazlauskas
This reverts commit 25b1b4128c75bc9b9cf033425427d085f97439ec.
Causes a hang when hotplugging DP, shutting down system, or
enabling dual eDP.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Hamza Mahfooz
Signed-off-by: Nicholas Kazlauskas
---
From: Gabe Teeger
[Why]
The existing calculations in DCN3.1 were placeholder and need to be
replaced with HW team approved calculations.
[How]
The new calculations add new parameters to the bounding box and pipe
params - VblankNom and the bounding box default.
The placeholder calculations are
* DPP DTO fix
* Transient encoder fix
* Restrict the reading of LTTPR capabilities in LTTPR mode
* Increase maximum stages for BB
On Fri, Jun 3, 2022 at 2:51 PM Rodrigo Siqueira
wrote:
>
> It looks like that we have some new warnings on display code and a
> compilation error when using allmodconfig. This series clean up some of
> the DML warnings and fix the compilation problem with allmodeconfig.
>
> Thanks
>
> Rodrigo
This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
This commit introduced the below compilation error when using
allmodconfig:
error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did
you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
GCC throw warnings for the function dcn21_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:
error: the frame size of 1936 bytes is larger than 1024 bytes
[-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
GCC throw warnings for the function dcn31_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:
error: the frame size of 1936 bytes is larger than 1024 bytes
[-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
GCC throw warnings for the function dcn20_update_bounding_box due to its
frame size that looks like this:
error: the frame size of 1936 bytes is larger than 1024 bytes
[-Werror=frame-larger-than=]
This commit fixes this issue by eliminating an intermediary variable
that creates a large array.
GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box
due to its frame size that looks like this:
error: the frame size of 1936 bytes is larger than 1024 bytes
[-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
Cc: Stephen Rothwell
Cc:
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 11391eead954..a0dffe30b394 100644
---
It looks like that we have some new warnings on display code and a
compilation error when using allmodconfig. This series clean up some of
the DML warnings and fix the compilation problem with allmodeconfig.
Thanks
Rodrigo Siqueira (6):
drm/amd/display: Remove duplicated macro
Removed an unused parameter from two functions and added kernel-doc
comments.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 7 ++---
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 28 ---
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 5
On Fri, Jun 03, 2022 at 11:49:31AM -0400, Alex Deucher wrote:
> On Thu, Jun 2, 2022 at 10:22 AM Michal Kubecek wrote:
> >
> > On Thu, Jun 02, 2022 at 09:58:22AM -0400, Alex Deucher wrote:
> > > On Fri, May 27, 2022 at 8:58 AM Michal Kubecek wrote:
> > > > On Fri, May 27, 2022 at 11:00:39AM
On 2022-06-03 12:32, sunpeng...@amd.com wrote:
> From: David Zhang
>
> [Why]
>
> In cases where there are multiple eDP instances, DMUB needs to know
> which instance the command is for. Today, the field for specifying the
> panel_inst exists in both dmub_cmd_update_dirty_rect_data and
>
From: David Zhang
[Why]
In cases where there are multiple eDP instances, DMUB needs to know
which instance the command is for. Today, the field for specifying the
panel_inst exists in both dmub_cmd_update_dirty_rect_data and
dmub_cmd_update_cursor_info_data.
For cursor updates, we already
On Thu, Jun 2, 2022 at 10:22 AM Michal Kubecek wrote:
>
> On Thu, Jun 02, 2022 at 09:58:22AM -0400, Alex Deucher wrote:
> > On Fri, May 27, 2022 at 8:58 AM Michal Kubecek wrote:
> > > On Fri, May 27, 2022 at 11:00:39AM +0200, Michal Kubecek wrote:
> > > > Hello,
> > > >
> > > > while testing
A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
A: No.
Q: Should I
On 2022-06-02 16:48, Harry Wentland wrote:
>
>
> On 2022-06-02 14:03, sunpeng...@amd.com wrote:
>> From: David Zhang
>>
>> [why]
>> DMUB FW uses OTG instance to get eDP panel instance. But in case
>> of MPO multiple pipe indexes are passed to updated the same panel.
>> The other OTG
Am 2022-06-03 um 09:59 schrieb Philip Yang:
Migration range from system memory to VRAM, if system page can not be
locked or unmapped, we do partial migration and leave some pages in
system memory. Several bugs found to copy pages and update GPU mapping
for this situation:
1. copy to vram should
Do the other uvd/vce/vcn ring parse functions need a similar fix?
Alex
On Fri, Jun 3, 2022 at 10:08 AM Alex Deucher wrote:
>
> On Fri, Jun 3, 2022 at 8:10 AM Christian König
> wrote:
> >
> > Am 03.06.22 um 14:08 schrieb Pierre-Eric Pelloux-Prayer:
> > > Hi Christian,
> > >
> > > The patch is:
On Fri, Jun 3, 2022 at 8:10 AM Christian König
wrote:
>
> Am 03.06.22 um 14:08 schrieb Pierre-Eric Pelloux-Prayer:
> > Hi Christian,
> >
> > The patch is: Tested-by: Pierre-Eric Pelloux-Prayer
> >
> >
> > Could you add a reference to
> > https://gitlab.freedesktop.org/drm/amd/-/issues/2037 in
Migration range from system memory to VRAM, if system page can not be
locked or unmapped, we do partial migration and leave some pages in
system memory. Several bugs found to copy pages and update GPU mapping
for this situation:
1. copy to vram should use migrate->npage which is total pages of
Hi Christian,
This patch fixes almost all GPU faults on polaris caused by 86fd5edfbdae
"drm/amdgpu: rework TLB flushing".
I still get occasional faults though, about 1 every 3 runs of a subset of
piglit tests.
Thanks,
Pierre-Eric
On 03/06/2022 15:05, Christian König wrote:
> The TLB on
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Reviewed-by: Shashank Sharma for both the patches.
Regards
Shashank
-Original Message-
From: Somalapuram, Amaranath
Sent: Thursday, June 2, 2022 10:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Deucher, Alexander
; Sharma, Shashank ;
Somalapuram, Amaranath
Am 03.06.22 um 14:08 schrieb Pierre-Eric Pelloux-Prayer:
Hi Christian,
The patch is: Tested-by: Pierre-Eric Pelloux-Prayer
Could you add a reference to
https://gitlab.freedesktop.org/drm/amd/-/issues/2037 in the commit message?
Sure, can you also give me an rb or acked-by so that I can
Hi Christian,
The patch is: Tested-by: Pierre-Eric Pelloux-Prayer
Could you add a reference to
https://gitlab.freedesktop.org/drm/amd/-/issues/2037 in the commit message?
Thanks,
Pierre-Eric
On 03/06/2022 12:21, Christian König wrote:
> The job is not yet initialized here.
>
>
Extend KFD device topology to surface peer-to-peer links among
GPU devices connected over PCIe or xGMI. Enabling HSA_AMD_P2P is
REQUIRED to surface peer-to-peer links.
Prior to this KFD did not expose to user mode any P2P links or
indirect links that go over two or more direct hops. Old versions
Add support for peer-to-peer communication among AMD GPUs over PCIe
bus. Support REQUIRES enablement of config HSA_AMD_P2P.
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 312 ++
Extend current kernel config requirements of amdgpu by adding config
HSA_AMD_P2P. Enabling HSA_AMD_P2P is REQUIRED to support peer-to-peer
communication between AMD GPU devices over PCIe bus
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdkfd/Kconfig | 14 ++
1 file
[AMD Official Use Only - General]
Applied review comments and updated commit message as suggested. Some responses
are inline.
Regards,
Ramesh
-Original Message-
From: Kuehling, Felix
Sent: Wednesday, June 1, 2022 10:10 PM
To: Errabolu, Ramesh ; amd-gfx@lists.freedesktop.org
Subject:
[AMD Official Use Only - General]
Applied review comments. Please find responses inline
Regards,
Ramesh
-Original Message-
From: Kuehling, Felix
Sent: Wednesday, June 1, 2022 9:42 PM
To: Errabolu, Ramesh ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/amdgpu: Add
[AMD Official Use Only - General]
Update the both the description and commit message per review comments.
Will post new patch shortly.
Regards,
Ramesh
-Original Message-
From: Kuehling, Felix
Sent: Wednesday, June 1, 2022 9:15 PM
To: Errabolu, Ramesh ; amd-gfx@lists.freedesktop.org
The job is not yet initialized here.
Signed-off-by: Christian König
Fixes: 1027d5d791b7 ("drm/amdgpu: use job and ib structures directly in CS
parsers")
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git
Hi Lyude,
Thank you for the reviews.
On 5/18/22 19:39, Lyude Paul wrote:
> On Tue, 2022-05-17 at 17:23 +0200, Hans de Goede wrote:
>> Typically the acpi_video driver will initialize before nouveau, which
>> used to cause /sys/class/backlight/acpi_video0 to get registered and then
>> nouveau
54 matches
Mail list logo
