On 2022-11-25 05:21, Christian König wrote:
We already fallback to a dummy BO with no backing store when we
allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
Drop all those workarounds and generalize this for GTT as well. This
fixes ENOMEM issues with runaway applications
Applied. Thanks!
Alex
On Fri, Dec 9, 2022 at 3:24 AM Paulo Miguel Almeida
wrote:
>
> One-element arrays are deprecated, and we are replacing them with
> flexible array members instead. So, replace one-element array with
> flexible-array member in structs _ATOM_DISPLAY_OBJECT_PATH,
>
Fixed
Regards,
Jasdeel
From: Alex Deucher
Sent: December 9, 2022 4:37 PM
To: Dhillon, Jasdeep
Cc: amd-gfx@lists.freedesktop.org ; Wang,
Chao-kai (Stylon) ; Li, Sun peng (Leo)
; Wentland, Harry ; Zhuo, Qingqing
(Lillian) ; Siqueira, Rodrigo
; Li, Roman ;
This patch has been dropped
Regards,
Jasdeep
From: Alex Deucher
Sent: December 9, 2022 4:32 PM
To: Dhillon, Jasdeep
Cc: amd-gfx@lists.freedesktop.org ; Wang,
Chao-kai (Stylon) ; Li, Sun peng (Leo)
; Wentland, Harry ; Zhuo, Qingqing
(Lillian) ; Siqueira,
The missing DPCD defintions from DP2.0 spec is as follows:
DOWNSPREAD_CTRL (107h):
FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (bit 6)
For sink devices that support Adaptive-Sync operation
and Panel Replay
DPRX_FEATURE_ENUMERATION_LIST_CONT_1 (2214h):
On Thu, Dec 8, 2022 at 10:49 PM Evan Quan wrote:
>
> Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock.
> And update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock.
> User applications can better utilize these IOCTLs to get needed informations.
>
> Increase
The commit subject is very generic. A better one might be
"Add missing Adaptive Sync DPCD definitions"
On 12/8/22 14:25, Sung Joon Kim wrote:
> The missing DPCD defintions from DP2.0 spec is as follows:
>
> DOWNSPREAD_CTRL (107h):
> ADAPTIVE_SYNC_SDP_EN (bit 6)
> For sink
On Fri, Dec 9, 2022 at 11:38 AM jdhillon wrote:
>
> From: Samson Tam
>
> [Why]
> When we have a PSR display, we will not be requesting data from memory
> anymore.
> So we report back true for no memory request case.
>
> [How]
> Check for PSR by checking PSR version in link settings
>
>
On Fri, Dec 9, 2022 at 11:37 AM jdhillon wrote:
>
> From: hersen wu
>
> [Why]
> multiple display hdcp are enabled within event_property_validate,
> event_property_update by looping all displays on mst hub. when
> one of display on mst hub in unplugged or disabled, hdcp are
> disabled for all
From: hersen wu
[why]
For MST topology with 1 physical link and multiple connectors (>=2),
e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace
set to enable the HDCP simultaneously on all connected outputs, the
commit tail iteratively call the hdcp_update_display() for each
display
From: Aric Cyr
This version brings along following fixes:
-Fix array index out of bound error
-Speed up DML fast vadlaite
-Implement multiple secure display
-MST HDCP for multiple display
-Add DPIA notification
-Add support for three new square pattern variant
Reviewed-by: Bhawanpreet Lakha
From: Dillon Varone
[Description]
Modify soc BB to reduce expected sdp bandwidth and align with measurements to
fix underflow issues.
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 2 +-
1 file
From: Samson Tam
[Why]
When we have a PSR display, we will not be requesting data from memory anymore.
So we report back true for no memory request case.
[How]
Check for PSR by checking PSR version in link settings
Reviewed-by: Alvin Lee
Acked-by: Jasdeep Dhillon
Signed-off-by: Samson Tam
From: Mustapha Ghaddar
[WHY]
Adding the new DPIA NOTIFY packets from DMUB
As per the design with Cruise to account for
250ms response delay otherwise
[HOW]
Added th DPIA NOTIFY logic as per DMUB logic
Reviewed-by: Nicholas Kazlauskas
Acked-by: Jasdeep Dhillon
Signed-off-by: Mustapha Ghaddar
From: "Leo (Hanghong) Ma"
This reverts commit b1a3d467a069519fd8aed711fff94c49e486e701.
Workaround no longer needed.
Reviewed-by: Chris Park
Reviewed-by: Chris Park
Acked-by: Jasdeep Dhillon
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 1 -
1
From: Roman Li
[Why]
In case of failure to resume MST topology after suspend, an emtpty
mst tree prevents further mst hub detection on the same connector.
That causes the issue with MST hub hotplug after it's been unplug in
suspend.
[How]
Stop topology manager on the connector after detecting
From: Wenjing Liu
[why]
in dc_link_dp there still exist a few places where we call dio encoders
without checking current enabled encoder type.
The change is to make these places to call hwss equivalent functions so
it won't mistakenly program a wrong type encoder.
Reviewed-by: George Shen
From: Ian Chen
[WHY]
It causes regression AMD source will not write DPCD 340.
Reviewed-by: Wayne Lin
Acked-by: Jasdeep Dhillon
Signed-off-by: Ian Chen
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 6 --
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 14 +++---
From: Alan Liu
[Why]
Fix problems when we disable secure_display.
[How]
- Reset secure display context after disabled
- A secure_display_context is dedicate to a crtc, so we set the crtc for
it when we create the context.
Reviewed-by: Wayne Lin
Acked-by: Jasdeep Dhillon
Signed-off-by: Alan
From: Wenjing Liu
[why]
DP2.1 specs has brought 3 new variants of sqaure patterns with different
pre-shoot and de-emphasis equalization requirements. The commit adds
logic to identify these variants and apply corresponding eqaulization
requirements into hardware lane settings.
Reviewed-by:
From: Alvin Lee
[Description]
- Current policy does not support HDMI VRR by default, so we
cannot enable FPO / SubVP (DRR) cases
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c|
From: Alvin Lee
[Description]
- FW scheduling algorithm doesn't take into account of it's
a center timing
- This affects where the subvp mclk switch can be scheduled
(prevents HUBP vline interrupt from coming in if scheduled
incorrectly)
- Block subvp center timing cases for now
From: Roman Li
[Why]
Fixing smatch error:
dm_resume() error: we previously assumed 'aconnector->dc_link' could be null
[How]
Check if dc_link null at the beginning of the loop,
so further checks can be dropped.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Reviewed-by: Wayne Lin
From: Fangzhi Zuo
[Why && How]
On dcn32, HW supports odm transition in fast update. Hence this
error message is considered false positive. Downgrade the error level
to avoid catching unnecessary attention.
Reviewed-by: Dillon Varone
Acked-by: Jasdeep Dhillon
Signed-off-by: Fangzhi Zuo
---
From: hersen wu
[Why]
connector hdcp properties are lost after display is
unplgged from mst hub. connector is destroyed with
dm_dp_mst_connector_destroy. when display is plugged
back, hdcp is not desired, hdcp could not be enabled
by linux kernel automatically.
[How]
save hdcp properties into
From: hersen wu
[Why]
multiple display hdcp are enabled within event_property_validate,
event_property_update by looping all displays on mst hub. when
one of display on mst hub in unplugged or disabled, hdcp are
disabled for all displays on mst hub within hdcp_reset_display
by looping all
From: Alvin Lee
[Description]
- When merging a pipe that was previously pipe split, we need
to also clear the link resources or the next stream/plane that
uses the pipe may have an incorrect link resource state
Reviewed-by: Wenjing Liu
Reviewed-by: Nevenko Stupar
Acked-by: Jasdeep Dhillon
From: Dillon Varone
[WHY]
Subvp portion validation currently assumes that if vlevel provided does not
support pstate, then none will, and so subvp is not used.
[HOW]
After get vlevel, use lowest vlevel that supports pstate if it
exists, and use that for subvp validation.
Reviewed-by: Alvin Lee
From: Hamza Mahfooz
If we build the kernel without CONFIG_DRM_AMD_SECURE_DISPLAY set, we get
the following compile warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.c: In function
‘amdgpu_dm_crtc_configure_crc_source’:
From: Alan Liu
[Why]
Current secure display only work with single display, now make it
work with multiple displays.
[How]
Create secure_display_context for each crtc instance to store its
own Region of Interest (ROI) information.
Reviewed-by: Wayne Lin
Acked-by: Jasdeep Dhillon
From: Ilya Bakoulin
[Why]
Iterating over every voltage state when we need to validate thousands of
configurations all at once (i.e. display hotplug) can take a significant
amount of time.
[How]
Check just the highest voltage state when fast_validate is true to
verify whether the configuration
From: Dillon Varone
[Description]
Add debug bit to disable unbounded requesting.
Reviewed-by: Jun Lei
Acked-by: Jasdeep Dhillon
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fix array index out of bound error
* Speed up DML fast vadlaite
* Implement multiple secure display
* MST HDCP for multiple display
* Add DPIA notification
* Add support for three new square pattern variant
Please try the latest AMDGPU driver:
https://gitlab.freedesktop.org/agd5f/linux/-/commits/amd-staging-drm-next/
On 2022-12-07 15:54, Alex Deucher wrote:
+ Leo, Thong
On Wed, Dec 7, 2022 at 3:43 PM Mikhail Gavrilov
wrote:
On Wed, Dec 7, 2022 at 7:58 PM Alex Deucher wrote:
What GPU do you
One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in structs _ATOM_DISPLAY_OBJECT_PATH,
_ATOM_DISPLAY_OBJECT_PATH_TABLE, _ATOM_OBJECT_TABLE, GOP_VBIOS_CONTENT
_ATOM_GPIO_VOLTAGE_OBJECT_V3 and
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