[Why]
SDMA0_CNTL and MMHUB system aperture related registers are blocked by L1 Policy.
Therefore, they cannot be accessed by VF and loged in violation.
[How]
For MMHUB registers, they will be programmed by PF. So VF will skip to program
them in mmhubv3_0.
For SDMA0_CNTL which is a PF_only
Remove page shift operations as ttm_resource moved
from num_pages to size_t size in bytes.
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/i915/i915_scatterlist.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c
Remove page shift operations as ttm_resource moved
from num_pages to size_t size in bytes.
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 12 ++--
2 files changed, 7 insertions(+), 9
Remove page shift operations as ttm_resource moved
from num_pages to size_t size in bytes.
v1 -> v2: fix missing page shift to fpfn and lpfn
v2 -> v3: separate patch’s based on driver module
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/ttm/ttm_range_manager.c | 13 ++---
1
ttm_resource allocate size in bytes to support less than page size
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/drm_gem.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 59a0bb5ebd85..ee8b5c2b6c60 100644
---
Am 2023-01-10 um 17:41 schrieb Philip Yang:
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used definition type to int64_t to be able to
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: January 10, 2023 5:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu/vcn4: add missing encoder cap
VCN4.x supports AV1
The YCC conversion matrix for RGB -> COLOR_SPACE_YCBCR2020_TYPE is
missing the values for the fourth column of the matrix.
The fourth column of the matrix is essentially just a value that is
added given that the color is 3 components in size.
These values are needed to bias the chroma from the
VCN4.x supports AV1 encode.
Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used definition type to int64_t to be able to trigger
WARN_ONCE(adev && adev->kfd.vram_used < 0,
On 2023-01-10 15:49, Felix Kuehling wrote:
Am 2023-01-10 um 15:44 schrieb Philip Yang:
On 2023-01-10 13:33, Felix Kuehling wrote:
Am 2023-01-10 um 12:11 schrieb Philip Yang:
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage,
Christian,
I'm attaching the output of sudo lspci -. I'm not sure what $bus_id
is in this case. I guess it might be 00 in 00:00.0. I attached the dmesg
from previous boots with 6.2-rc1 at
https://bugzilla.kernel.org/show_bug.cgi?id=216865#c2 as I mentioned at
Am 2023-01-10 um 15:44 schrieb Philip Yang:
On 2023-01-10 13:33, Felix Kuehling wrote:
Am 2023-01-10 um 12:11 schrieb Philip Yang:
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used definition type to int64_t to be able to trigger
WARN_ONCE(adev && adev->kfd.vram_used < 0,
On 2023-01-10 13:33, Felix Kuehling wrote:
Am 2023-01-10 um 12:11 schrieb Philip Yang:
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used
Code in get_output_color_space depends on knowing the pixel encoding to
determine whether to pick between eg. COLOR_SPACE_SRGB or
COLOR_SPACE_YCBCR709 for transparent RGB -> YCbCr 4:4:4 in the driver.
v2: Fixed patch being accidentally based on a personal feature branch, oops!
Signed-off-by:
Code in get_output_color_space depends on knowing the pixel encoding to make
determinations about whether to pick between eg. COLOR_SPACE_SRGB or
COLOR_SPACE_YCBCR709 for transparent RGB -> YCbCr 4:4:4 in the driver.
Signed-off-by: Joshua Ashton
---
On Tue, Jan 10, 2023 at 2:40 PM Limonciello, Mario
wrote:
>
> [AMD Official Use Only - General]
>
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Tuesday, January 10, 2023 13:29
> > To: Limonciello, Mario
> > Cc: amd-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH]
[AMD Official Use Only - General]
> -Original Message-
> From: Alex Deucher
> Sent: Tuesday, January 10, 2023 13:29
> To: Limonciello, Mario
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd: Only load TA microcode for psp v12_0 once
>
> On Tue, Jan 10, 2023 at 2:16
On Tue, Jan 10, 2023 at 2:16 PM Mario Limonciello
wrote:
>
> During rebase from patch series accidentally ended up with two calls
> to load TA microcode for psp v12_0. Only one is needed, so remove the
> second.
>
> Fixes: f1efed401badb ("drm/amd: Parse both v1 and v2 TA microcode headers
>
During rebase from patch series accidentally ended up with two calls
to load TA microcode for psp v12_0. Only one is needed, so remove the
second.
Fixes: f1efed401badb ("drm/amd: Parse both v1 and v2 TA microcode headers using
same function")
Signed-off-by: Mario Limonciello
---
From: Luben Tuikov
[ Upstream commit 7554886daa31eacc8e7fac9e15bbce67d10b8f1f ]
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".
v2: Make the patch standalone, i.e. not dependent on local
From: Luben Tuikov
[ Upstream commit 7554886daa31eacc8e7fac9e15bbce67d10b8f1f ]
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".
v2: Make the patch standalone, i.e. not dependent on local
Am 2023-01-10 um 12:11 schrieb Philip Yang:
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used definition type to int64_t to be able to
Use page aligned size to reserve memory usage because page aligned TTM
BO size is used to unreserve memory usage, otherwise no page aligned
size causes memory usage accounting unbalanced.
Change vram_used definition type to int64_t to be able to trigger
WARN_ONCE(adev && adev->kfd.vram_used < 0,
From: hersen wu
[Why]
incorrect skip when drm_connector.index = 0 within
event_property_validate and update
[How] handle hdcp validate and update for connector 0
Reviewed-by: Bhawanpreet Lakha
Acked-by: Rodrigo Siqueira
Signed-off-by: hersen wu
---
From: Aric Cyr
This version brings along following fixes:
- Revert patches that caused regressions associated with audio and an
old change that checks the DCN version.
- Refactor DDC and HDP.
- Move DPIA and DPCD logic to new files.
- Updates to DMUB.
- Optimization and bug fixes for
From: hersen wu
[why]
For MST topology with 1 physical link and multiple connectors (>=2),
e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace
set to enable the HDCP simultaneously on all connected outputs, the
commit tail iteratively call the hdcp_update_display() for each
display
From: Alvin Lee
[Description]
- Request min clocks after disabling pipes on init
- This optimizes for power savings during init sequence
- Also handles the case where we boot up with no display connected
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
From: Dillon Varone
[WHY?]
Cannot only consider the MALL required from top pipes because of the MPO
case.
[HOW?]
Only count a pipe if it fits the following criteria:
1) does not have a top pipe (is the topmost pipe for that plane)
2) it does have a top pipe, but that pipe is associated with a
From: Alvin Lee
Enable subvp on specifically 1440p@60hz displays even though it can
switch in vactive.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 2 ++
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 31
From: Charlene Liu
keep dig_fifo enable for test pattern generation.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 +
.../gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c | 3
From: Brandon Syu
[Why]
There is an issue mapping non-allocated location of memory.
It would allocate gpio registers from an array out of bounds.
[How]
Patch correct numbers of bounds for using.
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Brandon Syu
---
From: Tony Tascioglu
[Why]
When an eDP panel is powered externally from a different GPU, we can avoid
waiting for hardware sequencing delays when switching the backlight on/off
as the display backlight is no longer powered by the original source.
[How]
This commit extends the
From: Dillon Varone
[WHY?]
For dcn32, SMU handles DISPCLK dentist programming.
[HOW?]
Only use calls to SMU to set DISPCLK.
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 96 ++-
1 file
From: Saaem Rizvi
[Why]
DCC meta was found to be detached from usable pixel data. Due to this
DCC meta and the end of the fetched part of the frame will be on not
be on the same mblk. Furthermore if the meta is not aligned to the mblk
size, then we require an extra mblk in MALL to account for
Remove some code that is never used from freesync file.
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/modules/freesync/freesync.c | 44 ---
1 file changed, 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
From: Dillon Varone
When using freesync on desktop, need to set freesync active bit for AMD
VSDBv3 infopacket.
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../amd/display/modules/freesync/freesync.c | 20 +--
1 file changed, 14
From: Tony Tascioglu
[Why]
When an eDP panel is powered externally by a different GPU, we don't need
to wait for hardware sequencing delays when powering down a link, as the
display is not dependent on the GPU being powered down.
[How]
This commit adds a variable 'link_powered_externally' to
From: Aurabindo Pillai
Checking for disabled master pipe on a timing synchronized pipe is
incorrect in the case of ODM combine. This case is acceptable as long as
the disabled master pipe is part of the ODM tree. Skip printing error
message if this condition holds true.
Reviewed-by: Dillon
From: Wenjing Liu
Reviewed-by: Wesley Chalmers
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 127 +--
From: Aurabindo Pillai
This reverts commit 08f4ff51e7667a473ae3d5435942a9dfda5953c4.
Reverting to put in a better solution which does not involve checking
DCN version.
Reviewed-by: Dillon Varone
Acked-by: Rodrigo Siqueira
Signed-off-by: Aurabindo Pillai
---
From: Saaem Rizvi
Current implementation of SubVP does not support cases where stream
timing matched neither the destination rect nor the source rect.
Will need to further debug to see how we can support these cases.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Saaem
From: Dillon Varone
Remove array size on array passed to CalculateDETSwathFillLatencyHiding.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 +-
From: Bhawanpreet Lakha
[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.
[how]
slower down the HW i2c speed when used by HW i2c.
Reviewed-by: Aurabindo Pillai
Reviewed-by: Rodrigo Siqueira
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c |
From: Dillon Varone
MALL SS and Subvp use the same calculations for determining the size of
the required allocation for a given surface, which is already done in
DML. Add an interface to extract this information from VBA variables and
use in their respective helper functions. Also refactor
From: Dillon Varone
DML does not explicitly consider support for space in MALL required for
subvp phantom pipes. This adds a check to make sure portion of phantom
surface can fit in MALL.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
From: Dillon Varone
Two issues existed:
1) Configs that support DRR, but have it disabled will fail subvp+vblank
validation incorrectly. Use subvp+vblank path for this case.
2) Configs that support DRR and have it enabled can use higher voltage level
than required if they also support
From: Dillon Varone
DML incorrectly uses surface width for determining DCC meta size in MALL
allocation calculations. Meta pitch should be used instead.
Reviewed-by: Alvin Lee
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
.../drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
From: Charlene Liu
Required by display init, also update get_dig_mode
Reviewed-by: Hansen Dsouza
Reviewed-by: Duncan Ma
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
.../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 12 +++-
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 18
From: Mustapha Ghaddar
[WHY]
Last PR missed name of a struct to match in DMUB
[HOW]
Update the logic in dmub_cmh.h header
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Rodrigo Siqueira
Signed-off-by: Mustapha Ghaddar
---
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 16 +-
From: Wenjing Liu
[why]
1. Move dd_link_ddc functions to link_ddc.
2. Move link ddc functions declaration exposed in dc to link.h
3. Move link ddc functions declaration exposed in dm to dc_link.h
4. Remove i2caux_interface.h file
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by:
From: Wenjing Liu
Reviewed-by: George Shen
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/Makefile | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
From: Wenjing Liu
[why]
Moving dpcd logic from dc_link_dpcd to link_dpcd as part of link file
restructure
Reviewed-by: George Shen
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/Makefile | 2 +-
From: Wenjing Liu
[why]
Factor out hpd handling logic from generic dc link file.
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 224 +---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 16 --
From: Cruise Hung
[Why]
The DPIA link encoder (DIG) was not released when a Display XDR 6K
monitor was disconnected. That's because the DPIA link encoder logic
checked the BW when it removed the link encoder for it. And the timing
BW was less than DP link BW. So, it failed to release the link
From: Dillon Varone
[WHY?]
FIFO enable sequence is incomplete as it is currently implemented in FW,
and requires reset to prevent the FIFO to be enabled in an invalid
state. This cannot be done until DIG FE is connected to the BE.
[HOW?]
Add FIFO enable sequence in driver for dcn32 with reset
From: Martin Leung
This reverts commit ef4e2703d6c81eb08e1cd29d14c819791e6898a6.
It caused corruption in some media players.
Reviewed-by: Aric Cyr
Reviewed-by: Nevenko Stupar
Acked-by: Rodrigo Siqueira
Signed-off-by: Martin Leung
---
.../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 -
From: Dmytro Laktyushkin
A previous fix attempted to correct mismatch between DM display
targets and dc panel instancing by only counting connected panels.
This behaviour breaks a feature, thus this is an alternative solution
that allows mapping display targets to dc links during
This DC patchset brings improvements in multiple areas. In summary, we
highlight the following areas:
- Revert patches that caused regressions associated with audio and an
old change that checks the DCN version.
- Refactor DDC and HDP.
- Move DPIA and DPCD logic to new files.
- Updates to
From: Mustapha Ghaddar
[WHY]
After introducing new DPIA NOTIFICATION we will need
to update the exiting BW allocation logic
[HOW]
Updated the BW alloc source and header files
Reviewed-by: Meenakshikumar Somasundaram
Acked-by: Rodrigo Siqueira
Signed-off-by: Mustapha Ghaddar
---
On Tue, Jan 10, 2023 at 11:23 AM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:
> Am 10.01.23 um 16:28 schrieb Marek Olšák:
>
> On Wed, Jan 4, 2023 at 9:51 AM Christian König <
> ckoenig.leichtzumer...@gmail.com> wrote:
>
>> Am 04.01.23 um 00:08 schrieb Marek Olšák:
>>
>> I see about
On 2023-01-09 22:14, Felix Kuehling wrote:
Am 2023-01-09 um 19:01 schrieb Philip Yang:
Use page aligned size to reserve VRAM usage because page aligned TTM BO
size is used to unreserve VRAM usage, otherwise this cause vram_used
accounting unbalanced.
Change vram_used definition type to
Am 10.01.23 um 16:28 schrieb Marek Olšák:
On Wed, Jan 4, 2023 at 9:51 AM Christian König
wrote:
Am 04.01.23 um 00:08 schrieb Marek Olšák:
I see about the access now, but did you even look at the patch?
I did look at the patch, but I haven't fully understood yet what
you are
Hi Rodrigo,
On Tue, Jan 10, 2023 at 4:44 PM Rodrigo Siqueira
wrote:
> Geert Uytterhoeven reported compiler issues in some specific gcc
> versions that point to a large stack size for DCN31/314. Unfortunately,
> I could not reproduce the problem with the latest version of GCC/Clang;
> but I still
On 11/22/22 06:20, hongao wrote:
[Why]
Setting scaling does not correctly update CRTC state. As a result
dc stream state's src (composition area) && dest (addressable area)
was not calculated as expected. This causes set scaling doesn's work.
[How]
Correctly update CRTC state when setting
On 12/27/22 13:39, Deepak R Varma wrote:
kfree() & vfree() internally performs NULL check on the pointer handed
to it and take no action if it indeed is NULL. Hence there is no need
for a pre-check of the memory pointer before handing it to
kfree()/vfree().
Issue reported by ifnullfree.cocci
On 10/01/2023 12:02, Matthew Auld wrote:
On 07/01/2023 15:15, Arunpravin Paneer Selvam wrote:
As we are observing low numbers in viewperf graphics benchmark, we
are strictly not allowing the top down flag enabled allocations
to steal the memory space from cpu visible region.
The approach is,
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
[...]/display/dc/dml/dcn314/display_mode_vba_314.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn314/display_mode_vba_314.c:7127:1: error: the
frame size of 2208 bytes is larger than 2048 bytes
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
[...]/display/dc/dml/dcn314/display_mode_vba_314.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn314/display_mode_vba_314.c:7127:1: error: the
frame size of 2208 bytes is larger than 2048 bytes
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
[...]/display/dc/dml/dcn314/display_mode_vba_314.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn314/display_mode_vba_314.c:7127:1: error: the
frame size of 2208 bytes is larger than 2048 bytes
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
[...]/display/dc/dml/dcn314/display_mode_vba_314.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn314/display_mode_vba_314.c:7127:1: error: the
frame size of 2208 bytes is larger than 2048 bytes
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
[...]/display/dc/dml/dcn314/display_mode_vba_314.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn314/display_mode_vba_314.c:7127:1: error: the
frame size of 2208 bytes is larger than 2048 bytes
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media]
Error 2
[...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1:
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media]
Error 2
[...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1:
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media]
Error 2
[...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1:
It was reported that on kernel v6.2-rc1, we have the following stack
size issue:
make[3]: *** [/kisskb/src/scripts/Makefile.build:504: drivers/media]
Error 2
[...]/display/dc/dml/dcn31/display_mode_vba_31.c: In function
'UseMinimumDCFCLK':
[...]/display/dc/dml/dcn31/display_mode_vba_31.c:7082:1:
Geert Uytterhoeven reported compiler issues in some specific gcc
versions that point to a large stack size for DCN31/314. Unfortunately,
I could not reproduce the problem with the latest version of GCC/Clang;
but I still believe this is a valid issue. Therefore, this patchset
attempts to address
Am 2023-01-05 um 14:28 schrieb Eric Huang:
The point bo->kfd_bo is NULL for queue's write pointer BO
when creating queue on mGPU. To avoid using the pointer
fixes the error.
Signed-off-by: Eric Huang
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
On Wed, Jan 4, 2023 at 9:51 AM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:
> Am 04.01.23 um 00:08 schrieb Marek Olšák:
>
> I see about the access now, but did you even look at the patch?
>
>
> I did look at the patch, but I haven't fully understood yet what you are
> trying to do
Hi Matthew,
On 1/10/2023 5:32 PM, Matthew Auld wrote:
On 07/01/2023 15:15, Arunpravin Paneer Selvam wrote:
As we are observing low numbers in viewperf graphics benchmark, we
are strictly not allowing the top down flag enabled allocations
to steal the memory space from cpu visible region.
The
On Tue, Jan 10, 2023 at 10:05:44AM -0500, Felix Kuehling wrote:
> Am 2023-01-10 um 08:45 schrieb Christian König:
> > And I'm like 99% sure that Kabini/Wani should be identical to that.
>
> Kabini is not supported by KFD. There should be no calls to amd_iommu_...
> functions on Kabini, at least
Am 2023-01-10 um 10:19 schrieb Jason Gunthorpe:
On Tue, Jan 10, 2023 at 10:05:44AM -0500, Felix Kuehling wrote:
Am 2023-01-10 um 08:45 schrieb Christian König:
And I'm like 99% sure that Kabini/Wani should be identical to that.
Kabini is not supported by KFD. There should be no calls to
Ping.
On 2023-01-05 14:28, Eric Huang wrote:
The point bo->kfd_bo is NULL for queue's write pointer BO
when creating queue on mGPU. To avoid using the pointer
fixes the error.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
Am 2023-01-10 um 08:45 schrieb Christian König:
And I'm like 99% sure that Kabini/Wani should be identical to that.
Kabini is not supported by KFD. There should be no calls to
amd_iommu_... functions on Kabini, at least not from kfd_iommu.c. And
I'm not aware of any other callers in
On 1/9/23 23:48, Quan, Evan wrote:
[AMD Official Use Only - General]
We need these to address the fan speed setting failure reported for the new
SMU13 asics.
My opinion shouldn't matter much given sparseness of activity, but,
despite his... short tonality, I agree with Lijo's assessment
Am 10.01.23 um 14:51 schrieb Jason Gunthorpe:
On Tue, Jan 10, 2023 at 02:45:30PM +0100, Christian König wrote:
Since this is a device integrated in the CPU it could be that the ACS/ATS
functionalities are controlled by the BIOS and can be enabled/disabled
there. But this should always
On Tue, Jan 10, 2023 at 01:48:39PM +0800, Baolu Lu wrote:
> On 2023/1/6 22:14, Jason Gunthorpe wrote:
> > On Thu, Jan 05, 2023 at 03:57:28PM +0530, Vasant Hegde wrote:
> > > Matt,
> > >
> > > On 1/5/2023 6:39 AM, Matt Fagnani wrote:
> > > > I built 6.2-rc2 with the patch applied. The same black
On Tue, Jan 10, 2023 at 02:45:30PM +0100, Christian König wrote:
> Since this is a device integrated in the CPU it could be that the ACS/ATS
> functionalities are controlled by the BIOS and can be enabled/disabled
> there. But this should always enable/disable both.
This sounds like a GPU driver
Am 10.01.23 um 14:25 schrieb Jason Gunthorpe:
On Tue, Jan 10, 2023 at 01:48:39PM +0800, Baolu Lu wrote:
On 2023/1/6 22:14, Jason Gunthorpe wrote:
On Thu, Jan 05, 2023 at 03:57:28PM +0530, Vasant Hegde wrote:
Matt,
On 1/5/2023 6:39 AM, Matt Fagnani wrote:
I built 6.2-rc2 with the patch
On 07/01/2023 15:15, Arunpravin Paneer Selvam wrote:
As we are observing low numbers in viewperf graphics benchmark, we
are strictly not allowing the top down flag enabled allocations
to steal the memory space from cpu visible region.
The approach is, we are sorting each order list entries in
On 12/19/22 09:49, Javier Martinez Canillas wrote:
> Hello Uwe,
>
> On 12/19/22 09:36, Uwe Kleine-König wrote:
>> While working on a drm driver that doesn't need the i2c algobit stuff I
>> noticed that DRM selects this code even though only 8 drivers actually use
>> it. While also only some
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