[AMD Official Use Only - General]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Lazar, Lijo
Sent: Friday, October 27, 2023 1:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Wang, Yang(Kevin) ; kernel
test robot
Subject:
Fixes warnings:
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c:286:45:
warning: '%s' directive output may be truncated writing up to 29 bytes
into a region of size 23 [-Wformat-truncation=]
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.c:286:52:
warning: '%s'
Switch from mode-1 reset to mode-2 for poison consumption.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 2ef7141596eed0b4b45ef18b3626f428a6b0a822 Add linux-next specific
files for 20231026
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202310171905.azfrkoid-...@intel.com
https
[why]
If driver does not set unmap latency for KIQ, the default value of KIQ
unmap latency is zero. When do unmap queue, KIQ will return that almost
immediately after receiving unmap command. So, the queue status will be
saved to MQD incorrectly or lost in some chance.
[how]
Set unmap latency
[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng
-Original Message-
From: Ma, Jun
Sent: Friday, October 27, 2023 9:57 AM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ;
Deucher, Alexander
Cc: Ma, Jun
Subject: [PATCH] drm/amd/pm: Return 0 as default min power limit for
Return 0 as the default min power limit for the asics using
powerplay.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Mahfooz, Hamza
Sent: Friday, October 27, 2023 1:29 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry ; Deucher, Alexander
; Koenig, Christian ; Li,
Sun peng
From: Rob Clark
Some of the fields that are handled by drm_show_fdinfo() crept back in
when rebasing the patch. Remove them again.
Fixes: 376c25f8ca47 ("drm/amdgpu: Switch to fdinfo helper")
Signed-off-by: Rob Clark
Reviewed-by:
Co-developed-by: Umio Yasuno
Signed-off-by: Umio Yasuno
---
Remove unused variables from amdgpu_show_fdinfo
Signed-off-by: Umio Yasuno
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
index e9b5d1903..b960ca7ba
Since `pr_config` is not initialized after its declaration, the
following operations with `replay_enable_option` may be performed
when `replay_enable_option` is holding junk values which could
possibly lead to undefined behaviour
```
...
pr_config.replay_enable_option |=
GFX 9.4.3 uses a new version of the GC info table in IP
discovery. This patch adds a new function to parse and
fill the cache information based on the new table. Also,
update cache reporting based on compute and memory
partitioning modes.
Signed-off-by: Mukul Joshi
---
Thanks!
On Thu, Oct 26, 2023 at 4:17 PM Luben Tuikov wrote:
>
> Pushed to drm-misc-next.
>
> Regards,
> Luben
>
> On 2023-10-26 15:52, Luben Tuikov wrote:
> > On 2023-10-26 15:32, Alex Deucher wrote:
> >> On Thu, Oct 26, 2023 at 2:22 AM Christian König
> >> wrote:
> >>>
> >>> Am 25.10.23 um
Pushed to drm-misc-next.
Regards,
Luben
On 2023-10-26 15:52, Luben Tuikov wrote:
> On 2023-10-26 15:32, Alex Deucher wrote:
>> On Thu, Oct 26, 2023 at 2:22 AM Christian König
>> wrote:
>>>
>>> Am 25.10.23 um 19:19 schrieb Alex Deucher:
Rather than doing this in the IP code for the SDMA
I've gone ahead and pushed this. Thanks!
Alex
On Thu, Oct 26, 2023 at 8:37 AM Christian König
wrote:
>
> Am 26.10.23 um 12:24 schrieb Arunpravin Paneer Selvam:
> > Temporarily remove the seq64 mapping sequence.
> >
> > Signed-off-by: Arunpravin Paneer Selvam
>
> Reviewed-by: Christian König
On 2023-10-26 15:32, Alex Deucher wrote:
> On Thu, Oct 26, 2023 at 2:22 AM Christian König
> wrote:
>>
>> Am 25.10.23 um 19:19 schrieb Alex Deucher:
>>> Rather than doing this in the IP code for the SDMA paging
>>> engine, move it up to the core device level init level.
>>> This should fix the
On 2023-10-26 13:29, Hamza Mahfooz wrote:
> An assignment statement was reversed during a refactor which effectively
> disabled S/G display outright. Since, we use
> adev->mode_info.gpu_vm_support to indicate to the rest of the driver
> that S/G display should be enabled and currently it is always
On Thu, Oct 26, 2023 at 1:45 PM Luben Tuikov wrote:
>
> Update the GPU Scheduler maintainer email.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Cc: AMD Graphics
> Cc: Direct Rendering Infrastructure - Development
>
> Signed-off-by: Luben Tuikov
On Thu, Oct 26, 2023 at 2:22 AM Christian König
wrote:
>
> Am 25.10.23 um 19:19 schrieb Alex Deucher:
> > Rather than doing this in the IP code for the SDMA paging
> > engine, move it up to the core device level init level.
> > This should fix the scheduler init ordering.
> >
> > v2: drop extra
#regzbot introduced: 1cfb4d612127
#regzbot title: rx7600 stopped working after "1cfb4d612127 drm/amdgpu: put MQDs
in VRAM"
Hi all,
I've been playing with RX7600 and it was observed that amdgpu stopped working
between kernel 6.2 and 6.5.
Then I narrowed it down to 6.4 <-> 6.5-rc1 and finally
On Thu, Oct 26, 2023 at 2:32 PM Mukul Joshi wrote:
>
> Fix a typo in parsing of the GC info table header when
> reading the IP discovery table.
>
> Fixes: ecb70926eb86 ("drm/amdgpu: add type conversion for gc info")
> Signed-off-by: Mukul Joshi
Reviewed-by: Alex Deucher
> ---
> v1->v2:
> -
On Thu, Oct 26, 2023 at 1:47 PM Hamza Mahfooz wrote:
>
> An assignment statement was reversed during a refactor which effectively
> disabled S/G display outright. Since, we use
> adev->mode_info.gpu_vm_support to indicate to the rest of the driver
> that S/G display should be enabled and
Since they were moved to VRAM, we need to use the IO
variants of memcpy.
Fixes: 1cfb4d612127 ("drm/amdgpu: put MQDs in VRAM")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 12 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++--
2 files changed, 12
On Thu, Oct 26, 2023 at 1:33 PM Alexey Klimov wrote:
>
> #regzbot introduced: 1cfb4d612127
> #regzbot title: rx7600 stopped working after "1cfb4d612127 drm/amdgpu: put
> MQDs in VRAM"
>
> Hi all,
>
> I've been playing with RX7600 and it was observed that amdgpu stopped working
> between kernel
Fix a typo in parsing of the GC info table header when
reading the IP discovery table.
Fixes: ecb70926eb86 ("drm/amdgpu: add type conversion for gc info")
Signed-off-by: Mukul Joshi
---
v1->v2:
- Add the Fixes tag.
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1
Fix a typo in parsing of the GC info table header when
reading the IP discovery table.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
Update the GPU Scheduler maintainer email.
Cc: Alex Deucher
Cc: Christian König
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: AMD Graphics
Cc: Direct Rendering Infrastructure - Development
Signed-off-by: Luben Tuikov
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
An assignment statement was reversed during a refactor which effectively
disabled S/G display outright. Since, we use
adev->mode_info.gpu_vm_support to indicate to the rest of the driver
that S/G display should be enabled and currently it is always set to
false. So, to fix this set
On Tue, 19 Sep 2023 15:22:49 -0300, Helen Koike wrote:
> DRM CI keeps track of which tests are failing, flaking or being skipped
> by the ci in the expectations files. Add entries for those files to the
> corresponding driver maintainer, so they can be notified when they
> change.
>
>
Applied
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
-Original Message-
From: amd-gfx On Behalf Of
jiadong@amd.com
Sent: Thursday, October 26, 2023 5:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Jiadong
Subject: [PATCH] drm/amdgpu/soc21: add mode2 asic
From: Aric Cyr
This version brings along following fixes:
Update test link rate DPCD bit field to match spec
Enable RCO options for dcn35
Add missing dml2 init value for dcn35
Enable DCN clock gating
DCN35 Disable cm power optimization
Allow 16 max_slices for DP2 DSC
Fix OTG disable workaround
From: Sung Joon Kim
[why]
To help isolate static screen and
video playback tests, we want to enable
an IPS option to allow IPS only on D3 cycle.
[how]
Add DISABLE_DYNAMIC and DISABLE_ALL
IPS disable flags for user control.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
From: Dennis Chan
[Why]
Current Desync IRQ handler will have some potential do not hit the
desync error case. We change to check both desync error HPD and DPCD.
Signed-off-by: Dennis Chan
Acked-by: Hersen Wu
Reviewed-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dc_types.h
From: ChunTao Tso
[Why]
For Replay, if we receive HPD, it doesn’t need to reboot the display.
We don’t need to return anything exactly.
[How]
Return nothing just because we don’t need to reboot the display.
Signed-off-by: ChunTao Tso
Acked-by: Hersen Wu
Reviewed-by: Jerry Zuo
---
From: Daniel Miess
[Why & How]
Enable root clock optimization options for dcn35
for power savings
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
.../gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c| 1 +
.../drm/amd/display/dc/dcn35/dcn35_resource.c|
From: Dennis Chan
[why]
It's useful to disable the recovery mechanism when debugging replay
desync errors.
Signed-off-by: Dennis Chan
Acked-by: Hersen Wu
Reviewed-by: Robin Chen
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 3 ++-
From: Anthony Koo
- Increase number of bits for IPS boot option
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: George Shen
[Why]
An SCR was made to the DP2.0 spec that updated the bit field definition
for UHBR13.5 in the test link rate DPCD register.
[How]
Add new translation to match the SCR update. Keep old translation for
backwards compatibility.
Reviewed-by: Wenjing Liu
Acked-by: Hersen Wu
From: Daniel Miess
[Why & How]
Enable dcn clock gating for dcn35
Disable DTBCLK gate before FRL link training
and re-enable afterwards
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h| 6 +-
From: Fangzhi Zuo
Enable 12 and 16 max_slices for DP2 DSC
Reviewed-by: Alvin Lee
Acked-by: Hersen Wu
Signed-off-by: Fangzhi Zuo
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 10 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 11 +++
From: Roman Li
[Why]
For lighting up, some dml2 params needs to be initialized.
One of them escaped initial patch under:
"drm/amd/display: Add DCN35 DML2 support"
[How]
Add missing initialization.
Fixes: 8e821cf83eed ("drm/amd/display: Add DCN35 DML2 support")
Reviewed-by: Harry Wentland
From: Taimur Hassan
[Why]
DENTIST was hanging when performing DISPCLK update with OTG enabled, as
OTG disable workaround was not executing.
[How]
Workaround was checking against current_state before running, but when
called from optimize_bandwidth (safe_to_lower), we should be checking
against
From: Ilya Bakoulin
[Why]
When MPO surface pixel format is not ARGB, fast update can miss
programming blendTF.
[How]
Set the gamma_change update flag on blend_tf change.
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Sung Joon Kim
[why]
DML2 does not handle the case when we have
a single stream sourcing 2 or more planes
that are duplicates of one another. To properly
handle this scenario, pipe index to plane index
mapping is used to decide which plane is being
processed and programmed.
[how]
Create
From: George Shen
[Why]
Some DP link layer tests request a different colorimetry than the
default one that is used. Currently, our test automation logic does not
update the MSA with the test request value for DP HPO case.
[How]
Update HPO MSA colorimetry with test automation request value.
From: Yihan Zhu
[WHY & HOW]
Enabling SCE after boot up will cause color distortion.
Reviewed-by: Ovidiu Bunea
Acked-by: Hersen Wu
Signed-off-by: Yihan Zhu
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Anthony Koo
- Minor formatting changes
- Update defines to match the bit width of the field it is used for
- Add new boot up bits to control HW sub block regions power
down
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Anthony Koo
---
From: Sung Joon Kim
[why]
Make sure to ungate the clocks on boot
so programming sequence is done successfully.
[how]
Move the ungate logic after bios init.
Reviewed-by: Xi (Alex) Liu
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
---
From: Ilya Bakoulin
[Why]
LUT write index does not get reset to zero when writing the LUT values
for each separate RGB component, which results in wrong data for 2 of
the 3 components.
[How]
Reset LUT write index to zero before writing each component's data.
Reviewed-by: Krunoslav Kovac
From: Aric Cyr
This version brings along following fixes:
On boot disable domain22 force power on
decouple dmcub execution to reduce lock granularity
Enable fast update on blendTF change
Fix blend LUT programming
Program plane color setting correctly
amend HPD handler for Replay
Avoid NULL
From: Daniel Miess
[Why]
HDCP2 enablement fails when domain22 is set to force
power on
[How]
Disable force power on for domain22 on startup
Reviewed-by: Nicholas Kazlauskas
Acked-by: Hersen Wu
Signed-off-by: Daniel Miess
---
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c | 10
From: Ilya Bakoulin
[Why]
Full update is not required on surface blend TF change.
[How]
Update full_update_required condition.
Reviewed-by: Aric Cyr
Acked-by: Hersen Wu
Signed-off-by: Ilya Bakoulin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
1 file changed, 1 deletion(-)
diff
From: "JinZe.Xu"
[Why]
On some systems dmub commands run at high IRQ, so long running
commands will block other interrupts.
[How]
Decouple wait_for_idle from dmcub queue/execute/wait.
Reviewed-by: Josip Pavic
Acked-by: Hersen Wu
Signed-off-by: JinZe.Xu
---
From: Wayne Lin
[Why & How]
Check whether assigned timing generator is NULL or not before
accessing its funcs to prevent NULL dereference.
Reviewed-by: Jun Lei
Acked-by: Hersen Wu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
1 file changed, 2
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Enable HPD handler for replay.
* Add disable replay desync error check.
* Add more IPS options for static screen and video playback.
* Add test link rate UHBR13.5 for DP2.0.
* Enable 12 and 16 max_slices for DP2
From: Sung Joon Kim
[why]
There are some registers for plane
color that are skipped programming
on resume. Need to add those as part
of the sequence.
[how]
Add new function hook for programming
plane color control.
Reviewed-by: Duncan Ma
Acked-by: Hersen Wu
Signed-off-by: Sung Joon Kim
---
[AMD Official Use Only - General]
Yes, I have tested this.
The (!amdgpu_sriov_runtime(adev) && adev->gfx.rlc.rlcg_reg_access_supported)
conditions in amdgpu_device_xcc_wreg will guarantee it will go into
amdgpu_virt_rlcg_reg_rw instead of looping back to WREG32_XCC.
Thanks,
Victor
Am 26.10.23 um 15:34 schrieb Yifan Zhang:
gpu tlb flush is skipped if reset sem is held, it makes
mes_self_test fail since it involves add_hw_queue/remove_hw_queue
which needs tlb flush functional. Remove mes_self_test in gpu
recover sequence.
Oh, the TLB issue is actually only the tip of the
gpu tlb flush is skipped if reset sem is held, it makes
mes_self_test fail since it involves add_hw_queue/remove_hw_queue
which needs tlb flush functional. Remove mes_self_test in gpu
recover sequence.
This patch is to fix the recover failure in gfx11.
[ 1831.768292] [drm] ring sdma_32769.3.3
Am 10.10.23 um 12:17 schrieb Shashank Sharma:
This patch adds support for userqueue eviction fences. In general, when
a process wants to map VRAM memory but TTM can't find enough space, it
attempts to evict BOs from its LRU list. This fence will prevent the TTM
manager from evicting the
Am 26.10.23 um 12:24 schrieb Arunpravin Paneer Selvam:
Temporarily remove the seq64 mapping sequence.
Signed-off-by: Arunpravin Paneer Selvam
Reviewed-by: Christian König
Please push to amd-staging-drm-next ASAP and ping Kenny when that's
merged (or if it doesn't merge automatically).
Temporarily remove the seq64 mapping sequence.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index
From: Jiadong Zhu
Set the default reset method to mode2 for SMU IP v14.0.0
Signed-off-by: Jiadong Zhu
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index
[AMD Official Use Only - General]
Looks like Tao's patch already fixed it, [PATCH] drm/amdgpu: check RAS
supported first in ras_reset_error_count
[Zhang, Jesse(Jie)] I see it, Thanks for you reminder.
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Jesse Zhang
Sent:
[AMD Official Use Only - General]
Looks like Tao's patch already fixed it, [PATCH] drm/amdgpu: check RAS
supported first in ras_reset_error_count
Thanks,
Candice
-Original Message-
From: amd-gfx On Behalf Of Jesse Zhang
Sent: Thursday, October 26, 2023 4:37 PM
To:
[AMD Official Use Only - General]
Thanks a lot for the review!
Regards.
Perry
> -Original Message-
> From: Zhang, Yifan
> Sent: Thursday, October 26, 2023 3:31 PM
> To: Yuan, Perry ; Feng, Kenneth
> ; Limonciello, Mario
>
> Cc: Deucher, Alexander ; Wang, Yang(Kevin)
> ;
Add check for ras pointers.
Issues caused by this commit: be5c7eb104067d61
[ 2312.987618] BUG: kernel NULL pointer dereference, address: 00e8
[ 2312.987622] #PF: supervisor read access in kernel mode
[ 2312.987624] #PF: error_code(0x) - not-present page
[ 2312.987625] PGD 0 P4D 0
On 10/26/2023 2:22 AM, Victor Lu wrote:
amdgpu_kiq_wreg/rreg is hardcoded to use MEC engine 0.
Add an xcc_id parameter to amdgpu_kiq_wreg/rreg, define W/RREG32_XCC
and amdgpu_device_xcc_wreg/rreg to to use the new xcc_id parameter.
v3: use W/RREG32_XCC to handle non-kiq case
v2: define
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Yuan, Perry
Sent: Tuesday, October 24, 2023 10:50 PM
To: Zhang, Yifan ; Feng, Kenneth ;
Limonciello, Mario
Cc: Deucher, Alexander ; Wang, Yang(Kevin)
;
[AMD Official Use Only - General]
This patch is:
Reviewed-by: Yifan Zhang
Best Regards,
Yifan
-Original Message-
From: Yuan, Perry
Sent: Tuesday, October 24, 2023 10:50 PM
To: Zhang, Yifan ; Feng, Kenneth ;
Limonciello, Mario
Cc: Deucher, Alexander ; Wang, Yang(Kevin)
;
Am 25.10.23 um 20:45 schrieb Felix Kuehling:
On 2023-10-25 02:12, Christian König wrote:
Am 24.10.23 um 21:20 schrieb David Francis:
dmaunmap can call ttm_bo_validate, which expects the
ttm dma_resv to be held.
Well first of all the dma_resv object isn't related to TTM.
Acquire the locks
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