Am 29.11.23 um 17:03 schrieb Alex Deucher:
On Wed, Nov 29, 2023 at 10:47 AM Christian König
wrote:
Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
While improbable, there may be a chance of hitting integer
overflow when the result of radeon_get_ib_value() gets shifted
left.
Avoid it by
Hi Alex,
On 11/30/2023 12:39 AM, Alex Deucher wrote:
> On Wed, Nov 29, 2023 at 11:37 AM Ma Jun wrote:
>>
>> Some platforms can't resume from d3cold state, So add a
>> new module parameter to disable d3cold state for debugging
>> purpose or workaround.
>
> Doesn't the runpm parameter already
[AMD Official Use Only - General]
Reviewed-by: Bob Zhou
Regards,
Bob
-Original Message-
From: amd-gfx On Behalf Of Yang Wang
Sent: Thursday, November 30, 2023 1:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Wang, Yang(Kevin)
; Zhang, Hawking
Subject: [PATCH] drm/amdgpu:
[AMD Official Use Only - General]
-Original Message-
From: Lazar, Lijo
Sent: Thursday, November 30, 2023 1:13 PM
To: Wang, Yang(Kevin) ; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking
Subject: Re: [PATCH] drm/amdgpu: fix miss to create mca debugfs node issue
On 11/30/2023 10:39 AM,
On 11/30/2023 10:39 AM, Yang Wang wrote:
Use amdgpu_ip_version() helper function to check ip version.
The ip verison contains other information,
use the helper function to avoid reading wrong value.
Signed-off-by: Yang Wang
May refine the subject to "Fix missing mca debugfs node"
Use amdgpu_ip_version() helper function to check ip version.
The ip verison contains other information,
use the helper function to avoid reading wrong value.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 2023-11-29 22:36, Luben Tuikov wrote:
> On 2023-11-29 15:49, Alex Deucher wrote:
>> On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
>>>
>>> Actually I think I see the problem. I'll try and send out a patch
>>> later today to test.
>>
>> Does the attached patch fix it?
>
> Thanks for the
On 2023-11-29 15:49, Alex Deucher wrote:
> On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
>>
>> Actually I think I see the problem. I'll try and send out a patch
>> later today to test.
>
> Does the attached patch fix it?
Thanks for the patch, Alex.
Is it possible for AMD to also
On Thu, Nov 23, 2023 at 02:23:01PM +, Conor Dooley wrote:
> On Tue, Nov 21, 2023 at 07:05:15PM -0800, Samuel Holland wrote:
> > RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other
> > architectures. Enabling hardware FP requires overriding the ISA string
> > for the relevant
- After a full reset, VF's FB will be cleaned. This
includes the VCN's fw_shared memory.
However, there is no suspend-resume routine for
SRIOV VF. Therefore, the data in the fw_shared
memory will be lost forever and it causes engine
hang later on.
We must repopulate the data in
- Move VCN4's fw_shared initialization to a separated function.
This way, the function can be reused at different locations.
Signed-off-by: Bokun Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 45 ---
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git
Hi Weixi,
Even though Christian has listed reasons rejecting this proposal (yes they are
very reasonable to me), I would open my mind and further explore the
possibility here. Since the current GPU driver uses a hmm based implementation
(AMD and NV has done this; At Intel we are catching up),
On Wed, Nov 22, 2023 at 1:58 PM Christian König
wrote:
>
> Am 22.11.23 um 17:05 schrieb Ramesh Errabolu:
> > Fix the documentation of struct dma_buf members name and exp_name
> > as to how these members are to be used and accessed.
> >
> > Signed-off-by: Ramesh Errabolu
>
> Reviewed-by:
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Bokun Zhang
> Sent: Tuesday, November 28, 2023 4:25 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Bokun
> Subject: [PATCH] drm/amd/amdgpu: Clean up VCN fw_shared and set flag
> bits during
On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
>
> Actually I think I see the problem. I'll try and send out a patch
> later today to test.
Does the attached patch fix it?
Alex
>
> Alex
>
> On Wed, Nov 29, 2023 at 1:52 PM Alex Deucher wrote:
> >
> > On Wed, Nov 29, 2023 at 11:41 AM
Luben Tuikov writes:
> I remember that the problem was really that amdgpu called
> drm_sched_entity_init(),
> in amdgpu_ttm_set_buffer_funcs_status() without actually having initialized
> the scheduler
> used therein. For instance, the code before commit b70438004a14f4, looked
> like this:
>
Actually I think I see the problem. I'll try and send out a patch
later today to test.
Alex
On Wed, Nov 29, 2023 at 1:52 PM Alex Deucher wrote:
>
> On Wed, Nov 29, 2023 at 11:41 AM Luben Tuikov wrote:
> >
> > On 2023-11-29 10:22, Alex Deucher wrote:
> > > On Wed, Nov 29, 2023 at 8:50 AM Alex
On Wed, Nov 29, 2023 at 11:41 AM Luben Tuikov wrote:
>
> On 2023-11-29 10:22, Alex Deucher wrote:
> > On Wed, Nov 29, 2023 at 8:50 AM Alex Deucher wrote:
> >>
> >> On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
> >>>
> >>> On 2023-11-28 17:13, Alex Deucher wrote:
> On Mon, Nov 27,
On Wed, Nov 29, 2023 at 11:21 AM Luben Tuikov wrote:
>
> On 2023-11-29 08:50, Alex Deucher wrote:
> > On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
> >>
> >> On 2023-11-28 17:13, Alex Deucher wrote:
> >>> On Mon, Nov 27, 2023 at 6:24 PM Phillip Susi wrote:
>
> Alex Deucher
On Wed, Nov 29, 2023 at 1:02 PM Mario Limonciello
wrote:
>
> On 11/29/2023 02:51, Ma Jun wrote:
> > Some platforms can't resume from d3cold state, So add a
> > new module parameter to disable d3cold state for debugging
> > purpose or workaround.
> >
> > Signed-off-by: Ma Jun
> > ---
>
> This
During hibernate sequence the source context might not have a clk_mgr.
So don't use it to look for DML2 support.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2980
Fixes: a2815ada8616 ("drm/amd/display: Introduce DML2")
Signed-off-by: Mario Limonciello
---
On 11/29/2023 03:13, Ma Jun wrote:
From: Evan Quan
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Ma Jun
Signed-off-by: Evan Quan
I think the order should be the other way around for these SoB as
"you're signing off on Evan's work".
On 11/29/2023 03:13, Ma Jun wrote:
Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.
To mitigate this, AMD has
On 11/29/2023 03:13, Ma Jun wrote:
Add documentation about AMD's Wifi band RFI mitigation (WBRF) mechanism
explaining the theory and how it is used.
Signed-off-by: Ma Jun
Reviewed-by: Hans de Goede
Reviewed-by: Mario Limonciello
--
v14:
- Fix the format issue (IIpo Jarvinen)
---
On 2023-11-29 10:22, Alex Deucher wrote:
> On Wed, Nov 29, 2023 at 8:50 AM Alex Deucher wrote:
>>
>> On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
>>>
>>> On 2023-11-28 17:13, Alex Deucher wrote:
On Mon, Nov 27, 2023 at 6:24 PM Phillip Susi wrote:
>
> Alex Deucher writes:
On Wed, Nov 29, 2023 at 11:37 AM Ma Jun wrote:
>
> Some platforms can't resume from d3cold state, So add a
> new module parameter to disable d3cold state for debugging
> purpose or workaround.
Doesn't the runpm parameter already handle this? If you set runpm=0,
that should disable d3cold.
Alex
On 2023-11-14 16:01, Xiaogang.Chen
wrote:
From: Xiaogang Chen
This patch implements partial migration/mapping for gpu/cpu page faults in SVM
according to migration granularity(default 2MB). A svm range may include pages
from both system ram and vram of one
On 2023-11-29 08:50, Alex Deucher wrote:
> On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
>>
>> On 2023-11-28 17:13, Alex Deucher wrote:
>>> On Mon, Nov 27, 2023 at 6:24 PM Phillip Susi wrote:
Alex Deucher writes:
>> In that case those are the already known problems
On Wed, Nov 29, 2023 at 10:47 AM Christian König
wrote:
>
> Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
> > While improbable, there may be a chance of hitting integer
> > overflow when the result of radeon_get_ib_value() gets shifted
> > left.
> >
> > Avoid it by casting one of the operands
Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
While improbable, there may be a chance of hitting integer
overflow when the result of radeon_get_ib_value() gets shifted
left.
Avoid it by casting one of the operands to larger data type (u64).
Found by Linux Verification Center
On 11/29/2023 06:36, Lijo Lazar wrote:
Only PSPv13.0.6 SOCs take a longer time to reach steady state. Other
PSPv13 based SOCs don't need extended wait. Also, reduce PSPv13.0.6 wait
time.
Signed-off-by: Lijo Lazar
Thanks!
Reviewed-by: Mario Limonciello
When you commit can you please add the
It may be possible, albeit unlikely, to encounter integer overflow
during the multiplication of several unsigned int variables, the
result being assigned to a variable 'size' of wider type.
Prevent this potential behaviour by converting one of the multiples
to unsigned long.
Found by Linux
While improbable, there may be a chance of hitting integer
overflow when the result of radeon_get_ib_value() gets shifted
left.
Avoid it by casting one of the operands to larger data type (u64).
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes:
On 11/29/2023 02:51, Ma Jun wrote:
Some platforms can't resume from d3cold state, So add a
new module parameter to disable d3cold state for debugging
purpose or workaround.
Signed-off-by: Ma Jun
---
This patch is essentially an 'amdgpu knob' for d3cold on the root port.
At least for
On Wed, Nov 29, 2023 at 8:50 AM Alex Deucher wrote:
>
> On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
> >
> > On 2023-11-28 17:13, Alex Deucher wrote:
> > > On Mon, Nov 27, 2023 at 6:24 PM Phillip Susi wrote:
> > >>
> > >> Alex Deucher writes:
> > >>
> > In that case those are the
Am 29.11.23 um 09:27 schrieb zhuweixi:
Glad to hear that more sharable code is desirable.
IMHO, for a common MM subsystem, it is more beneficial for
GMEM to extend core MM instead of building a separate one.
As stated in the beginning of my RFC letter, MM systems are
large and similar. Even a
On Wed, Nov 29, 2023 at 6:17 AM Lazar, Lijo wrote:
>
>
>
> On 11/29/2023 12:22 AM, Mario Limonciello wrote:
> > As the module parameter can be used to control behavior, all parts
> > of the driver should obey what has been programmed by user or
> > detected by auto mode rather than what "can" be
On Wed, Nov 29, 2023 at 9:22 AM Tom St Denis wrote:
>
> These were requested by a UMR user for debugging purposes.
>
> Signed-off-by: Tom St Denis
Acked-by: Alex Deucher
> ---
> .../asic_reg/smuio/smuio_10_0_2_offset.h | 102 ++
> .../asic_reg/smuio/smuio_10_0_2_sh_mask.h |
[AMD Official Use Only - General]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, November 29, 2023 6:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Limonciello,
Mario
Subject:
On Tue, Nov 28, 2023 at 11:45 PM Luben Tuikov wrote:
>
> On 2023-11-28 17:13, Alex Deucher wrote:
> > On Mon, Nov 27, 2023 at 6:24 PM Phillip Susi wrote:
> >>
> >> Alex Deucher writes:
> >>
> In that case those are the already known problems with the scheduler
> changes, aren't they?
These were requested by a UMR user for debugging purposes.
Signed-off-by: Tom St Denis
---
.../asic_reg/smuio/smuio_10_0_2_offset.h | 102 ++
.../asic_reg/smuio/smuio_10_0_2_sh_mask.h | 184 ++
2 files changed, 286 insertions(+)
create mode 100644
Only PSPv13.0.6 SOCs take a longer time to reach steady state. Other
PSPv13 based SOCs don't need extended wait. Also, reduce PSPv13.0.6 wait
time.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
On 11/29/2023 12:22 AM, Mario Limonciello wrote:
As the module parameter can be used to control behavior, all parts
of the driver should obey what has been programmed by user or
detected by auto mode rather than what "can" be supported.
This is also not correct. You can very well disable
On 11/29/2023 12:22 AM, Mario Limonciello wrote:
Rather than plumbing module parameter deep into IP declare BAMACO
runpm mode at amdgpu_driver_set_runtime_pm_mode() and then detect
this mode in consumers.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
On 11/29/2023 12:22 AM, Mario Limonciello wrote:
On products that support both BOCO and BACO it should be possible
to override the BOCO detection and force BACO by amdgpu.runpm=1 but
this doesn't work today.
Adjust the logic used in amdgpu_driver_load_kms() to make sure that
module
On 11/28/23 07:50, Weixi Zhu wrote:
This patch adds an abstraction layer, struct vm_object, that maintains
per-process virtual-to-physical mapping status stored in struct gm_mapping.
For example, a virtual page may be mapped to a CPU physical page or to a
device physical page. Struct vm_object
Glad to hear that more sharable code is desirable.
IMHO, for a common MM subsystem, it is more beneficial for
GMEM to extend core MM instead of building a separate one.
As stated in the beginning of my RFC letter, MM systems are
large and similar. Even a sophisticated one like Linux MM
that
From: Evan Quan
Fulfill the SMU13.0.7 support for Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
Signed-off-by: Ma Jun
--
v10->v11:
- downgrade the prompt level on message failure(Lijo)
v13:
- Fix the format issue (IIpo Jarvinen)
- Remove duplicate
Fulfill the SMU13.0.0 support for Wifi RFI mitigation feature.
Co-developed-by: Evan Quan
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
Signed-off-by: Ma Jun
--
v10->v11:
- downgrade the prompt level on message failure(Lijo)
v13:
- Fix the format issue (IIpo Jarvinen)
- Move
From: Evan Quan
To protect PMFW from being overloaded.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 29 +++
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +
2 files changed, 30
From: Evan Quan
With WBRF feature supported, as a driver responding to the frequencies,
amdgpu driver is able to do shadow pstate switching to mitigate possible
interference(between its (G-)DDR memory clocks and local radio module
frequency bands used by Wifi 6/6e/7).
Signed-off-by: Evan Quan
From: Evan Quan
Add those data structures to support Wifi RFI mitigation feature.
Signed-off-by: Evan Quan
Reviewed-by: Mario Limonciello
Signed-off-by: Ma Jun
v13:
- Move some struct variables to amdgpu_smu.h to reduce
duplicate code
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
From: Evan Quan
To support the WBRF mechanism, Wifi adapters utilized in the system must
register the frequencies in use (or unregister those frequencies no longer
used) via the dedicated calls. So that, other drivers responding to the
frequencies can take proper actions to mitigate possible
From: Evan Quan
The newly added WBRF feature needs this interface for channel
width calculation.
Signed-off-by: Ma Jun
Signed-off-by: Evan Quan
--
v8->v9:
- correct typo(Mhz -> MHz) (Johnson)
v13:
- Fix the format issue (IIpo Jarvinen)
---
include/net/cfg80211.h | 9 +
Due to electrical and mechanical constraints in certain platform designs
there may be likely interference of relatively high-powered harmonics of
the (G-)DDR memory clocks with local radio module frequency bands used
by Wifi 6/6e/7.
To mitigate this, AMD has introduced a mechanism that devices
Add documentation about AMD's Wifi band RFI mitigation (WBRF) mechanism
explaining the theory and how it is used.
Signed-off-by: Ma Jun
Reviewed-by: Hans de Goede
--
v14:
- Fix the format issue (IIpo Jarvinen)
---
Documentation/driver-api/wbrf.rst | 78 +++
1 file
Due to electrical and mechanical constraints in certain platform designs there
may be likely interference of relatively high-powered harmonics of the (G-)DDR
memory clocks with local radio module frequency bands used by Wifi 6/6e/7. To
mitigate possible RFI interference we introuduced WBRF(Wifi
Some platforms can't resume from d3cold state, So add a
new module parameter to disable d3cold state for debugging
purpose or workaround.
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
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