[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Candice Li
Sent: Tuesday, March 19, 2024 11:26
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice
Subject: [PATCH] drm/amdgpu: Update setting EEPROM table version
Use helper function instead of umc callback to set
EEPROM table version.
Signed-off-by: Candice Li
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 22 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 --
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c| 6 -
3 files
[Public]
Reviewed-by: Lang Yu
>-Original Message-
>From: Lee, Peyton
>Sent: Wednesday, March 13, 2024 7:45 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander ; Zhang, Yifan
>; Ma, Li ; Yu, Lang
>; Lee, Peyton
>Subject: [PATCH] drm/amdgpu/vpe: power on vpe when hw_init
>
>To
On 2/23/24 11:39 PM, Srinivasan Shanmugam wrote:
pipe_ctx->plane_res.mpcc_inst is of a type that can only hold values
between 0 and 255, so it's always greater than or equal to 0.
Thus the condition 'pipe_ctx->plane_res.mpcc_inst >= 0' was always true
and has been removed.
Fixes the below:
On 2/23/24 11:39 PM, Srinivasan Shanmugam wrote:
Refactors the dml32_TruncToValidBPP function by removing a
redundant return statement.
The function previously had a return statement at the end that was
never executed because all execution paths in the function ended with
a return statement
Add a new test case for the drm buddy clear and dirty
allocation.
Signed-off-by: Arunpravin Paneer Selvam
Suggested-by: Matthew Auld
---
drivers/gpu/drm/tests/drm_buddy_test.c | 127 +
1 file changed, 127 insertions(+)
diff --git
Add clear page support in vram memory region.
v1(Christian):
- Dont handle clear page as TTM flag since when moving the BO back
in from GTT again we don't need that.
- Make a specialized version of amdgpu_fill_buffer() which only
clears the VRAM areas which are not already cleared
-
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each block as cleared.
- Track the available cleared pages size
- If driver requests cleared memory we prefer cleared
From: Hawking Zhang
Enable smuio v14_0_2_callbacks
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
From: Hawking Zhang
Add smuio v14_0_2 ip block support
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile| 3 +-
drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c | 41 ++
From: Hawking Zhang
Add smuio callback to get gpu clk counter
Signed-off-by: Hawking Zhang
Reviewed-by: Likun Gao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h | 1 +
drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c | 21 +
2 files changed, 22
SMUIO is the IO subset of the SMU block. It handles a variety
of functionality on the GPU including reading the ROM image and
accessing the GPU clock counter. This adds support for SMUIO
14.0.2.
Note that patch 1 adds register headers and is very large so it
has been omitted.
Hawking Zhang
On 2024-03-15 14:17, Mukul Joshi wrote:
Check cgroup permissions when returning DMA-buf info and
based on cgroup check return the id of the GPU that has
access to the BO.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
1 file changed, 2 insertions(+), 2
On Mon, Mar 18, 2024 at 3:52 PM Alex Deucher wrote:
>
> On Mon, Mar 18, 2024 at 12:06 PM Kurt Kartaltepe
> wrote:
> >
> > On Mon, Mar 18, 2024 at 8:42 AM Alex Deucher wrote:
> > >
> > > On Mon, Mar 18, 2024 at 10:19 AM Kurt Kartaltepe
> > > wrote:
> > > >
> > > > On Mon, Mar 18, 2024 at 6:37
On Mon, Mar 18, 2024 at 12:06 PM Kurt Kartaltepe wrote:
>
> On Mon, Mar 18, 2024 at 8:42 AM Alex Deucher wrote:
> >
> > On Mon, Mar 18, 2024 at 10:19 AM Kurt Kartaltepe
> > wrote:
> > >
> > > On Mon, Mar 18, 2024 at 6:37 AM Alex Deucher
> > > wrote:
> > > >
> > > > On Mon, Mar 18, 2024 at
On 18/03/2024 18:30, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: amd-gfx On Behalf Of
Shashank Sharma
Sent: Monday, March 18, 2024 12:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian ; Kuehling, Felix
; Bhardwaj, Rajneesh
; Deucher,
On 18/03/2024 19:10, Christian König wrote:
Am 18.03.24 um 17:11 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be
In SRIOV CPX mode, each VF has 4 jpeg engines. The even-
numbered VFs point to JPEG0 block of the AID and the odd-
numbered VFs point to the JPEG1 block.
Even-numbered VFs Odd numbered VFs
VCN doorbell 0 VCN Decode ring VCN Decode ring
VCN doorbell 1-3
sdma has 2 instances in SRIOV cpx mode. Odd numbered VFs have
sdma0/sdma1 instances. Even numbered vfs have sdma2/sdma3.
Changes involve
1. identifying odd/even numbered VF
2. registering correct number of instances with irq handler
3. mapping instance number with IH client-id depending upon
For SRIOV CPX mode, the assignments of jpeg doorbells depends on
whether the VF is even/odd numbered. Physical xcc_id provides
info whether the VF is even/odd.
regCP_PSP_XCP_CTL is RO for VF through rlcg.
Signed-off-by: Samir Dhume
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
Am 18.03.24 um 17:11 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of
> Shashank Sharma
> Sent: Monday, March 18, 2024 12:12 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Koenig, Christian ; Kuehling, Felix
> ; Bhardwaj, Rajneesh
> ; Deucher, Alexander
> ; Sharma, Shashank
>
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will keep the
objects that need to be freed after tlb_flush.
- Adds PT entries in this list in amdgpu_vm_ptes_update after
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a DMA-fence object which
can be used to delay the
On Mon, Mar 18, 2024 at 10:19 AM Kurt Kartaltepe wrote:
>
> On Mon, Mar 18, 2024 at 6:37 AM Alex Deucher wrote:
> >
> > On Mon, Mar 18, 2024 at 4:47 AM Kurt Kartaltepe
> > wrote:
> > >
> > > These checks prevent using amdgpu with the pcie=assign-busses parameter
> > > which will re-address
Am 18.03.24 um 16:22 schrieb Sharma, Shashank:
On 18/03/2024 16:01, Christian König wrote:
Am 18.03.24 um 15:44 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in
On 18/03/2024 16:01, Christian König wrote:
Am 18.03.24 um 15:44 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will
keep the
objects
On 18/03/2024 15:58, Christian König wrote:
Am 18.03.24 um 13:08 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be
Am 18.03.24 um 15:44 schrieb Shashank Sharma:
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will keep the
objects that need to be freed after tlb_flush.
- Adds PT
Am 18.03.24 um 13:08 schrieb Shashank Sharma:
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will keep the
objects that need to be freed after tlb_flush.
- Adds PT entries in this list in amdgpu_vm_ptes_update after
The change you shared with me fixes the crash. Pl include in v8.
On 3/18/2024 10:06 AM, Sharma, Shashank wrote:
[AMD Official Use Only - General]
Already sent a NULL check patch based on this backtrace, I am waiting
for Rajneesh's feedback.
Regards
Shashank
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 2e93f143ca010a5013528e1cfdc895f024fe8c21 Add linux-next specific
files for 20240318
Error/Warning ids grouped by kconfigs:
gcc_recent_errors
|-- arc-allmodconfig
| `--
fs-ubifs
[AMD Official Use Only - General]
Already sent a NULL check patch based on this backtrace, I am waiting for
Rajneesh's feedback.
Regards
Shashank
From: Bhardwaj, Rajneesh
Sent: Monday, March 18, 2024 3:04 PM
To: Sharma, Shashank ; amd-gfx@lists.freedesktop.org
HI Shashank
We'll probably need a v8 with the null pointer crash fixed i.e. before
freeing the PT entries check for a valid entry before calling
amdgpu_vm_pt_free. The crash is seen with device memory allocators but
the system memory allocators are looking fine.
[ 127.255863] [drm] Using
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
*
Acked-by: Alex Deucher
On Mon, Mar 18, 2024 at 6:38 AM Lang Yu wrote:
>
> Ready now. Remove this workaround.
> This reverts commit 1a2bb3bb2a84f8364f0a8b338afa9b9025e1bcc0.
>
> Signed-off-by: Lang Yu
> Tested-by: Alan Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 3 ---
> 1 file
On Mon, Mar 18, 2024 at 4:47 AM Kurt Kartaltepe wrote:
>
> These checks prevent using amdgpu with the pcie=assign-busses parameter
> which will re-address devices from their acpi values.
>
> Signed-off-by: Kurt Kartaltepe
This will likely break multi-GPU functionality. The BDF values are
how
[AMD Official Use Only - General]
Reviewed-by: Leo Liu
> -Original Message-
> From: Dhume, Samir
> Sent: Friday, March 15, 2024 3:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Dhume, Samir ; Lazar, Lijo
> ; Wan, Gavin ; Liu, Leo
> ; Deucher, Alexander
> Subject: [PATCH v2 3/3]
On 3/18/24 6:50 AM, Srinivasan Shanmugam wrote:
Adds descriptions for 'new_context', 'srf_updates', and 'surface_count',
and removes the excess description for 'context'.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Function
parameter or
Adds descriptions for 'new_context', 'srf_updates', and 'surface_count',
and removes the excess description for 'context'.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4411: warning: Function
parameter or member 'new_context' not described in
Am 18.03.24 um 07:29 schrieb Sunil Khatri:
adev is a global data structure and isn't expected
to be NULL and hence removing the redundant adev
check from the devcoredump code.
CC: Dan Carpenter
Signed-off-by: Sunil Khatri
Suggested-by: Dan Carpenter
Acked-by: Christian König
---
Am 18.03.24 um 02:43 schrieb Ma, Jun:
Hi Christian,
On 3/15/2024 3:16 PM, Christian König wrote:
Am 15.03.24 um 06:17 schrieb Ma Jun:
Setting the rmmio pointer to NULL to fix the following
iounmap error and calltrace.
iounmap: bad address d0b3631f
Fixes: 923f7a82d2e1
From: Christian Koenig
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a DMA-fence object which
can be used to delay the
The idea behind this patch is to delay the freeing of PT entry objects
until the TLB flush is done.
This patch:
- Adds a tlb_flush_waitlist in amdgpu_vm_update_params which will keep the
objects that need to be freed after tlb_flush.
- Adds PT entries in this list in amdgpu_vm_ptes_update after
Ready now. Remove this workaround.
This reverts commit 1a2bb3bb2a84f8364f0a8b338afa9b9025e1bcc0.
Signed-off-by: Lang Yu
Tested-by: Alan Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
Am 15.03.24 um 20:08 schrieb Khatri, Sunil:
Thanks for pointing these. I do have some doubt and i raised inline.
On 3/15/2024 8:46 PM, Dan Carpenter wrote:
Hello Sunil Khatri,
Commit 42742cc541bb ("drm/amdgpu: add ring buffer information in
devcoredump") from Mar 11, 2024 (linux-next), leads
These checks prevent using amdgpu with the pcie=assign-busses parameter
which will re-address devices from their acpi values.
Signed-off-by: Kurt Kartaltepe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 3 ---
1 file changed, 3 deletions(-)
diff --git
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Tao Zhou
Sent: Monday, March 18, 2024 15:26
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao
Subject: [PATCH 3/3] drm/amdgpu: make reset method
Each RAS block has different requirement for gpu reset in poison
consumption handling.
Add support for mmhub RAS poison consumption handling.
v2: remove the mmhub poison support for kfd int v10.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 2 +-
Support the query for both gfxhub and mmhub, also replace
xcc_id with hub_inst.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 17 -
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 ++---
Add it for mmhub v1.8.
Signed-off-by: Tao Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 2 ++
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
adev is a global data structure and isn't expected
to be NULL and hence removing the redundant adev
check from the devcoredump code.
CC: Dan Carpenter
Signed-off-by: Sunil Khatri
Suggested-by: Dan Carpenter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 57 ++-
1 file
[AMD Official Use Only - General]
Got it. Thanks for reported that. Sent the patch for review.
Regards
Sunil khatri
-Original Message-
From: Dan Carpenter
Sent: Saturday, March 16, 2024 2:42 PM
To: Khatri, Sunil
Cc: Khatri, Sunil ; Koenig, Christian
; Deucher, Alexander ;
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