[AMD Official Use Only - General]
-Original Message-
From: Alex Deucher
Sent: Saturday, April 13, 2024 1:56 AM
To: Khatri, Sunil
Cc: Khatri, Sunil ; Deucher, Alexander
; Koenig, Christian ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 2/2] drm/amdgpu: Add support of gfx10
On Fri, Apr 12, 2024 at 5:47 PM Gao, Likun wrote:
>
> [AMD Official Use Only - General]
>
> From: Likun Gao
>
> Fix build issue on si dma to replace tmz flag
>
> Signed-off-by: Likun Gao
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
> 1 file changed, 1
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Gao, Likun
Sent: Friday, April 12, 2024 17:41
To: amd-gfx list
Subject: [PATCH] drm/amdgpu: replace sdma tmz flag on si dma
[AMD Official Use Only - General]
[AMD Official Use Only - General]
From: Likun Gao
Fix build issue on si dma to replace tmz flag
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
On 2024-04-12 16:22, Harry Wentland wrote:
>
>
> On 2024-04-12 12:26, Melissa Wen wrote:
>> On 04/12, Joshua Ashton wrote:
>>>
>>>
>>> On 4/11/24 3:26 PM, Melissa Wen wrote:
On 04/10, Joshua Ashton wrote:
> The comment here states "no OGAM in DPP since DCN1", yet that is not
>
On Fri, Apr 12, 2024 at 1:31 PM Khatri, Sunil wrote:
>
>
> On 4/12/2024 10:42 PM, Alex Deucher wrote:
>
> On Fri, Apr 12, 2024 at 1:05 PM Khatri, Sunil wrote:
>
> On 4/12/2024 8:50 PM, Alex Deucher wrote:
>
> On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
>
> Adding initial set of
On 2024-04-12 12:26, Melissa Wen wrote:
> On 04/12, Joshua Ashton wrote:
>>
>>
>> On 4/11/24 3:26 PM, Melissa Wen wrote:
>>> On 04/10, Joshua Ashton wrote:
The comment here states "no OGAM in DPP since DCN1", yet that is not
true.
Testing on an RX 7900XTX (dcn32), it
On 2024-04-12 11:31, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
On Fri, 12 Apr 2024 10:28:52 -0400
Leo Li wrote:
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
...
That begs the question of what can be
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 9ed46da14b9b9b2ad4edb3b0c545b6dbe5c00d39 Add linux-next specific
files for 20240412
Unverified Error/Warning (likely false positive, please contact us if
interested):
{standard input}:1011
To test RDMA using dummy driver on the system without NIC/RDMA
device, the get dma pages pass in null device pointer, skip the
dma map resource to avoid null device pointer access.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 33 +++-
1 file
When TTM failed to alloc VRAM, TTM evict BOs from VRAM to system memory
then retry the allocation, this currently skips the KFD BOs from the
same process because KFD requires all BOs are resident for user queues.
If TTM BO with TTM_PL_FLAG_CONTIGUOUS flag to alloc contiguous VRAM,
allow TTM evict
Bump the kfd ioctl minor version to delcare the contiguous VRAM
allocation flag support.
Signed-off-by: Philip Yang
---
include/uapi/linux/kfd_ioctl.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index
TTM allocate contiguous VRAM may takes more than 1 second to evict BOs
for larger size RDMA buffer. Because KFD restore bo worker reserves all
KFD BOs, then TTM cannot hold the remainning KFD BOs lock to evict them,
this may causes TTM failed to alloc contiguous VRAM.
Increase the KFD restore BO
If the BO pages pinned for RDMA is not contiguous on VRAM, evict it to
system memory first to free the VRAM space, then allocate contiguous
VRAM and then move it from system memory back to VRAM.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 ++-
RDMA device with limited scatter-gather capability requires physical
address contiguous VRAM buffer for RDMA peer direct access.
Add a new KFD alloc memory flag and store as new GEM bo alloc flag. When
pin this buffer object to export for RDMA peerdirect access, set
This patch series implement new KFD memory alloc flag for best effort contiguous
VRAM allocation, to support peer direct access RDMA device with limited
scatter-gather
dma capability.
Philip Yang (6):
drm/amdgpu: Support contiguous VRAM allocation
drm/amdgpu: Evict BOs from same process for
On 4/12/2024 10:42 PM, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 1:05 PM Khatri, Sunil wrote:
On 4/12/2024 8:50 PM, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
Adding initial set of registers for ipdump during
devcoredump starting with gfx10 gc registers.
On Fri, Apr 12, 2024 at 1:05 PM Khatri, Sunil wrote:
>
>
> On 4/12/2024 8:50 PM, Alex Deucher wrote:
> > On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
> >> Adding initial set of registers for ipdump during
> >> devcoredump starting with gfx10 gc registers.
> >>
> >> ip dump is triggered
On 4/12/2024 8:50 PM, Alex Deucher wrote:
On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
Adding initial set of registers for ipdump during
devcoredump starting with gfx10 gc registers.
ip dump is triggered when gpu reset happens via
devcoredump and the memory is allocated by each
ip
Add support of dumping the IP registers for
debugging purposes in devcoredump.
Signed-off-by: Sunil Khatri
---
.../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +++
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 127 +-
.../include/asic_reg/gc/gc_10_1_0_offset.h
Add the prototype for all the ips of different
asics and set them to NULL for now and based on
the need will keep adding the function for each
ip eventually.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
On Fri, Apr 12, 2024 at 12:49 PM Khatri, Sunil wrote:
>
>
> On 4/12/2024 8:50 PM, Alex Deucher wrote:
>
> I would split this into two patches, one to add the core
> infrastructure in devcoredump and one to add gfx10 support. The core
> support could be squashed into patch 1 as well.
>
>
> Sure
On 4/12/2024 8:50 PM, Alex Deucher wrote:
I would split this into two patches, one to add the core
infrastructure in devcoredump and one to add gfx10 support. The core
support could be squashed into patch 1 as well.
Sure would push the v3 with the changes.
Regards
Sunil
According to [1]:
```
DTN only logs 'pipe_count' instances of MPCC. However in some cases
there are different number of MPCC than DPP (pipe_count).
```
As DTN log still relies on pipe_count to print mpcc state, switch to
mpcc_count in all occurrences.
[1]
On 04/12, Joshua Ashton wrote:
>
>
> On 4/11/24 3:26 PM, Melissa Wen wrote:
> > On 04/10, Joshua Ashton wrote:
> > > The comment here states "no OGAM in DPP since DCN1", yet that is not
> > > true.
> > >
> > > Testing on an RX 7900XTX (dcn32), it actually does exist in hardware and
> > > works
On Fri, Apr 12, 2024 at 11:08 AM Pekka Paalanen
wrote:
>
> On Fri, 12 Apr 2024 10:28:52 -0400
> Leo Li wrote:
>
> > On 2024-04-12 04:03, Pekka Paalanen wrote:
> > > On Thu, 11 Apr 2024 16:33:57 -0400
> > > Leo Li wrote:
> > >
>
> ...
>
> > >> That begs the question of what can be nailed down
On Fri, Apr 12, 2024 at 10:00 AM Sunil Khatri wrote:
>
> Adding initial set of registers for ipdump during
> devcoredump starting with gfx10 gc registers.
>
> ip dump is triggered when gpu reset happens via
> devcoredump and the memory is allocated by each
> ip and is freed once the dump is
Reviewed-by: Alex Deucher
On Fri, Apr 12, 2024 at 7:25 AM Sunil Khatri wrote:
>
> Add vbios version in the devcoredump along with formatting
> the information with proper alignment.
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 9 +
> 1
[AMD Official Use Only - General]
Reviewed-by: Alex Deucher
From: Min, Frank
Sent: Friday, April 12, 2024 8:06 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Zhang, Hawking ;
Deucher, Alexander ; Koenig, Christian
Subject: [PATCH] drm/amdgpu: replace
On 2024-04-12 04:03, Pekka Paalanen wrote:
On Thu, 11 Apr 2024 16:33:57 -0400
Leo Li wrote:
On 2024-04-04 10:22, Marius Vlad wrote:
On Thu, Apr 04, 2024 at 09:59:03AM -0400, Harry Wentland wrote:
Hi all,
On 2024-04-04 06:24, Pekka Paalanen wrote:
On Wed, 3 Apr 2024 17:32:46 -0400
Convert a variable sized array from [1] to [].
v2: fix up a few more.
v3: integrate comments from Kees.
Tested-by: Jeff Johnson
Acked-by: Christian König (v1)
Signed-off-by: Alex Deucher
Cc: keesc...@chromium.org
---
drivers/gpu/drm/radeon/pptable.h | 10 +-
1 file changed, 5
Adding initial set of registers for ipdump during
devcoredump starting with gfx10 gc registers.
ip dump is triggered when gpu reset happens via
devcoredump and the memory is allocated by each
ip and is freed once the dump is complete by
devcoredump.
Signed-off-by: Sunil Khatri
---
Add the prototype for all the ips of different
asics and set them to NULL for now and based on
the need will keep adding the function for each
ip eventually.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
On 2024-04-12 00:16, Alex Deucher wrote:
> ping?
>
> On Fri, Mar 29, 2024 at 6:59 PM Alex Deucher
> wrote:
>>
>> This reverts commit b5abd7f983e14054593dc91d6df2aa5f8cc67652.
>>
>> This change breaks DSC on 4k monitors at 144Hz over USB-C.
>>
>> Closes:
Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.
So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 14
Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.
So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 14
Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.
Signed-off-by: Sunil Khatri
---
.../drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h | 4
.../amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h| 10 ++
2 files changed,
We need IH Ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
We need IH Ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
On Wed, Apr 10, 2024 at 3:37 AM Kees Cook wrote:
>
> On Mon, Apr 08, 2024 at 01:37:48PM -0400, Alex Deucher wrote:
> > Convert a variable sized array from [1] to [].
> >
> > v2: fix up a few more.
> >
> > Acked-by: Christian König (v1)
> > Signed-off-by: Alex Deucher
> > ---
> >
There are new control registers introduced in gfx10 used to configure
hardware watchpoints triggered by SMEM instructions:
SQ_WATCH{0,1,2,3}_{CNTL_ADDR_HI,ADDR_L}.
Those registers work in a similar way as the TCP_WATCH* registers
currently used for gfx9 and above.
This patch adds support to
[AMD Official Use Only - General]
From: Frank Min
Replace tmz flag into buffer flag to make it easier to understand and extend
Signed-off-by: Likun Gao
Signed-off-by: Frank Min
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c| 2 +-
Add vbios version in the devcoredump along with formatting
the information with proper alignment.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
Am 12.04.24 um 10:55 schrieb YiPeng Chai:
[Why]
After calling amdgpu_vram_mgr_reserve_range
multiple times with the same address, calling
amdgpu_vram_mgr_query_page_status will always
return -EBUSY.
From the second call to amdgpu_vram_mgr_reserve_range,
the same address will be added to
Am 03.04.24 um 09:06 schrieb YiPeng Chai:
[Why]
After calling amdgpu_vram_mgr_reserve_range
multiple times with the same address, calling
amdgpu_vram_mgr_query_page_status will always
return -EBUSY.
From the second call to amdgpu_vram_mgr_reserve_range,
the same address will be added to
[AMD Official Use Only - General]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chai, Thomas
> Sent: Friday, April 12, 2024 4:56 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chai, Thomas ; Zhang, Hawking
> ; Zhou1, Tao ; Li, Candice
> ; Wang, Yang(Kevin) ; Yang,
> Stanley ; Chai,
[AMD Official Use Only - General]
Ignore the series sent by mistake
-Original Message-
From: Sunil Khatri
Sent: Friday, April 12, 2024 2:30 PM
To: Deucher, Alexander ; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Khatri, Sunil
Subject: [PATCH 0/2] First set in IP dump
[AMD Official Use Only - General]
Ignore sent by mistake.
-Original Message-
From: Sunil Khatri
Sent: Friday, April 12, 2024 2:30 PM
To: Deucher, Alexander ; Koenig, Christian
Cc: amd-gfx@lists.freedesktop.org; Khatri, Sunil
Subject: [PATCH 2/2] drm/amdgpu: Add support of gfx10
We need IH Ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
We need IH Ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
Sunil Khatri (2):
drm:amdgpu: Enable IH RING1 for IH v6.0
drm:amdgpu: Enable IH RING1 for IH v6.1
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
--
2.34.1
Adding initial set of registers for ipdump during
devcoredump starting with gfx10 gc registers.
ip dump is triggered when gpu reset happens via
devcoredump and the memory is allocated by each
ip and is freed once the dump is complete by
devcoredump.
Signed-off-by: Sunil Khatri
---
Add the prototype for all the ips of different
asics and set them to NULL for now and based on
the need will keep adding the function for each
ip eventually.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
Adding infrastructure needed for ipdump along
with dumping gfx10 registers.
Sunil Khatri (2):
drm/amdgpu: add prototype to dump ip state
drm/amdgpu: Add support of gfx10 register dump
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1
[Why]
After calling amdgpu_vram_mgr_reserve_range
multiple times with the same address, calling
amdgpu_vram_mgr_query_page_status will always
return -EBUSY.
From the second call to amdgpu_vram_mgr_reserve_range,
the same address will be added to the reservations_pending
list again and is never
On Thu, Apr 11, 2024 at 12:25 PM Christian König
wrote:
> Am 11.04.24 um 05:28 schrieb xinhui pan:
> > Ensure there is no address overlapping.
> >
> > Reported-by: Vlad Stolyarov
> > Signed-off-by: xinhui pan
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
> > 1 file changed,
+Jann Horn for his thoughts
On Thu, Apr 11, 2024 at 12:25 PM Christian König
wrote:
> Am 11.04.24 um 05:28 schrieb xinhui pan:
> > Ensure there is no address overlapping.
> >
> > Reported-by: Vlad Stolyarov
> > Signed-off-by: xinhui pan
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |
Am 12.04.24 um 09:35 schrieb xinhui pan:
Verify the parameters of
amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place.
Reported-by: Vlad Stolyarov
Suggested-by: Christian König
Signed-off-by: xinhui pan
Reviewed-by: Christian König
---
Verify the parameters of
amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place.
Reported-by: Vlad Stolyarov
Suggested-by: Christian König
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 72 --
1 file changed, 46 insertions(+), 26
Am 12.04.24 um 08:47 schrieb xinhui pan:
Verify the parameters of
amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place.
Reported-by: Vlad Stolyarov
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 63 --
1 file changed, 39
Verify the parameters of
amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place.
Reported-by: Vlad Stolyarov
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 63 --
1 file changed, 39 insertions(+), 24 deletions(-)
diff --git
Signed-off-by: Stanley.Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 80b9642f2bc4..5f5bf0c26b1f 100644
---
63 matches
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