From: Aric Cyr
Change-Id: I1985922707a40f9ce5f6c01385bded36058206f2
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b
-by: Joseph Gravenor
Reviewed-by: Eric Yang
Acked-by: Bhawanpreet Lakha
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 82 +--
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h | 1 -
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 15 +++-
.../dc/clk_mgr/dcn21
functions.
Change-Id: I324a1ab2fe8212577b934e1e442498db83e79034
Signed-off-by: Jaehyun Chung
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules
From: Eric Yang
[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.
[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.
Change-Id:
lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.
Change-Id: I296933f24dff550330dd2693d348456d312d6930
Signed-off-by: Lewis Huang
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core
From: Anthony Koo
Change-Id: I98f27f86f683ed714241496f82254cb39023d8c7
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index
From: Joseph Gravenor
[why]
dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
so we will hang on reboot
[how]
add a guard for smu versions before SMU FW 55.21.0
Change-Id:
From: Michael Strauss
[WHY]
Number of audio endpoints wasn't updated from dcn20's 6 when created
[HOW]
Changed num_audio to 4 to match the correct sbios value
Change-Id: I2b79ef72762d6b4e5ff491c1ddf58847f96c973b
Signed-off-by: Michael Strauss
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet
-by: Aric Cyr
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/modules/freesync/freesync.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules
From: Eric Yang
[Why]
Previously SMU was giving us 0s for the clock table. Now they have valid
clock table. We should use theirs. Also, need to send SMU watermark
ranges for selecting optimal watermarks.
Change-Id: I59cefd343ddb7ebf00164854c6b43407e7c07c4e
Signed-off-by: Eric Yang
---
Change-Id: Ibb469a7eb5a084db89e5754bffebb558f35df331
Signed-off-by: Martin Leung
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 61 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 60 --
.../gpu/drm/amd
From: Dmytro Laktyushkin
Doing this allows us to split it for diffrent asics. This design will
be helpful for future Asciis.
Change-Id: I7f06c1ad9aa5ca30abf6953fc172edee75402862
Signed-off-by: Dmytro Laktyushkin
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 23 +++
gned-off-by: Vitaly Prosyak
Reviewed-by: Charlene Liu
Acked-by: Bhawanpreet Lakha
Acked-by: Vitaly Prosyak
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c| 1 +
drivers/gpu/drm/amd/display/include/ddc_service_types.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu
: I7b257552f251af5ad23091a7d6cfbb5e81bf4567
Signed-off-by: Joshua Aberback
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
Signed-off-by: Xiaodong Yan
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce
ers are programmed.
[How]
Pass the updated context down to the (enable|update)_writeback functions
so that they can use the correct watermarks when programming MMHUBBUB.
Change-Id: I36b9805b186cdca8416a449d866a08db423c44b6
Signed-off-by: Julian Parkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet La
implement for dcn2
Change-Id: I5525ee91093ed97235e1b85a70ea41e95240953b
Signed-off-by: Jun Lei
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 24 +++
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 --
.../g
From: Nikola Cornij
[why]
Output bitrate was mistakenly left out, causing corruption on some
DSC low resolution (such as 800x600) modes.
Change-Id: I47962603773d106a810a0b1b829dbd4168a53e47
Signed-off-by: Nikola Cornij
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
drivers
From: Eric Yang
[Why]
If 48mhz refclk is turned off during PSR, we will have issue doing
link training during detection.
[How]
Get out of PSR before detection
Change-Id: Ibe8c0a8caf787e1338c0cdbc4b9938f862290895
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
and remove
memset in fill_stream_properties_from_drm_display_mode()
Change-Id: I443a8d0346b97472e454a9c7f3822c4ee0ad3f85
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
1 file changed, 3 insertions
has completed processing
the command.
[How]
Wait for the DMCU FW to finish processing set pipe commands
Change-Id: I85d4bdbb2cddbf75ce9721a802dd6c37b6f7fa07
Signed-off-by: Josip Pavic
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 3
.
[How]
Reprogram the FMT in dcn20_program_pipe whenever a pipe is
newly enabled, or when its opp changes.
Change-Id: I2d30b47c7370091133e40d879592b55ee1a54382
Signed-off-by: Julian Parkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../drm/amd/display/dc/dcn20
: I2eecdbb4020c064573efb3c66764cb13e56ce7f4
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
.../amd/display/modules/inc/mod_info_packet.h | 3 +
.../display/modules/info_packet/info_packet.c | 98 +++
2 files changed, 101 insertions(+)
diff --git a/drivers/gpu/drm/amd
: I89d7c29153e14947b97bfee7d3b74c0814d7aa25
Signed-off-by: Joshua Aberback
Reviewed-by: Jaehyun Chung
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20
-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bdab3f7db732
Signed-off-by: Wayne Lin
Reviewed-by: Nicholas Kazlauskas
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Summary Of Changes
*fix compile warnings
*dcn21 fixes (audio, clk_mgr)
*DML output calculations update
Anthony Koo (1):
drm/amd/display: 3.2.52
Aric Cyr (4):
drm/amd/display: Update V_UPDATE whenever VSTARTUP changes
drm/amd/display: Properly round nominal frequency for SPD
for pixel formatter
(fmt dynamic bitdepth expansion control). Interface control
the FMT_DYNAMIC_EXP_EN bit, during crc capture keep
it disabled.
Change-Id: I096eaafad0fe90c98f943f2171dad8dade925d45
Signed-off-by: Robin Singh
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
---
.../drm/amd
: Ica31f3410b4b65b3f33540c6fe977a69e7aaf03b
Signed-off-by: Aric Cyr
Reviewed-by: Sivapiriyan Kumarasamy
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 7 +++
2 files changed, 10 insertions
.
Change-Id: I8e1fe85a66eaa757aec88e1a0360f1fa6cee3397
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers
From: Dmytro Laktyushkin
Currently pipe split may steal an existing ODM pipe depending on stream
sequence. This change prevents that from happening as easily.
Change-Id: I2e604894aaef2c782284fcc12d4e9a7381cf6eab
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Gary Kattan
Acked-by: Bhawanpreet
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry
From: Ramalingam C
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on
[Why]
HDCP is not fully finished, so we need to be able to
build and run the driver without it.
[How]
Add a Kconfig to toggle it
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git
[Why]
We need to read and write specific i2c and dpcd messages.
[How]
Created static functions for packing the dpcd and i2c messages for hdcp.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 40 ++-
1 file
[Why]
We need to update the hdcp display parameter whenever the link is
updated, so the next time there is an update to hdcp we have the
latest display info
[How]
Create a callback, and use this anytime there is a change in the link. This will
be used later by the dm.
Signed-off-by: Bhawanpreet
[Why]
This is needed for DP as DP can send us info using irq.
[How]
Check if irq bit is set on short pulse and call the
function that handles cpirq in amdgpu_dm_hdcp
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15
[Why]
All the HDCP transactions should be verified using PSP.
[How]
This patch calls psp with the correct inputs to verify the steps
of authentication.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 328
e hdcp
Then on plugin/resume/dpms: enable HDCP
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/g
From: Ramalingam C
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Pekka have completed the Weston DRM-backend review in
https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
and the UAPI for HDCP
needed for
the module
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 4 +
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 241 ++
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 61 +
3 files changed, 306
[Why]
We need to use HW state to set content protection to ENABLED.
This way we know that the link is encrypted from the HW side
[How]
Create a workqueue that queries the HW every ~2seconds, and sets it to
ENABLED or DESIRED based on the result from the hardware
Signed-off-by: Bhawanpreet Lakha
for such a solution.
NOTE: The 7 patches by Ramalingam have already been merged to drm-misc
but are required to apply the HDCP patches on amd-staging-drm-next
Bhawanpreet Lakha (13):
drm/amdgpu: psp HDCP init
drm/amdgpu: psp DTM init
drm/amd/display: Add HDCP module
drm/amd/display: add PSP block
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
drivers/gpu/drm/amd/amdgpu
[Why]
We don't support HDCP for pre RAVEN asics
[How]
Check if we are RAVEN+. Use this to attach the content_protection
property, this way usermode can't try to enable HDCP on pre DCN asics.
Also we need to update the module on hpd so guard it aswell
Signed-off-by: Bhawanpreet Lakha
Reviewed
[Why]
We need this to enable HDCP on linux, as we need events to interact
with the hdcp module
[How]
Add work queue to display manager and handle the creation and destruction
of the queue
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm
From: Ramalingam C
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Pekka have completed the Weston DRM-backend review in
From: Ramalingam C
Considering the significant size of hdcp related code in drm, all
hdcp related codes are moved into separate file called drm_hdcp.c.
v2:
Rebased.
v2:
Rebased.
Signed-off-by: Ramalingam C
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
From: Ramalingam C
Content protection property is created once and stored in
drm_mode_config. And attached to all HDCP capable connectors.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
Signed-off-by: Daniel Vetter
Link:
From: Ramalingam C
Existing functions for converting a 3bytes(be24) of big endian value
into u32 of little endian and vice versa are renamed as
s/drm_hdcp2_seq_num_to_u32/drm_hdcp_be24_to_cpu
s/drm_hdcp2_u32_to_seq_num/drm_hdcp_cpu_to_be24
Signed-off-by: Ramalingam C
Suggested-by: Daniel
From: Ramalingam C
On every hdcp revocation check request SRM is read from fw file
/lib/firmware/display_hdcp_srm.bin
SRM table is parsed and stored at drm_hdcp.c, with functions exported
for the services for revocation check from drivers (which
implements the HDCP authentication)
This patch
e hdcp
Then on plugin/resume/dpms: enable HDCP
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/g
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry
[Why]
HDCP is not fully finished, so we need to be able to
build and run the driver without it.
[How]
Add a Kconfig to toggle it
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git
[Why]
We need to read and write specific i2c and dpcd messages.
[How]
Created static functions for packing the dpcd and i2c messages for hdcp.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 40 ++-
1 file
[Why]
We need to use HW state to set content protection to ENABLED.
This way we know that the link is encrypted from the HW side
[How]
Create a workqueue that queries the HW every ~2seconds, and sets it to
ENABLED or DESIRED based on the result from the hardware
Signed-off-by: Bhawanpreet Lakha
From: Ramalingam C
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Pekka have completed the Weston DRM-backend review in
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
drivers/gpu/drm/amd/amdgpu
[Why]
This is needed for DP as DP can send us info using irq.
[How]
Check if irq bit is set on short pulse and call the
function that handles cpirq in amdgpu_dm_hdcp
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15
for such a solution.
NOTE: The 7 patches by Ramalingam have already been merged to drm-misc
but are required to apply the HDCP patches on amd-staging-drm-next
Bhawanpreet Lakha (13):
drm/amdgpu: psp HDCP init
drm/amdgpu: psp DTM init
drm/amd/display: Add HDCP module
drm/amd/display: add PSP block
[Why]
We need this to enable HDCP on linux, as we need events to interact
with the hdcp module
[How]
Add work queue to display manager and handle the creation and destruction
of the queue
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm
From: Ramalingam C
On every hdcp revocation check request SRM is read from fw file
/lib/firmware/display_hdcp_srm.bin
SRM table is parsed and stored at drm_hdcp.c, with functions exported
for the services for revocation check from drivers (which
implements the HDCP authentication)
This patch
From: Ramalingam C
Content protection property is created once and stored in
drm_mode_config. And attached to all HDCP capable connectors.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
Signed-off-by: Daniel Vetter
Link:
[Why]
We need to update the hdcp display parameter whenever the link is
updated, so the next time there is an update to hdcp we have the
latest display info
[How]
Create a callback, and use this anytime there is a change in the link. This will
be used later by the dm.
Signed-off-by: Bhawanpreet
[Why]
We don't support HDCP for pre RAVEN asics
[How]
Check if we are RAVEN+. Use this to attach the content_protection
property, this way usermode can't try to enable HDCP on pre DCN asics.
Also we need to update the module on hpd so guard it aswell
Signed-off-by: Bhawanpreet Lakha
Reviewed
From: Ramalingam C
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Pekka have completed the Weston DRM-backend review in
https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
and the UAPI for HDCP
[Why]
All the HDCP transactions should be verified using PSP.
[How]
This patch calls psp with the correct inputs to verify the steps
of authentication.
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 328
From: Ramalingam C
Considering the significant size of hdcp related code in drm, all
hdcp related codes are moved into separate file called drm_hdcp.c.
v2:
Rebased.
v2:
Rebased.
Signed-off-by: Ramalingam C
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
From: Ramalingam C
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on
needed for
the module
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 4 +
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 241 ++
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 61 +
3 files changed, 306
From: Ramalingam C
Existing functions for converting a 3bytes(be24) of big endian value
into u32 of little endian and vice versa are renamed as
s/drm_hdcp2_seq_num_to_u32/drm_hdcp_be24_to_cpu
s/drm_hdcp2_u32_to_seq_num/drm_hdcp_cpu_to_be24
Signed-off-by: Ramalingam C
Suggested-by: Daniel
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
v2: Fix formatting
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 189 +-
drivers/gpu/drm/amd/amdgpu
Dali is a new asic revision based on raven2
Add the ID and ASICREV_IS_DALI define
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
[Why]
we only want the lowest voltage to be available for dali.
[How]
Use the get_highest_allowed_voltage_level function
to return 0 for dali
Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4
1 file changed, 4 insertions
Dali is a new asic based on raven. This patch adds the asic ID and
support for it in the display core.
Bhawanpreet Lakha (2):
drm/amd/display: add Asic ID for Dali
drm/amd/display: Implement voltage limitation for dali
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4
drivers/gpu
[Why]
HDCP is not fully finished, so we need to be able to
build and run the driver without it.
[How]
Add a Kconfig to toggle it
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display
: Ide8dbbb5877c83c4aac576bb4bd3e0b9cbd9f63e
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 +
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 65 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 7 +-
3 files changed, 73 insertions(+), 15 deletions(-)
diff
[Why]
We need to update the hdcp display parameter whenever the link is
updated, so the next time there is an update to hdcp we have the
latest display info
[How]
Create a callback, and use this anytime there is a change in the link. This will
be used later by the dm.
Signed-off-by: Bhawanpreet
e hdcp
Then on plugin/resume/dpms: enable HDCP
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amd
[Why]
This is needed for DP as DP can send us info using irq.
[How]
Check if irq bit is set on short pulse and call the
function that handles cpirq in amdgpu_dm_hdcp
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++
1 file changed, 15
From: Ramalingam C
Existing functions for converting a 3bytes(be24) of big endian value
into u32 of little endian and vice versa are renamed as
s/drm_hdcp2_seq_num_to_u32/drm_hdcp_be24_to_cpu
s/drm_hdcp2_u32_to_seq_num/drm_hdcp_cpu_to_be24
Signed-off-by: Ramalingam C
Suggested-by: Daniel
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 188 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 17 ++
drivers/gpu/drm/amd/amdgpu
needed for
the module
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 4 +
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 241 ++
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h| 61 +
3 files changed, 306 insertions(+)
create mode
From: Ramalingam C
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on
: I1f425bca6eb1139a4b0fe808c455df148ca0925e
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index
From: Ramalingam C
On every hdcp revocation check request SRM is read from fw file
/lib/firmware/display_hdcp_srm.bin
SRM table is parsed and stored at drm_hdcp.c, with functions exported
for the services for revocation check from drivers (which
implements the HDCP authentication)
This patch
[Why]
We need to read and write specific i2c and dpcd messages.
[How]
Created static functions for packing the dpcd and i2c messages for hdcp.
Signed-off-by: Bhawanpreet Lakha
---
.../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c| 40 ++-
1 file changed, 39 insertions(+), 1
From: Ramalingam C
drm function is defined and exported to update a connector's
content protection property state and to generate a uevent along
with it.
Pekka have completed the Weston DRM-backend review in
https://gitlab.freedesktop.org/wayland/weston/merge_requests/48
and the UAPI for HDCP
[Why]
We need this to enable HDCP on linux, as we need events to interact
with the hdcp module
[How]
Add work queue to display manager and handle the creation and destruction
of the queue
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30
[Why]
All the HDCP transactions should be verified using PSP.
[How]
This patch calls psp with the correct inputs to verify the steps
of authentication.
Signed-off-by: Bhawanpreet Lakha
---
.../drm/amd/display/modules/hdcp/hdcp_psp.c | 328 ++
.../drm/amd/display/modules/hdcp
DTM is the display topology manager. This is needed to communicate with
psp about the display configurations.
This patch adds
-Loading the firmware
-The functions and definitions for communication with the firmware
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu
From: Ramalingam C
DRM API for generating uevent for a status changes of connector's
property.
This uevent will have following details related to the status change:
HOTPLUG=1, CONNECTOR= and PROPERTY=
Pekka have completed the Weston DRM-backend review in
From: Ramalingam C
Considering the significant size of hdcp related code in drm, all
hdcp related codes are moved into separate file called drm_hdcp.c.
v2:
Rebased.
v2:
Rebased.
Signed-off-by: Ramalingam C
Suggested-by: Daniel Vetter
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
From: Ramalingam C
Content protection property is created once and stored in
drm_mode_config. And attached to all HDCP capable connectors.
Signed-off-by: Ramalingam C
Reviewed-by: Daniel Vetter
Acked-by: Dave Airlie
Signed-off-by: Daniel Vetter
Link:
for such a solution.
NOTE: The 7 patches by Ramalingam have already been merged to drm-misc
but are required to apply the HDCP patches on amd-staging-drm-next
Bhawanpreet Lakha (13):
drm/amdgpu: psp HDCP init
drm/amdgpu: psp DTM init
drm/amd/display: Add HDCP module
drm/amd/display: add PSP block
From: Charlene Liu
[Description]
1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update)
2. using memory type to convert UMC's MCLK to Yclk.
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dce110
From: Nikola Cornij
[why]
The requirement has been clarified and only DSC 4:2:2 Native has to
be disabled.
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index
Add tracking to HW access during destructor to make future issues
easier to pinpoint, and block access to prevent hangs.
Signed-off-by: Jun Lei
Reviewed-by: Yongqiang Sun
Acked-by: Bhawanpreet Lakha
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 3 +++
drivers/gpu/drm/amd/display/dc/core
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