Separate those ASIC specific settings from common helpers.
Signed-off-by: Evan Quan
Change-Id: Ie3224b8719d48c6e6936b738df379959bd1df4ad
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 1 -
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 16 +---
2 files changed, 13
The pptable in the vbios is fully ready. The related workarounds
in driver are not needed any more.
Signed-off-by: Evan Quan
Change-Id: I2549cd1acd6eebde361ed8e27d5631bd57644e52
--
v1->v2:
- drop unrelated and unnecessary changes(Alex, Guchun)
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_
Add a new member to flag where to get the pptable. So that,
we can separate those ASIC specific ones from common helpers.
Signed-off-by: Evan Quan
Change-Id: I814db70b5cedc225578bcb4988663de7dcf535af
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 31
drivers/gpu/drm/amd/pm
Enable 3794 pptable support for SMU13.0.0.
Signed-off-by: Evan Quan
Change-Id: Ia208531c9eb96611b6136975bcbd8d27007b9e14
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b/drivers
Missing SetMGpuFanBoostLimitRpm mapping leads to loading failure for SMU
13.0.7.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I2ea606ad5089b2612069614349c3a228406ef928
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git
To fit the latest 78.53 PMFW.
Signed-off-by: Evan Quan
Change-Id: I16b36a3c209c82fc2d48325f7e6ef5a702678782
---
.../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 31 +++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +-
2 files changed, 19 insertions(+), 14 deletions(-)
diff
Without these, potential memory leak may be induced.
Signed-off-by: Evan Quan
Change-Id: Ied7cd204d44d739dece11774c9d29e7a192fd341
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
2 files changed, 4 insertions(+)
diff
To avoid any potential memory leak.
Signed-off-by: Evan Quan
Change-Id: Ide94e85d862c10aae93e04e3ce64c0451e5e1570
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers
Some stability issues were reported with these features.
Signed-off-by: Evan Quan
Change-Id: I5fccae63bd530d6ff9e4167bb1c44319830806f9
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu
Add support for 3715 softpptable.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: Iae7360ce853a6b5fde38025d528640c9b88fc54c
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu
The feature is ready with latest firmwares.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I4907ef8c96eb8933db01818d7431afb3778d1afd
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu
And get the version bumped to 0x2C to match the latest PMFW.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: Ie4bc8fa0831ae6d1735c2dca27331ff6f6229e30
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
From: Jack Xiao
mes self test rely on vm mapping, move it after
drm sched re-started so that vm mapping can work
during gpu reset.
Signed-off-by: Jack Xiao
Acked-and-tested-by: Evan Quan
Change-Id: Ib202c04d86191ca47da90d27c2a8cf9e7c8e6732
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3
This extra call trace dump comes out in every gpu reset.
And it gives people a wrong impression that something
went wrong. Although actually there was not.
Signed-off-by: Evan Quan
Change-Id: I884af405b6b3cd52b9024408a21fd39811a01f4d
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
1 file
fail issue for
smu13")
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: I4e93f08f930ebeb1ed134307e62b4c53a9885066
--
v1->v2:
- limit the impacts to legacy ASICs(Hawking)
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ---
1 file changed
To fit the latest 78.49.0 PMFW. Also, bump the version
to 0x2B.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: Icbf79cca25dbfd2850425e9e4afbb77cf1ff28db
---
.../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h| 4 ++--
drivers/gpu/drm/amd/pm
Only PP_MP1_STATE_UNLOAD is supported for now. For other mp1 state, we
should just ignore it. Otherwise, there will be errors coming out.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: I15427d6daf14d5c82a6e7f9d32fdea60a80fd0ec
---
.../drm/amd/pm/swsmu
The feature is ready with latest firmwares.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: I581a7aae2618134a9d196cd383cdabf3516efec0
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers
ect the return value to reflect the real result of disablement.
Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display
Core")
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: If87d4cf76f6cfb36d607f051ff32f9c7870b4d6d
--
v1->v2:
- correct the hash tag
ect the return value to reflect the real result of disablement.
Fixes: e40fcd4a ("drm/amd/display: add DCN32/321 specific files for Display
Core")
Cc:
Signed-off-by: Evan Quan
Change-Id: If87d4cf76f6cfb36d607f051ff32f9c7870b4d6d
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c |
And bump the version to 0x2A.
Signed-off-by: Evan Quan
Change-Id: I2b66b9a289177a979201fca2056ff11e0b81f2bb
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +-
2 files changed, 3 insertions(+), 2
Enable VR0 Hot support for SMU 13.0.0.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: I11a642033d6e0885877cf48c1f1e07f30de4622e
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13
Update GFX11 cs related settings.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: If99a46ef4178fb4cd686008038923d3b15efa452
---
drivers/gpu/drm/amd/amdgpu/clearstate_gfx11.h | 307 +-
1 file changed, 158 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm
The feature is ready with latest PMFW and IFWI.
Signed-off-by: Evan Quan
Change-Id: I0b1ea6a32bc092eec4b95118a1442597688ee8d0
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
b
Enable BAMACO reset support for SMU 13.0.0.
Signed-off-by: Evan Quan
Change-Id: I67696671c216790a0b6d5b84f7d4b430d734ac3c
--
v1->v2:
- maximum code sharing around smu13.0.0 and smu13.0.7
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 3 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_pp
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan
Change-Id: Ib3b0e106ff43ad49f0f815e6eeb5c756b6bf4550
--
v1->v2:
- support LTR disabled scenario(Lijo)
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |
PMFW will handle that properly. Driver involvement may cause some
unexpected issues.
Signed-off-by: Evan Quan
Change-Id: I77da7d894485a3ac6a1a956e4d2605d0bc730c25
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git
m
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c:33:
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h:55: note: this is the location of
the previous definition
55 | #define MAX_PCIE_CONF 3
Signed-off-by: Evan Quan
Change-Id: Iacc4ff4007b74d5db54c1e66cb237e55b70975b0
---
drivers/gpu/
Drop those redundant declarations in smu_v13_0.h.
Signed-off-by: Evan Quan
Change-Id: I54e43d072235f006b937878c126bcd8ef81ea6f7
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
b
Fulfill the interfaces for mode1 reset related.
Signed-off-by: Evan Quan
Change-Id: I03bb1f7f3b88bf304a188bb6939c043805df8f10
--
v1->v2:
- drop invalid psp alive check(Lijo)
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 1 +
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|
Make sure the clockgating feature is supported before action.
Otherwise, the feature may be disabled unexpectedly on enablement
request.
Signed-off-by: Evan Quan
Change-Id: Ie20e6c5975c2a0af40dc52189e3df97161300117
---
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 10 --
1 file changed, 8
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan
Change-Id: Ib3b0e106ff43ad49f0f815e6eeb5c756b6bf4550
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c| 109
Suppress the compile warning below:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:1292
gfx_v11_0_rlc_backdoor_autoload_copy_ucode() warn: should '1 << id' be a 64 bit
type?
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Evan Quan
Cha
prototype for function 'gfx_v11_0_rlc_stop' [-Wmissing-prototypes]
Signed-off-by: Evan Quan
Change-Id: I679436c91cb98afb9fcbef8942fd90a17e5234b5
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 12 ++--
2 files changed
ed, which
can lead to unaligned accesses [-Wunaligned-access]
Signed-off-by: Evan Quan
Change-Id: I855062e987effd563ccc09336caad75f02751bb6
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h | 9 ++---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h | 9 ++---
drivers/gpu/dr
To fit the latest 78.39.0 PMFW.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: Ie8280606729fa8b80a0abf1bc94f16c4b06191d4
--
v1->v2:
- coding style fixes(Hawking)
---
.../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h | 6 ++
drivers/gpu/drm/amd/pm/swsmu/
The feature is ready with latest 78.39.0 PMFW.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I99096e23ed7ebcd5aaada84b7f11ad9e3d3cd8b8
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu
There is some problem with average frequency reading. Thus, we
switch to the target frequency reading instead.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I50fd370bbca68159cb1a4f69b05232f907af2bb9
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
1 file
Suppress two compile warnings about "no previous prototype".
Reported-by: kernel test robot
Signed-off-by: Evan Quan
Change-Id: I74d029c6ebd8bf6bc08edada7a992d04786330d8
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc21.c| 1
With the latest vbios, the memory temp reading is working.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I3b4679f03e5ff7cf8e0b68c095d210e608149fcb
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
Enable OOB Monitor and SOC CG which are ready since 78.38.0.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: I0d7334106917ac83fff2b673ec7e9eb096089afe
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff
To align with 78.37.0 and later PMFWs.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I17c3a6b466c921cb5ffe5025a94023fae478c80e
---
.../inc/pmfw_if/smu13_driver_if_v13_0_0.h | 22 +--
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +-
2 files changed, 11
Since PMFW will handle this properly. Driver involvement is
unnecessary.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I19be26eed090d57040553f5cdff9534072f08106
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm
To better match with the pptable_id settings from VBIOS.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Acked-by: Alex Deucher
Change-Id: I3379443067a5df3a2fb04ff1bc48e8c8f28e1c66
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 47 ++-
1 file changed, 35 insertions
Enable MP0CLK DPM and FW Dstate since they are already supported
by latest 78.36.0 PMFW.
Signed-off-by: Evan Quan
Reviewed-by: Hawking Zhang
Change-Id: I75b6129dab509a51ccaf92bbc0b094eae41ea20f
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +++
1 file changed, 3 insertions
d than 'struct smu_13_0_0_overdrive_table' and is usually due to
'struct smu_13_0_0_powerplay_table' being packed,
which can lead to unaligned accesses [-Wunaligned-access]
Reported-by: kernel test robot
Signed-off-by: Evan Quan
Change-Id: Ibba9dbfcc6440d0bdf0fbe0534ce6a82ab6d5d10
---
drivers/g
Fix the compile warning below:
drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.c:1641
kv_get_acp_boot_level() warn: always true condition '(table->entries[i]->clk >=
0) => (0-u32max >= 0)'
Reported-by: kernel test robot
CC: Alex Deucher
Signed-off-by: Evan
Fix the compile warning below:
drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.c:1641
kv_get_acp_boot_level() warn: always true condition '(table->entries[i]->clk >=
0) => (0-u32max >= 0)'
Reported-by: kernel test robot
CC: Alex Deucher
Signed-off-by: Evan
e.
Fixes: 3712e7a49459 ("drm/amd/pm: unified lock protections in amdgpu_dpm.c")
Reported-by: Paul Menzel
Reported-by: Arthur Marsh
Link: https:
//lore.kernel.org/all/9e689fea-6c69-f4b0-8dee-32c4cf7d8...@molgen.mpg.de/
BugLink: https: //gitlab.freedesktop.org/drm/amd/-/issues/1957
Signe
By placing those unrelated code outside of adev->pm.mutex
protections or restructuring the call flow, we can eliminate
the deadlock issue. This comes with no real logics change.
Fixes: 3712e7a49459 ("drm/amd/pm: unified lock protections in amdgpu_dpm.c")
Signed-off-by: Evan Qu
With this, we can support more CG flags.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Reviewed-by: Hawking Zhang
Change-Id: Iccf13c2f9c570ca6a4654291fc4876556125c3b8
--
v1->v2:
- amdgpu_debugfs_gca_config_read: add a new rev to
support CG flag upper 32 bits(Alex)
v2->v3:
- use
With this, we can support more CG flags.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: Iccf13c2f9c570ca6a4654291fc4876556125c3b8
--
v1->v2:
- amdgpu_debugfs_gca_config_read: add a new rev to
support CG flag upper 32 bits(Alex)
---
drivers/gpu/drm/amd/amdgpu/amdgp
Instead of having an interface for every reset method, we replace them
with a new interface which can support all reset methods.
Signed-off-by: Evan Quan
Change-Id: I4c8a7121dd65c2671085673dd7c13cf7e4286f3d
---
drivers/gpu/drm/amd/amdgpu/aldebaran.c| 2 +-
drivers/gpu/drm/amd/amdgpu
They are totally redundant. The checks before them can guard
they cannot be NULL.
Signed-off-by: Evan Quan
Change-Id: I9f31734f49a8093582fc321ef3d93233946006e3
---
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 182 ++
.../amd/pm/powerplay/hwmgr/hardwaremanager.c | 42
Since the "smu->ppt_funcs" was already well installed at early_init phase,
the checks afterwards make nonsense.
Signed-off-by: Evan Quan
Change-Id: I07a945035a87b23032e4911bba768edacbd5e65a
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 +---
drivers/gpu/drm
As it can be covered by the "!adev->pm.dpm_enabled" check. As long as
"adev->pm.dpm_enabled != NULL", "pp_funcs != NULL" can be also guarded.
Signed-off-by: Evan Quan
Change-Id: Iec801f18a0069ad5fd384c4133016977fb2b67e8
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
By setting pm_enabled as false for non pp_one_vf sriov case,
we can avoid the check for (amdgpu_sriov_vf(adev) &&
!amdgpu_sriov_is_pp_one_vf(adev)) in every routine.
Signed-off-by: Evan Quan
Change-Id: I3859529183cd26dce98c57dc87eab5273ecc949b
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_sm
Those gpu reset APIs can be granted when:
- System is up and dpm features are enabled.
- System is under resuming and dpm features are not yet enabled.
Under such scenario, the PMFW is already alive and can support
those gpu reset functionalities.
Signed-off-by: Evan Quan
Change-Id
Make sure the interface get granted only when amdgpu_dpm enabled.
Signed-off-by: Evan Quan
Change-Id: Ia1d1123470fab89b41b24ea80dcb319570aa7438
---
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 6 ++
drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c | 3 ---
2 files changed, 6
Instead of checking this in every instance(framework), moving that check to
amdgpu_dpm.c is more proper. And that can make code clean and tidy.
Signed-off-by: Evan Quan
Change-Id: I2f83a3b860e8aa12cc86f119011f520fbe21a301
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +-
drivers/gpu
adev->pm.dpm_enabled instead of hwmgr->pm_en can better reflect
whether the dpm features are actually enabled.
Signed-off-by: Evan Quan
Change-Id: I6896dcee19bb473d26115cdcb12b6efd554b30f9
---
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c| 39 +++---
drivers/gpu/drm/amd/pm/legacy-dpm/si
As smu->pm_enabled is a prerequisite for adev->pm.dpm_enabled.
So, with adev->pm.dpm_enabled set, it can be guarded that
smu->pm_enabled is also set. Thus the extra check for
"!smu->pm_enabled" is totally unnecessary.
Signed-off-by: Evan Quan
Change-Id: I6ff67137d447e6a
Drop those interfaces which never get used.
Signed-off-by: Evan Quan
Change-Id: Ia22d395145a1003faca5ac792dca6a30ef2cae54
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 4
Drop those members which get never used.
Signed-off-by: Evan Quan
Change-Id: Iec70ad1dfe2059be26843f378588e6c894e9cae8
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm
For Cyan Skillfish and Renoir, there is no interface provided by PMFW
to retrieve the enabled features. So, we assume all features are enabled.
Fixes: 7ade3ca9cdb5 ("drm/amd/pm: correct the usage for 'supported' member of
smu_feature structure")
Signed-off-by: Evan Quan
Fulfill the implementations for DriverSmuConfig setting on Navi1x.
Signed-off-by: Evan Quan
Change-Id: I244766a893b4070dfdf171451f6338d33572ec1d
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 50 +++
1 file changed, 50 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm
MMHUB PG needs to be disabled for Picasso for stability reasons.
Signed-off-by: Evan Quan
Change-Id: Iea0ec757582a764ab5a000d7cc411fb814ffb19f
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU
specific stability issues.
Signed-off-by: Evan Quan
Change-Id: I172c6429c54253788dbf28f7acf877375f2bfc5b
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff
Fulfill the implementations for DriverSmuConfig setting on Sienna_Cichlid.
Signed-off-by: Evan Quan
Change-Id: Ic519c8d4fcfeefdda79ba9ed01b235824d76e40f
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 54 +++
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/amd
Enable the support for DriverSmuConfig table on Navi1x and
Sienna_Cichlid.
Signed-off-by: Evan Quan
Change-Id: Ie510f8b06b7a4910b1574b6e9affa875805ef868
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 9 +
.../gpu
For Some ASICs, with the PMFW default settings, we may see the
power consumption reported via metrics table is "Very Erratic".
With the socket power alpha filter set as 10/100ms, we can correct
that issue.
Signed-off-by: Evan Quan
Change-Id: Ia352579e1cc7a531cb1de5c835fe5bf132d5dd20
--
Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige
Goby.
Signed-off-by: Evan Quan
Change-Id: I74fdbcf2cfa11f97ae16e4921449ab7cdb7e43c9
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 26 +++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.h | 8 ++
2
As there is no internal cache for enabled ppfeatures now. Thus the 2nd
parameter will be not needed any more.
Signed-off-by: Evan Quan
Change-Id: I0c1811f216c55d6ddfabdc9e099dc214c21bdf2e
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
drivers/gpu/drm/amd/pm/swsmu/inc
As the enabled ppfeatures are just retrieved ahead. We can use
that directly instead of retrieving again and again.
Signed-off-by: Evan Quan
Change-Id: I08827437fcbbc52084418c8ca6a90cfa503306a9
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +-
1 file changed, 9 insertions(+), 1
related DPM features. All those are performed without driver's
notice.
Also considering driver does not actually interact with PMFW such
frequently, the benefit brought by such cache is very limited.
Signed-off-by: Evan Quan
Change-Id: I20ed58ab216e930c7a5d223be1eb99146889f2b3
---
drivers
Use uint64_t instead of an array of uint32_t. This can avoid
some non-necessary intermediate uint32_t -> uint64_t conversions.
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Change-Id: I4e217357203a23440f058d7e25f55eaebd15c5ef
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |
The supported features should be retrieved just after EnableAllDpmFeatures
message
complete. And the check(whether some dpm feature is supported) is only needed
when we
decide to enable or disable it.
Signed-off-by: Evan Quan
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
drivers
Instead of having two which do the same thing.
Signed-off-by: Evan Quan
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f
--
v1->v2:
- use SMU IP version check rather than an asic type check(Alex)
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 2 +-
.../gpu/drm/amd/pm/swsmu/sm
As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.
Signed-off-by: Evan Quan
Acked-by: Alex Deucher
Change-Id: I9e845ba84dd45d0826506de44ef4760fa851a516
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
As there is no internal cache for enabled ppfeatures now. Thus the 2nd
parameter will be not needed any more.
Signed-off-by: Evan Quan
Change-Id: I0c1811f216c55d6ddfabdc9e099dc214c21bdf2e
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
drivers/gpu/drm/amd/pm/swsmu/inc
As the enabled ppfeatures are just retrieved ahead. We can use
that directly instead of retrieving again and again.
Signed-off-by: Evan Quan
Change-Id: I08827437fcbbc52084418c8ca6a90cfa503306a9
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +-
1 file changed, 9 insertions(+), 1
related DPM features. All those are performed without driver's
notice.
Also considering driver does not actually interact with PMFW such
frequently, the benefit brought by such cache is very limited.
Signed-off-by: Evan Quan
Change-Id: I20ed58ab216e930c7a5d223be1eb99146889f2b3
---
drivers
The supported features should be retrieved just after EnableAllDpmFeatures
message
complete. And the check(whether some dpm feature is supported) is only needed
when we
decide to enable or disable it.
Signed-off-by: Evan Quan
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
drivers
Instead of having two which do the same thing.
Signed-off-by: Evan Quan
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 2 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 6 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 6
As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.
Signed-off-by: Evan Quan
Change-Id: I9e845ba84dd45d0826506de44ef4760fa851a516
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm
The sub-routine(amdgpu_gfx_off_ctrl) tried to obtain the lock
adev->pm.mutex which was actually hold by amdgpu_dpm_force_performance_level.
A deadlock happened then.
Signed-off-by: Evan Quan
Change-Id: Id692829381dedc6380f5464d74107d696f7abca1
---
drivers/gpu/drm/amd/pm/amdgpu_dpm.c |
The existing way cannot handle Beige Goby well as a different
PPTable data structure(PPTable_beige_goby_t instead of PPTable_t)
is used there.
Signed-off-by: Evan Quan
Change-Id: I02208c011e93c4d37769bd022e65e9084faa97e4
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 +++---
1
As there is no internal cache for enabled ppfeatures now. Thus the 2nd
parameter will be not needed any more.
Signed-off-by: Evan Quan
Change-Id: I0c1811f216c55d6ddfabdc9e099dc214c21bdf2e
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
drivers/gpu/drm/amd/pm/swsmu/inc
As the enabled ppfeatures are just retrieved ahead. We can use
that directly instead of retrieving again and again.
Signed-off-by: Evan Quan
Change-Id: I08827437fcbbc52084418c8ca6a90cfa503306a9
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +-
1 file changed, 9 insertions(+), 1
related DPM features. All those are performed without driver's
notice.
Also considering driver does not actually interact with PMFW such
frequently, the benefit brought by such cache is very limited.
Signed-off-by: Evan Quan
Change-Id: I20ed58ab216e930c7a5d223be1eb99146889f2b3
---
drivers
As it has exactly the same value as the 'enabled' member and also do
the same thing.
Signed-off-by: Evan Quan
Change-Id: I07c9a5ac5290cd0d88a40ce1768d393156419b5a
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
.../gpu/drm/amd/pm
Use uint64_t instead of an array of uint32_t. This can avoid
some non-necessary intermediate uint32_t -> uint64_t conversions.
Signed-off-by: Evan Quan
Change-Id: I4e217357203a23440f058d7e25f55eaebd15c5ef
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/pm/sw
Instead of having two which do the same thing.
Signed-off-by: Evan Quan
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f
---
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 2 +-
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 6 +-
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 6
As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.
Signed-off-by: Evan Quan
Change-Id: I9e845ba84dd45d0826506de44ef4760fa851a516
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm
As all those APIs are already protected either by adev->pm.mutex
or smu->message_lock.
Signed-off-by: Evan Quan
Change-Id: I1db751fba9caabc5ca1314992961d3674212f9b0
--
v1->v2:
- optimize the "!smu_table->hardcode_pptable" check(Guchun)
- add the lock protection(a
Suppress the warning below on building htmldocs:
drivers/gpu/drm/amd/include/amd_shared.h:103: warning: Enum value
'AMD_IP_BLOCK_TYPE_NUM' not described in enum 'amd_ip_block_type'
Fixes: 6ee27ee27ba8 ("drm/amd/pm: avoid duplicate powergate/ungate setting")
Signed-off-by: Evan Quan
As all those related APIs are already well protected by adev->pm.mutex.
Signed-off-by: Evan Quan
Change-Id: I36426791d3bbc9d84a6ae437da26a892682eb0cb
---
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 278 +++---
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h | 1 -
2 fi
As all those related APIs are already well protected by adev->pm.mutex.
Signed-off-by: Evan Quan
Change-Id: Ia2c752ff22e8f23601484f48b66151cfda8c01b5
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
.../gpu/drm/amd/pm/swsmu/sm
As those APIs related are already well protected by adev->pm.mutex.
Signed-off-by: Evan Quan
Change-Id: I8a7d8da5710698a98dd0f7e70c244be57474b573
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 -
.../gpu/drm/amd/pm/swsmu/sm
As all those related APIs are already well protected by
adev->pm.mutex and smu->message_lock.
Signed-off-by: Evan Quan
Change-Id: I20974b2ae68d63525bc7c7f406fede2971c5fecc
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 -
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu
201 - 300 of 1244 matches
Mail list logo