[PATCH] drm/amdgpu: update the domain flags for dumb buffer creation

gpu: use generic fb helpers instead of setting up AMD own's.") Signed-off-by: Evan Quan Reviewed-by: Christian König Change-Id: I403bf7a0b265c564b5f3a3343999670e5eb87ca6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/d

[PATCH V3] drm/amd/pm: avoid duplicate powergate/ungate setting

-by: Evan Quan Tested-by: Borislav Petkov -- v1->v2: - typo fix and add link for the issue referred in commit message(Paul/Boris) - update the data type to uint32_t(Paul) - better Macro naming(Lijo) v2->v3: - stick to original logics on handling unmentioned IP blocks(Lijo) --- d

[PATCH] drm/amd/pm: avoid duplicate powergate/ungate setting

-by: Evan Quan Tested-by: Borislav Petkov -- v1->v2: - typo fix and add link for the issue referred in commit message(Paul/Boris) - update the data type to uint32_t(Paul) - better Macro naming(Lijo) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/incl

[PATCH] drm/amd/pm: avoid duplicate powergate/ungate setting

Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometime may cause unexpected issues. Change-Id: I66346c69f121df0f5ee20182451313ae4fda2d04 Signed-off-by: Evan Quan Tested-by: Borislav Petkov --- drivers/gpu/drm

[PATCH] drm/amdgpu: fix uvd crash on Polaris12 during driver unloading

There was a change(below) target for such issue: cdccf1ffe1a3 drm/amdgpu: Fix crash on device remove/driver unload But the fix for VI ASICs was missing there. This is a supplement for that. Signed-off-by: Evan Quan Change-Id: Iedc25e2f572f04772511d56781b01b481e22fd00 --- drivers/gpu/drm/amd

[PATCH] drm/amdgpu: fix the Carrizo UVD hang on system reboot

It's confirmed that on some APUs the interaction with SMU about DPM disablement will power off the UVD completely. Thus the succeeding interactions with UVD during the reboot will trigger hard hang. To workaround this issue, we will skip the dpm disablement on APUs. Signed-off-by: Evan

[PATCH] drm/amdgpu: correctly toggle gfx on/off around RLC_SPM_* register access

with RDP launched in parallel. Signed-off-by: Evan Quan Change-Id: Ifae152e8151fecd25a238ebe87dffb3b17cdb540 --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 drivers/gpu/drm/amd/amdgpu/gfx_v9_0

[PATCH] drm/amdgpu: fix the hang observed on Carrizo due to UVD suspend failure

uring interaction with SMU for suspend scenario. Signed-off-by: Evan Quan Change-Id: I7804d3835aadbc7cf4b686da4994e8461748 --- .../powerplay/hwmgr/smu7_clockpowergating.c | 20 +-- .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 16 +-- drivers/gpu/drm/a

[PATCH] drm/amdgpu: fix Polaris12 uvd crash on driver unload

This is a supplement for the change below: cdccf1ffe1a3 drm/amdgpu: Fix crash on device remove/driver unload Signed-off-by: Evan Quan Change-Id: Iedc25e2f572f04772511d56781b01b481e22fd00 --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 +--- 1 file changed, 13 insertions

[PATCH] drm/amdgpu: use generic fb helpers instead of setting up AMD own's.

With the shadow buffer support from generic framebuffer emulation, it's possible now to have runpm kicked when no update for console. Change-Id: I285472c9100ee6f649d3f3f3548f402b9cd34eaf Signed-off-by: Evan Quan Acked-by: Christian König -- v1->v2: - rename amdgpu_align_

[PATCH] drm/amd/pm: fix runpm hang when amdgpu loaded prior to sound driver

switching back to legacy message way on sound driver missing, we are able to fix the runpm hang observed for the scenario below: amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded Change-Id: I0e44fef11349b5e45e6102913eb46c8c7d279c65 Signed-off-by: Evan Quan Reported-by: Pierr

[PATCH] drm/amdgpu: use generic fb helpers instead of setting up AMD own's.

With the shadow buffer support from generic framebuffer emulation, it's possible now to have runpm kicked when no update for console. Change-Id: I285472c9100ee6f649d3f3f3548f402b9cd34eaf Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/dr

[PATCH] drm/amdgpu: reenable BACO support for 699F:C7 polaris12 SKU

90abe6 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/vi.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 42a35d9520f9..fe9a7cc8d9eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/driver

[PATCH V2 1/3] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend

9ed Signed-off-by: Evan Quan Signed-off-by: xinhui pan -- v1->v2: - move the changes to ->hw_fini() (James Zhu) --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 23 +++ 2 files changed, 47 insertions(

[PATCH V2 3/3] drm/amdgpu: drop redundant cancel_delayed_work_sync call

As those _sw_fini() APIs follow just after _suspend() APIs. And the cancel_delayed_work_sync was already called in latter. Change-Id: I7f092e39242a1ffbc3c29e1fcd7bf31b769b0ef5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

[PATCH V2 2/3] drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend

This is a supplement for commit below: "drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend". Change-Id: I7ff5692fd0c3e880ec8e55a7329469a67e5a1363 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 24 drivers/gpu/drm/amd/amdgp

[PATCH 4/4] drm/amdgpu: drop redundant cancel_delayed_work_sync call

As those _sw_fini() APIs follow just after _suspend() APIs. And the cancel_delayed_work_sync was already called in latter. Change-Id: I7f092e39242a1ffbc3c29e1fcd7bf31b769b0ef5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

[PATCH 3/4] drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend

This is a supplement for commit below: "drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend". Change-Id: I7ff5692fd0c3e880ec8e55a7329469a67e5a1363 Signed-off-by: Evan Quan -- v1->v2: - correct the sequence for clock/power gating (Lijo Lazar) --- drivers/gpu/d

[PATCH 2/4] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend

9ed Signed-off-by: Evan Quan Signed-off-by: xinhui pan -- v1->v2: - move the changes to ->hw_fini() (James Zhu) v2->v3: - correct the sequence for clock/power gating (Lijo Lazar) --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 drivers/gpu/drm/amd/amd

[PATCH 1/4] drm/amdgpu: correct clock/power gating sequence on UVD/VCE suspend/resume

The clocks should be gated before power. And reverse sequence should be used on ungating. Change-Id: Iab09f1f616560ff1083b75e95bfc6433d05d7f98 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 8 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 8

[PATCH] drm/amd/pm: a quick fix for "divided by zero" error

Considering Arcturus is a dedicated ASIC for computing, it will be more proper to drop the support for fan speed reading and setting. That's on the TODO list. Change-Id: Id83a7a88f26644ba66c4fd15034b4fc861cc6901 Signed-off-by: Evan Quan Reported-by: Rui Teng --- .../gpu/drm/amd/pm/swsmu/

[PATCH V2] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend

9ed Signed-off-by: Evan Quan Signed-off-by: xinhui pan -- v1->v2: - move the changes to ->hw_fini() (James Zhu) --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 23 +++ 2 files changed, 47 insertions(

[PATCH] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend

9ed Signed-off-by: Evan Quan Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 23 +++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/g

[PATCH] drm/amdgpu: properly powergate Polaris12 UVD/VCE on suspend

ned-off-by: Evan Quan Signed-off-by: xinhui pan --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 + 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 4eebf973a065..2f

[PATCH V2] drm/amdgpu: disable BACO support for 699F:C7 polaris12 SKU temporarily

We have a S3 issue on that SKU with BACO enabled. Will bring back this when that root caused. Change-Id: I56d4830e6275e20a415808896eecbadfe944070b Signed-off-by: Evan Quan Acked-by: Alex Deucher Reviewed-by: Guchun Chen -- v1->v2: - limit the SKU further by subsystem IDs (Alex) --- driv

[PATCH] drm/amdgpu: disable BACO support for 699F:C7 polaris12 SKU temporarily

We have a S3 issue on that SKU with BACO enabled. Will bring back this when that root caused. Change-Id: I56d4830e6275e20a415808896eecbadfe944070b Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/vi.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu

[PATCH V3 7/7] drm/amd/pm: correct the address of Arcturus fan related registers

These registers have different address from other SMU V11 ASICs. Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab Signed-off-by: Evan Quan --- v1->v2: - cover the ASIC specific details in arcturus_ppt.c (Lijo) --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 138 +-

[PATCH V3 6/7] drm/amd/pm: drop unnecessary manual mode check

As the fan control was guarded under manual mode before fan speed RPM/PWM setting. Thus the extra check is totally redundant. Change-Id: Ia9d776141ec4aa39255accbf00d7e7ed81c8424d Signed-off-by: Evan Quan -- v1->v2: - switch auto fan control off for AMD_FAN_CTRL_NONE mode (Lijo) --- driv

[PATCH V3 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition

Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb Signed-off-by: Evan Quan --- v1->

[PATCH V3 4/7] drm/amd/pm: correct the fan speed RPM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed RPM. Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044 Signed-off-by: Evan Quan -- v1->v2 - drop unneeded inter

[PATCH V3 3/7] drm/amd/pm: correct the fan speed PWM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed PWM. Change-Id: Idfe0276d7113b9c921b88fa08085a33fd971d621 Signed-off-by: Evan Quan --- .../include/asic_reg/thm/thm_11_0_2_o

[PATCH V3 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings

As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM settings need to be saved. Change-Id: I318c134d442273d518b805339cdf383e151b935d Signed-off-by: Evan Quan -- v1->v2: - coding style an

[PATCH V3 1/7] drm/amd/pm: correct the fan speed RPM setting

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to perform the fan speed RPM setting. Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8 Signed-off-by: Evan Quan -- v1->v2: - hardcode crystal_clo

[PATCH V2 7/7] drm/amd/pm: correct the address of Arcturus fan related registers

These registers have different address from other SMU V11 ASICs. Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab Signed-off-by: Evan Quan --- v1->v2: - cover the ASIC specific details in arcturus_ppt.c (Lijo) --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 138 +-

[PATCH V2 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition

Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb Signed-off-by: Evan Quan --- v1->

[PATCH V2 4/7] drm/amd/pm: correct the fan speed RPM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed RPM. Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044 Signed-off-by: Evan Quan -- v1->v2 - drop unneeded inter

[PATCH V2 6/7] drm/amd/pm: drop unnecessary manual mode check

As the fan control was guarded under manual mode before fan speed RPM/PWM setting. Thus the extra check is totally redundant. Change-Id: Ia9d776141ec4aa39255accbf00d7e7ed81c8424d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 12 +--- 1 file changed, 1

[PATCH V2 3/7] drm/amd/pm: correct the fan speed PWM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed PWM. Change-Id: Idfe0276d7113b9c921b88fa08085a33fd971d621 Signed-off-by: Evan Quan --- .../include/asic_reg/thm/thm_11_0_2_o

[PATCH V2 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings

As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM settings need to be saved. Change-Id: I318c134d442273d518b805339cdf383e151b935d Signed-off-by: Evan Quan -- v1->v2: - coding style an

[PATCH V2 1/7] drm/amd/pm: correct the fan speed RPM setting

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to perform the fan speed RPM setting. Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8 Signed-off-by: Evan Quan -- v1->v2: - hardcode crystal_clo

[PATCH V2 2/2] drm/amd/pm: restore user customized OD settings properly for Sienna Cichlid

Properly restore those committed and non-committed user customized OD settings. Change-Id: I25396df0b3ecdd7a0d9fc77ed220b0abf1fde020 Signed-off-by: Evan Quan --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 37 ++- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git

[PATCH V2 1/2] drm/amd/pm: restore user customized OD settings properly for NV1x

. - For those non-committed changes, they are restored only without feeding to SMU. Change-Id: Iea7cf7908dfcd919a4d0205e10bff91b1149a440 Signed-off-by: Evan Quan -- v1->v2 - better naming and logic revised for checking OD setting update(Lijo) --- drivers/gpu/drm/amd/pm/inc/amdgpu_sm

[PATCH 1/2] drm/amd/pm: restore user customized OD settings properly for NV1x

. - For those non-committed changes, they are restored only without feeding to SMU. Change-Id: Iea7cf7908dfcd919a4d0205e10bff91b1149a440 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 +++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 .../gpu/drm/amd/pm

[PATCH 2/2] drm/amd/pm: restore user customized OD settings properly for Sienna Cichlid

Properly restore those committed and non-committed user customized OD settings. Change-Id: I25396df0b3ecdd7a0d9fc77ed220b0abf1fde020 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 15

[PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers

These registers have different address from other SMU V11 ASICs. Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab Signed-off-by: Evan Quan --- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 104 +- 1 file changed, 78 insertions(+), 26 deletions(-) diff --git a/drivers/gpu

[PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed PWM. Change-Id: Idfe0276d7113b9c921b88fa08085a33fd971d621 Signed-off-by: Evan Quan --- .../include/asic_reg/thm/thm_11_0_2_o

[PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings

As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM settings need to be saved. Change-Id: I318c134d442273d518b805339cdf383e151b935d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu

[PATCH 6/7] drm/amd/pm: drop unnecessary manual mode check

As the fan control was guarded under manual mode before fan speed RPM/PWM setting. Thus the extra check is totally redundant. Change-Id: Ia9d776141ec4aa39255accbf00d7e7ed81c8424d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 12 +--- 1 file changed, 1

[PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed RPM. Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044 Signed-off-by: Evan Quan --- .../include/asic_reg/thm/thm_11_0_2_o

[PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition

Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb Signed-off-by: Evan Quan --- drivers/gpu

[PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting

The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to perform the fan speed RPM setting. Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc

[PATCH V2 1/3] drm/amd/pm: new SmuMetrics data structure for Sienna Cichlid

Due to the structure layout change: "uint32_t ThrottlerStatus" -> " uint8_t ThrottlingPercentage[THROTTLER_COUNT]". Change-Id: Ia62195857c5b377e8c95f76de0ec08e8674f04da Signed-off-by: Evan Quan --- .../pm/inc/smu11_driver_if_sienna_cichlid.h | 63

[PATCH V2 2/3] drm/amd/pm: update the gpu metrics data retrieving for Sienna Cichlid

Due to the structure layout change: "uint32_t ThrottlerStatus" -> " uint8_t ThrottlingPercentage[THROTTLER_COUNT]". Change-Id: I5ea15c1ea5152e480f4e379193c5848bf2b85dd4 Signed-off-by: Evan Quan -- V1->V2: - update the way for handling the new Metrics structure(L

[PATCH V2 3/3] drm/amd/pm: bump DRIVER_IF_VERSION for Sienna Cichlid

To suppress the annoying warning about version mismatch. Change-Id: I7dae1ef90ea3b09e1b378f96136b6ae61cc90696 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 2 +- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +- 2 files changed, 2

[PATCH 2/2] drm/amd/pm: bump DRIVER_IF_VERSION for Sienna Cichlid

To suppress the annoying warning about version mismatch. Change-Id: I7dae1ef90ea3b09e1b378f96136b6ae61cc90696 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h | 2 +- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +- 2 files changed, 2

[PATCH 1/2] drm/amd/pm: update the gpu metrics data retrieving for Sienna Cichlid

Due to the structure layout change: "uint32_t ThrottlerStatus" -> " uint8_t ThrottlingPercentage[THROTTLER_COUNT]". Change-Id: Id5c148b0584d972ae73fb9d7347a312944cec13d Signed-off-by: Evan Quan --- .../pm/inc/smu11_driver_if_sienna_cichlid.h | 63 -

[PATCH V3 6/7] drm/amdgpu: update GFX MGCG settings

Update GFX MGCG related settings. Change-Id: I0b7b8e7c97859f99db5f52026abbb4d226c179df Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm

[PATCH V3 7/7] drm/amdgpu: update HDP LS settings

Avoid unnecessary register programming on feature disablement. Change-Id: Ia8ad4fb28cb23f80ddcf1399eace284e4d33bd90 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 85 +++ 1 file changed, 48 insertions(+), 37 deletions(-) diff --git a/drivers/gpu

[PATCH V3 3/7] drm/amdgpu: fix NAK-G generation during PCI-e link width switch

A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Change-Id: I7a4d751e44bddc4bd1e97860cb4f53dfadc02a2c Signed-off-by: Evan Quan --- V1->V2: - move the code

[PATCH V3 4/7] drm/amdgpu: fix the hang caused by PCIe link width switch

ge-Id: I6315681f6fb194036b20991512dd88fa65bc0d56 Signed-off-by: Evan Quan --- V1->V2: - limit the change for Navi10 only V2->V3: - move the code to nbio_v2_3.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 1 + drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 + drivers/gpu/drm/amd/

[PATCH V3 5/7] drm/amdgpu: correct clock gating settings on feature unsupported

state, we will just skip the corresponding clock gating setting when the feature is not supported. Change-Id: Ic0995cf3de9f36b59316a90a28b7c95a08f4dccd Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 12 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 69

[PATCH V3 2/7] drm/amdgpu: fix Navi1x tcp power gating hang when issuing lightweight invalidaiton

Fix TCP hang when a lightweight invalidation happens on Navi1x. Change-Id: I5000fefa9ec48a5e863372d298354bed1562b332 Signed-off-by: Evan Quan --- V1->V2: - Alex: use ARRAY_SIZE instead of hard code - limit the changes for Navi1x only --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |

[PATCH V3 1/7] drm/amdgpu: correct tcp harvest setting

Add missing settings for SQC bits. And correct some confusing logics around active wgp bitmap calculation. Change-Id: If4992e175fd61d5609b00328cbe21f487517d039 Signed-off-by: Evan Quan --- V1->V2: - restore correct tcp_harvest setting for NV10 and NV12 - move asic type guard upper layer

[PATCH V2 3/7] drm/amdgpu: fix NAK-G generation during PCI-e link width switch

A lot of NAK-G being generated when link widht switching is happening. WA for this issue is to program the SPC to 4 symbols per clock during bootup when the native PCIE width is x4. Change-Id: I7a4d751e44bddc4bd1e97860cb4f53dfadc02a2c Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/nv.c

[PATCH V2 1/7] drm/amdgpu: correct tcp harvest setting

Add missing settings for SQC bits. And correct some confusing logics around active wgp bitmap calculation. Change-Id: If4992e175fd61d5609b00328cbe21f487517d039 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 28 -- 1 file changed, 17 insertions

[PATCH V2 4/7] drm/amdgpu: fix the hang caused by PCIe link width switch

ge-Id: I6315681f6fb194036b20991512dd88fa65bc0d56 Signed-off-by: Evan Quan --- V1->V2: - limit the change for Navi10 only --- drivers/gpu/drm/amd/amdgpu/nv.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 2e1d

[PATCH V2 6/7] drm/amdgpu: update GFX MGCG settings

Update GFX MGCG related settings. Change-Id: I0b7b8e7c97859f99db5f52026abbb4d226c179df Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm

[PATCH V2 7/7] drm/amdgpu: update HDP LS settings

Avoid unnecessary register programming on feature disablement. Change-Id: Ia8ad4fb28cb23f80ddcf1399eace284e4d33bd90 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 85 +++ 1 file changed, 48 insertions(+), 37 deletions(-) diff --git a/drivers/gpu

[PATCH V2 5/7] drm/amdgpu: correct clock gating settings on feature unsupported

state, we will just skip the corresponding clock gating setting when the feature is not supported. Change-Id: Ic0995cf3de9f36b59316a90a28b7c95a08f4dccd Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/athub_v2_0.c | 12 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 69

[PATCH V2 2/7] drm/amdgpu: fix Navi1x tcp power gating hang when issuing lightweight invalidaiton

Fix TCP hang when a lightweight invalidation happens on Navi1x. Change-Id: I5000fefa9ec48a5e863372d298354bed1562b332 Signed-off-by: Evan Quan --- V1->V2: - Alex: use ARRAY_SIZE instead of hard code - limit the changes for Navi1x only --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |

[PATCH V3 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x

For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 1 file

[PATCH V3 3/5] drm/amdgpu: make audio dev's D-state transition PMFW-aware

hange-Id: I136e196be7633e95883a7f6c33963f7583e9bad1 Signed-off-by: Evan Quan --- V1->V2: - Lijo: include the code in a seperate API for better readability - limit the change for Navi10 and later dGPUs - comments more about the background v2->V3: - Lijo: update the code comment further --- drivers/gpu/

[PATCH V3 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.q...@amd.com/ Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088 Signed-off-by: Evan Quan

[PATCH V3 4/5] drm/amd/pm: update the cached dpm feature status

For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be updated to pair that. Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9 Signed-off-by: Evan Quan --- V1->V2: - correct the setting

[PATCH V3 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01 Signed-off-by: Evan Quan --- V1->V2: - limit the changes for Navi1x

[PATCH V2] drm/amd/pm: correct the power limits reporting on OOB supported

with OOB imposed Change-Id: I63450ab75ec6ceb7f345bd3704295a28db23b881 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +++- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 14 +- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 26 +++-- .../gpu

[PATCH V2 4/5] drm/amd/pm: clear the cached dpm feature status

For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be cleared to pair that. Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9 Signed-off-by: Evan Quan --- V1->V2: - correct the setting

[PATCH V2 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x

For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 1 file

[PATCH V2 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01 Signed-off-by: Evan Quan --- V1->V2: - limit the changes for Navi1x

[PATCH V2 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.q...@amd.com/ Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088 Signed-off-by: Evan Quan

[PATCH V2 3/5] drm/amdgpu: correct the audio function initial Dstate

On driver loading, the ASIC is in D0 state. The bundled audio function should be in the same state also. Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1 Signed-off-by: Evan Quan --- V1->V2: - Lijo: include the code in a seperate API for better readability - limit the change for Nav

[PATCH 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x

For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Change-Id: I19363fc08568be4b7d3f2ec6eba21ccf8fff6c37 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 1 file

[PATCH 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue

As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.q...@amd.com/ Change-Id: I2a39688cdf9009885594663cd9ec99d4cfca0088 Signed-off-by: Evan Quan

[PATCH 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC

Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Change-Id: Id9ab5e308ff1873888d0acd822c71b0a303fbb01 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2

[PATCH 3/5] drm/amdgpu: correct the audio function initial Dstate

On driver loading, the ASIC is in D0 state. The bundled audio function should be in the same state also. Change-Id: I136e196be7633e95883a7f6c33963f7583e9bad1 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a

[PATCH 4/5] drm/amd/pm: clear the cached dpm feature status

For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be cleared to pair that. Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu

[PATCH] drm/amd/pm: bypass the internal power limit cache for Aldebaran

As out-of-band interface may be used to update the power limits. Thus to make sure the power limit of our driver always reflects the correct value, the internal cache must be bypassed. Change-Id: I63450ab75ec6ceb7f345bd3704295a28db23b881 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/inc

[PATCH] drm/amd/pm: correct MGpuFanBoost setting

No MGpuFanBoost setting for those ASICs which do not support it. Otherwise, it may breaks their fan control feature. Change-Id: Ifa9c87ac537a07937a0f0f6a670f21368eb29218 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c| 9 + .../gpu/drm/amd/pm/swsmu

[PATCH] drm/amdgpu: add new MC firmware for Polaris12 32bit ASIC

Polaris12 32bit ASIC needs a special MC firmware. Change-Id: I1eea9cc1d5c81a370c8fccf139f4f77bac4a1baa Signed-off-by: Evan Quan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm

[PATCH 2/2] drm/amd/pm: expose pmfw attached timestamp on Aldebaran

Available with 68.18.0 and later PMFWs. Change-Id: I0d7e61875101b476ab50f74ade6dc2aaf1e0bc24 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 13 - drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 +++ 2 files changed, 11 insertions(+), 5

[PATCH 1/2] drm/amd/pm: new gpu_metrics structure for pmfw attached timestamp

Supported by some latest ASICs. Change-Id: I0bb26df87d10f1b356b5b9bf008a1422a8fe60d9 Signed-off-by: Evan Quan --- .../gpu/drm/amd/include/kgd_pp_interface.h| 62 +++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu

[PATCH 1/2] drm/amd/pm: unify the interface for power gating

No need to have special handling for swSMU supported ASICs. Change-Id: I7292c1064c3a1c75dc9f91d7c5318eab4f407241 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 9 - drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 3 --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6

[PATCH 2/2] drm/amd/pm: unify the interface for gfx state setting

No need to have special handling for swSMU supported ASICs. Change-Id: I029414efa63c130a1a3aaba908bbf3857c5873ff Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 16 ++-- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 -- drivers/gpu/drm/amd/pm/swsmu

[PATCH 1/2] drm/amd/pm: unify the interface for loading SMU microcode

No need to have special handling for swSMU supported ASICs. Change-Id: I49395bfc31b43b09bac78527cd8f08e8600749b3 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 10 ++ drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 5 ++- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 4

[PATCH 2/2] drm/amd/pm: fix missing static declarations

Add "static" declarations for those APIs used internally. Change-Id: I38bfa8a117b3056202935163935a867f03ebaefe Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/am

[PATCH] drm/amd/pm: no need to force MCLK to highest when no display connected

Correct the check for vblank short. Change-Id: I0eb3a6bd95b7f6d97029772914154324c8ccd2c0 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b

[PATCH] drm/amd/pm: drop redundant and unneeded BACO APIs V2

Use other APIs which are with the same functionality but much more clean. V2: drop mediate unneeded interface Change-Id: I5e9e0ab5d39b49b02434f18e12392b13931396be Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/nv.c | 25 +- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 9

[PATCH 2/2] drm/amdgpu: disable runpm if other reset method not runpm capable is chosen

Otherwise, the runpm will be always enabled on a BACO capable target even the reset method was forced as like mode1. Change-Id: If6bf55c533e91470c9c83383788466161608f68d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2

[PATCH 1/2] drm/amd/pm: drop redundant and unneeded BACO APIs

Use other APIs which are with the same functionality but much more clean. Change-Id: I5e9e0ab5d39b49b02434f18e12392b13931396be Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/nv.c | 20 + drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 9 --- drivers/gpu/drm/amd/pm/swsmu

[PATCH 2/2] drm/amd/pm: label these APIs used internally as static

Also drop unnecessary header file and declarations. Change-Id: I877b48c32c599534798e14e271c3e700b0d6ebf6 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 - drivers/gpu/drm/amd/amdgpu/nv.c | 1 - drivers

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