[AMD Official Use Only - General]
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, November 30, 2022 2:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amd/display: use the proper fb offset for DM
[AMD Official Use Only - General]
Acked-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Friday, May 20, 2022 2:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liu, Aaron ; Zhang, Yifan
; Liang, Prike
Subject: [PATCH] drm/amdgpu: clean up asd
[AMD Official Use Only]
Acked-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Tuesday, March 8, 2022 2:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: align ip discovery naming with legacy ASICs
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Monday, March 7, 2022 3:54 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH 1/2] drm/amdgpu: change registers in error checking for smu
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Friday, February 25, 2022 4:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: add gfxoff support for smu 13.0.5
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Zhang, Yifan
Sent: Tuesday, February 22, 2022 4:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Zhang, Yifan
Subject: [PATCH] drm/amdgpu: add mode2 reset support for smu 13.0.5
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Liu, Aaron
Sent: Monday, February 14, 2022 12:38 PM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Yifan
Subject: RE: [PATCH] drm/amd/pm: correct the
[Public]
Reviewed-by: Huang Rui
From: Deucher, Alexander
Sent: Thursday, February 10, 2022 10:57 PM
To: Yu, Lang ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray
Subject: Re: [PATCH] drm/amdgpu: add support for GC 10.1.4
[Public]
Reviewed-by: Alex Deucher
mailto:alexander.deuc...@amd.com
To: Huang, Ray ; dri-de...@lists.freedesktop.org; Koenig,
Christian ; Daniel Vetter ;
Sumit Semwal
Cc: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org; Liu, Monk ;
linux-me...@vger.kernel.org
Subject: Re: [PATCH v2] drm/amdgpu: introduce new amdgpu_fence object to
indicate the job embedded
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 8:26 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org;
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 5:24 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org;
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 4:01 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org;
[AMD Official Use Only]
> -Original Message-
> From: Koenig, Christian
> Sent: Tuesday, December 14, 2021 4:00 PM
> To: Huang, Ray ; dri-de...@lists.freedesktop.org;
> Daniel Vetter ; Sumit Semwal
>
> Cc: amd-gfx@lists.freedesktop.org; linux-me...@vger.kernel.org;
[AMD Official Use Only]
> -Original Message-
> From: Liu, Aaron
> Sent: Tuesday, October 19, 2021 11:23 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron
> Subject: [PATCH] drm/amdgpu: support B0 external revision id for
[AMD Official Use Only]
+ Charlene.
Reviewed-by: Huang Rui
-Original Message-
From: Yu, Lang
Sent: Tuesday, October 12, 2021 2:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Yu, Lang
Subject: [PATCH] drm/amdgpu: enable display for cyan skillfish
[AMD Official Use Only]
Acked-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Lang Yu
Sent: Monday, October 11, 2021 4:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Yu, Lang
Subject: [PATCH] drm/amdgpu: query default sclk from smu
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Lang Yu
Sent: Friday, August 27, 2021 1:41 PM
To: amd-gfx@lists.freedesktop.org; Clements, John
Cc: Huang, Ray ; Yu, Lang
Subject: [PATCH] drm/amdgpu: show both cmd id and name when psp cmd failed
To cover
[AMD Official Use Only]
Nice catch!
Series are Reviewed-by: Huang Rui
Thanks,
Ray
-Original Message-
From: Liu, Aaron
Sent: Friday, August 27, 2021 9:29 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Kazlauskas, Nicholas ; Liu,
Aaron
Subject: [PATCH 2
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Tuesday, August 3, 2021 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Aaron ; Deucher, Alexander
; Huang, Ray ; Hou, Xiaomeng
(Matthew)
Subject: [PATCH] drm/amd/pm: update
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Wednesday, June 30, 2021 1:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Gong, Curry ; Kuehling, Felix
; Liu, Aaron ; Huang, Ray
Subject: [PATCH] drm/amdgpu
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Monday, June 28, 2021 10:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Tuikov, Luben ; Koenig, Christian
; Liu, Aaron
Subject: [PATCH] drm/amdgpu: enable sdma0
Reviewed-by: Huang Rui
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Monday, June 7, 2021 8:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Wang, Kevin(Yang) ;
Hou, Xiaomeng (Matthew)
Subject: [PATCH] drm/amd/pm: fix warning reported by kernel test robot
Kernel
[AMD Official Use Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liu, Aaron
Sent: Tuesday, May 18, 2021 10:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Wang, Kevin(Yang) ; Liu, Aaron
Subject: [PATCH] drm/amdgpu: modify system reference clock
tion to fix this issue at current. Nice
work, Changfeng!
Best Regards,
Ray
From: Deucher, Alexander
Sent: Wednesday, May 19, 2021 11:04 AM
To: Chen, Guchun ; Zhu, Changfeng ;
Alex Deucher ; Das, Nirmoy
Cc: Huang, Ray ; amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/ra
[AMD Public Use]
Reviewed-by: Huang Rui
-Original Message-
From: Su, Jinzhou (Joe)
Sent: Tuesday, March 9, 2021 10:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Su, Jinzhou (Joe)
Subject: [PATCH] drm/amdgpu: update secure display TA header
update secure display TA header
ign, patch looks good for me.
Acked-by: Huang Rui mailto:ray.hu...@amd.com>>
Thanks,
Ray
From: Wang, Kevin(Yang)
Sent: Wednesday, January 20, 2021 12:10 PM
To: Du, Xiaojian ; amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Quan, Evan ; Lazar, Lijo
Subject: Re: [PATCH] drm/amd/pm: mak
[AMD Public Use]
Reviewed-by: Huang Rui
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Thursday, December 10, 2020 9:00 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Gao, Likun ; Hou,
Xiaomeng (Matthew)
Subject: [PATCH] drm/amdgpu/sdma5.2: soft reset sdma blocks
Reviewed-by: Huang Rui
-Original Message-
From: Su, Jinzhou (Joe)
Sent: Friday, October 30, 2020 2:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Su, Jinzhou (Joe)
Subject: [PATCH] amdgpu: Add mmhub MGCG and MGLS for vangogh
Add AMD_CG_SUPPORT_MC_MGCG
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Monday, April 20, 2020 10:11 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liang, Prike
Subject: [PATCH] drm/amd/powerplay: update
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Wednesday, April 15, 2020 11:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Huang, Ray
; Liang, Prike
Subject: [PATCH] drm/amd/powerplay: fix
, 2020 10:12 AM
To: Zhu, James ; Alex Deucher ;
Zhang, Hawking ; Huang, Ray
Cc: amd-gfx list
Subject: RE: [PATCH] drm/amdgpu/vcn: fix gfxoff issue
[AMD Official Use Only - Internal Distribution Only]
+Ray
BR,
Changfeng.
-Original Message-
From: Zhu, James
Sent: Tuesday, April 14, 2020
[AMD Public Use]
Hi Alex,
MR = merge request? Should I create account to send merge request in the
freedesktop gitlab?
Thanks,
Ray
From: Deucher, Alexander
Sent: Tuesday, February 11, 2020 10:30 PM
To: Christian König ; Huang, Ray
; amd-gfx@lists.freedesktop.org
Cc: Pelloux-prayer, Pierre
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Huang Rui
-Original Message-
From: Wang, Kevin(Yang)
Sent: Monday, December 23, 2019 6:28 PM
To: amd-gfx-boun...@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ;
Liang, Prike ; Deucher, Alexander
; Wang, Kevin
om "error" to
> "warning" , it will be much better.
>
>
> -Original Message-
> From: Liang, Prike
> Sent: Thursday, December 19, 2019 2:46 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan ; Huang, Ray ; Dai,
> Yuxian (David) ; Lian
[AMD Official Use Only - Internal Distribution Only]
On Wed, Dec 18, 2019 at 07:40:26AM +0800, Kuehling, Felix wrote:
> See comment inline. Other than that, the series looks good to me.
>
> On 2019-12-16 2:02, Huang Rui wrote:
> > Thunk driver would like to know the num_cp_queues data, however
On Fri, Dec 13, 2019 at 11:24:00AM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> When smu version is larger than 0x41e2b, it will load
> raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it
> needs to avoid adev->pm.pp_feature &= ~PP_GFXOFF_MASK when it loads
>
[AMD Official Use Only - Internal Distribution Only]
On Thu, Dec 12, 2019 at 06:01:55PM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> When smu version is larger than 0x41e2b, it will load
> raven_kicker_rlc.bin.To enable gfxoff for raven_kicker_rlc.bin,it
> needs to avoid
On Tue, Dec 10, 2019 at 10:55:13AM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> It may cause timeout waiting for sem acquire in VM flush when using
> invalidate semaphore for picasso. So it needs to avoid using invalidate
> semaphore for piasso.
>
> Change-Id:
Sorry, please ignore this patch. Just misunderstood before.
Thanks,
Ray
-Original Message-
From: Huang, Ray
Sent: Wednesday, December 4, 2019 3:22 PM
To: amd-gfx@lists.freedesktop.org; Kuehling, Felix ;
Zhao, Yong
Cc: Deucher, Alexander ; Huang, Ray
Subject: [PATCH] drm/amdkfd: fix
[AMD Official Use Only - Internal Distribution Only]
On Thu, Nov 21, 2019 at 11:47:15PM +0800, Zhu, Changfeng wrote:
> From: changzhu
>
> It may lose gpuvm invalidate acknowldege state across power-gating off
> cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
>
Series are Reviewed-by: Huang Rui
On Mon, Nov 18, 2019 at 01:18:32PM +0800, Liu, Aaron wrote:
> This patch expands sdma copy_buffer interface with tmz parameter.
>
> Signed-off-by: Aaron Liu
> Reviewed-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 5 +++--
>
On Fri, Nov 15, 2019 at 11:34:55AM +0800, Liu, Aaron wrote:
> This patch add test to submit a sdma command with secure context.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/security_tests.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
On Fri, Nov 15, 2019 at 11:34:53AM +0800, Liu, Aaron wrote:
> This patch is to test the command submission with secure context.
>
> Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
> ---
> tests/amdgpu/security_tests.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git
On Fri, Nov 15, 2019 at 11:34:52AM +0800, Liu, Aaron wrote:
> Secure buffer is only able to be read with trusted ip block.
> So we need use GFX ip to read it back instead of CPU.
> Steps:
> 1. use write_data packet to write 0xdeadbeaf to secure buffer,
> 2. use atmoic_mem packet and
On Fri, Nov 15, 2019 at 11:34:54AM +0800, Liu, Aaron wrote:
> DMA's atomic behavir is unlike GFX,If the comparing data is not
> equal to destination data,
> For GFX, loop again till gfx timeout(system hang).
> For DMA, loop again till timer expired and then send interrupt.
> So testcase can't use
On Fri, Nov 15, 2019 at 11:34:51AM +0800, Liu, Aaron wrote:
> This patch expands secure param for amdgpu_test_exec_cs_helper_raw.
> The flag is transfered to kernel with cs.
>
> Signed-off-by: Aaron Liu
Acked-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 8 +---
> 1 file changed, 5
On Fri, Nov 15, 2019 at 11:34:51AM +0800, Liu, Aaron wrote:
> This patch expands secure param for amdgpu_test_exec_cs_helper_raw.
> The flag is transfered to kernel with cs.
>
> Signed-off-by: Aaron Liu
Acked-by: Huang Rui
> ---
> tests/amdgpu/basic_tests.c | 8 +---
> 1 file changed, 5
On Fri, Nov 15, 2019 at 11:34:52AM +0800, Liu, Aaron wrote:
> Secure buffer is only able to be read with trusted ip block.
> So we need use GFX ip to read it back instead of CPU.
> Steps:
> 1. use write_data packet to write 0xdeadbeaf to secure buffer,
> 2. use atmoic_mem packet and
On Fri, Nov 15, 2019 at 11:34:50AM +0800, Liu, Aaron wrote:
> In kernel, cs->in.flags is used for TMZ. Hence libdrm should transfer
> the flag to kernel.
>
> Signed-off-by: Aaron Liu
> ---
> amdgpu/amdgpu.h| 4 +++-
> amdgpu/amdgpu_cs.c | 4
> 2 files changed, 7 insertions(+), 1
> -Original Message-
> From: Zhu, Changfeng
> Sent: Friday, November 08, 2019 9:55 AM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Huang, Ray
> Cc: Zhu, Changfeng
> Subject: [PATCH] drm/amdgpu: allow direct upload save restore list for
> ra
mu, true);
> +
> mutex_unlock(>mutex);
>
> pr_info("SMU is resumed successfully!\n");
>
> -Original Message-
> From: Huang, Ray
> Sent: Friday, October 25, 2019 9:26 PM
> To: Gong, Curry ; amd-gfx@lists.freedesktop.org
> Cc:
Why do you disable CGPG for all APU?
Thanks,
Ray
-Original Message-
From: amd-gfx On Behalf Of chen gong
Sent: Friday, October 25, 2019 7:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Gong, Curry
Subject: [PATCH] drm/amd/powerplay: Disable gfx CGPG when suspend smu
if no disable gfx
On Thu, Oct 24, 2019 at 09:16:55PM +, Tuikov, Luben wrote:
> The GRBM interface is now capable of bursting 1-cycle op per register,
> a WRITE followed by another WRITE, or a WRITE followed by a READ--much
> faster than previous muti-cycle per completed-transaction interface.
> This causes a
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Thursday, October 24, 2019 7:17 PM
To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; Zhou,
David(ChunMing)
Subject: [PATCH] drm/ttm: use the parent resv for ghost objects v3
Series are Reviewed-by: Huang Rui
-Original Message-
From: Liang, Prike
Sent: Tuesday, October 15, 2019 5:50 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ;
Huang, Ray ; Liang, Prike
Subject: [PATCH 1/2] drm/amdgpu: add GFX_PIPELINE capacity check for updating
Series are Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, October 3, 2019 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu: improve MSI-X handling
Check the number of supported vectors
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Friday, September 27, 2019 8:34 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: [PATCH 2/2] drm/radeon: finally fix the racy VMA setup
Finally clean up the VMA
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, October 1, 2019 5:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: don't increment vram lost if we are in hibernation
We reset the GPU as part of
Ahh.
Reviewed-by: Huang Rui
-Original Message-
From: amd-gfx On Behalf Of Christian
König
Sent: Wednesday, October 2, 2019 4:38 AM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/ttm: also export ttm_bo_vm_fault
Just a gentle ping on
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
v4: filling cs parser with cs->in.flags
v5: move the job secure flag setting out of amdgpu_cs_submit()
> -Original Message-
> From: Liu, Aaron
> Sent: Friday, September 27, 2019 11:23 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Liu, Aaron
> Subject: [PATCH] Revert "drm/amdgpu: disable stutter mode for renoir"
>
> This reverts commit c512e6
> -Original Message-
> From: amd-gfx On Behalf Of Liu,
> Shaoyun
> Sent: Wednesday, September 25, 2019 6:14 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Shaoyun
> Subject: [PATCH] drm/amdgpu: Add NAVI12 support from kfd side
>
> Add device info for both navi12 PF and VF
>
>
> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, September 25, 2019 10:47 PM
> To: Huang, Ray ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Deucher, Alexander
>
> Cc: Tuikov, Luben ; Liu, Aaron
>
> Subject: Re: [PATC
> -Original Message-
> From: amd-gfx On Behalf Of
> Christian K?nig
> Sent: Thursday, September 19, 2019 1:43 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: fix error handling in amdgpu_bo_list_create
>
> We need to drop normal and userptr BOs separately.
>
>
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
v4: filling cs parser with cs->in.flags
Signed-off-by: Huang Rui
Co-developed-by: Luben Tuikov
Signed-off-by:
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
From: Alex Deucher
If a buffer object is secure, i.e. created with
AMDGPU_GEM_CREATE_ENCRYPTED, then the TMZ bit of
the PTEs that belong the buffer object should be
set.
v1: design and draft the skeletion of TMZ bits setting on PTEs (Alex)
v2: return failure once create secure BO on non-TMZ
Mark a job as secure, if and only if the command
submission flag has the secure flag set.
v2: fix the null job pointer while in vmid 0
submission.
v3: Context --> Command submission.
Signed-off-by: Huang Rui
Co-developed-by: Luben Tuikov
Signed-off-by: Luben Tuikov
Reviewed-by: Alex Deucher
This patch adds tmz bit in frame control pm4 packet, and it will used in future.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/nvd.h| 1 +
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 2 insertions(+)
diff
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41
From: Alex Deucher
Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Luben Tuikov
Add a flag to the command submission IOCTL
structure which when present indicates that this
command submission should be treated as
secure. The kernel driver uses this flag to
determine whether the engine should be
transitioned to secure or unsecure, or the work
can be
Hi all,
These series of patches introduce a feature to support secure buffer object.
The Trusted Memory Zone (TMZ) is a method to protect the contents being written
to and read from memory. We use TMZ hardware memory protection scheme to
implement the secure buffer object support.
TMZ is the
> -Original Message-
> From: Koenig, Christian
> Sent: Thursday, September 12, 2019 7:49 PM
> To: Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> Deucher, Alexander ; Tuikov, Luben
> ; Liu, Aaron
> Subject: Re: [PATCH 14/14]
> -Original Message-
> From: Liu, Aaron
> Sent: Monday, September 16, 2019 9:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Huang, Ray
> ; Liu, Aaron
> Subject: [PATCH] drm/amdgpu: remove program of lbpw for renoir
>
> These is no
On Wed, Sep 11, 2019 at 08:13:19PM +0800, Koenig, Christian wrote:
> Am 11.09.19 um 13:50 schrieb Huang, Ray:
> > From: Alex Deucher
> >
> > If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ
> > bits of
> > PTEs that belongs that b
From: Alex Deucher
Add a flag to the GEM_CREATE ioctl to create encrypted buffers.
Buffers with this flag set will be created with the TMZ bit set
in the PTEs or engines accessing them. This is required in order
to properly access the data from the engines.
Signed-off-by: Alex Deucher
From: Alex Deucher
If one bo is secure (created with AMDGPU_GEM_CREATE_ENCRYPTED), the TMZ bits of
PTEs that belongs that bo should be set. Then psp is able to protect the pages
of this bo to avoid the access from an "untrust" domain such as CPU.
v1: design and draft the skeletion of tmz bits
Hi all,
These series of patches introduce a feature to support secure buffer object.
The Trusted Memory Zone (TMZ) is a method to protect the contents being written
to and read from memory. We use TMZ hardware memory protection scheme to
implement the secure buffer object support.
TMZ is the
This patch adds tmz bit in frame control pm4 packet, and it will used in future.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nvd.h| 1 +
drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 +
2 files changed, 2 insertions(+)
diff --git
amdgpu_ttm_tt_pte_flags will be used for updating tmz bits while the bo is
secure, so we need pass the ttm_mem_reg under a buffer object.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 18 ++
1 file changed, 10 insertions(+), 8
The is_secure flag will indicate the current conext is protected or not.
v2: while user mode asks to create a context, but if tmz is disabled, it should
return failure.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 19 +++
While user mode submit a command with secure context, we should set the command
buffer with trusted mode.
v2: fix the null job pointer while in vmid 0 submission.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 +
This patch expands the context control function to support trusted flag while we
want to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
Add a function to check tmz capability with kernel parameter and ASIC type.
v2: use a per device tmz variable instead of global amdgpu_tmz.
v3: refine the comments for the function. (Luben)
v4: add amdgpu_tmz.c/h for future use.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
This patch expands the emit_tmz function to support trusted flag while we want
to set command buffer in trusted mode.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 4 ++--
From: Alex Deucher
Add a flag for when allocating a context to flag it as
secure. The kernel driver will use this flag to determine
whether a rendering context is secure or not so that the
engine can be transitioned between secure or unsecure
or the work can be submitted to a secure queue
This patch is to add a helper to get corresponding buffer object with a pointer
to a struct ttm_mem_reg.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
include/drm/ttm/ttm_bo_driver.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/drm/ttm/ttm_bo_driver.h
This patch adds tmz parameter to enable/disable the feature in the amdgpu kernel
module. Nomally, by default, it should be auto (rely on the hardware
capability).
But right now, it need to set "off" to avoid breaking other developers'
work because it's not totally completed.
Will set "auto" till
This patch to add amdgpu_tmz structure which stores all tmz related fields.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_tmz.h | 36 +
2 files changed, 41
From: Alex Deucher
Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.
Signed-off-by: Alex Deucher
Reviewed-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
This patch fixes null pointer issue below, I missed to init the asic renior name
while I rebase the patches.
[ 106.004250] BUG: kernel NULL pointer dereference, address:
[ 106.004254] #PF: supervisor read access in kernel mode
[ 106.004256] #PF: error_code(0x) -
> -Original Message-
> From: S, Shirish
> Sent: Tuesday, September 10, 2019 3:54 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org; S, Shirish
> Subject: [PATCH] drm/amdgpu: fix build error without CONFIG_HSA_AMD
&
Renoir's cache info should be the same with raven and carrizo's.
v2: fix missed "break"
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
This patch inits renoir kfd device info, so we treat renoir as "dgpu"
(bypass iommu v2). Will enable needs_iommu_device till renoir iommu is ready.
v2: rebase and align the drm-next
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 18 ++
1 file changed, 18
On Thu, Sep 05, 2019 at 07:31:11AM +0800, Kuehling, Felix wrote:
> There is no point retrying page faults in VMID0. Those faults are
> always fatal.
>
> Signed-off-by: Felix Kuehling
Thanks! I have verified it in my platform.
Reviewed-and-Tested-by: Huang Rui
> ---
>
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