On 2019-02-20 12:24 a.m., Mathias Fröhlich wrote:
> Hi,
>
> ping?
> ... to the dc folks?
>
> best
> Mathias
Hi Mathias,
Sorry for the wait, change looks good to me.
Reviewed-by: Leo Li
...and merged.
Thanks for cleaning this up.
Leo
>
> On Wednesday, 13 Febr
. But yeah, same problem seems to
> exits for VCE 2 as well.
>
> Leo any comment on this?
UVD and VCE start function were at hw_init originally from the bring up
on all the HW. And later the DPM developer moved them to
set_powergating_state() for some reason.
@Shirish, are you sure the vce_
> but we wouldn't should be doing anything in that case anyway.
>
> Fixes: c00e0cc0fdc0 ("drm/amd/display: Call into DC once per multiplane flip")
> Fixes: ea39594e0855 ("drm/amd/display: Perform plane updates only when
> needed")
>
> Cc: Michel Dänzer
&g
On 2019-01-15 5:42 a.m., Paul Menzel wrote:
> Dear Hersen, dear Leo,
>
>
> Some nitpicks. Could you not put the problem statement in the commit
> message summary, but the solution? For example:
>
>> Fix eDP fast bootup for pre-raven asics
>
> On 01/14/19 2
TC mode change or when VRR is toggled.
>
> The condition has been updated accordingly.
>
> Fixes: 3cc22f281318 ("drm/amdgpu: Set FreeSync state using drm VRR
> properties")
>
> Cc: Harry Wentland
> Cc: Leo Li
> Signed-off-by: Nicholas Kazlauskas
Revie
Reviewed-by: Leo Liu
On 12/21/18 11:36 AM, Alex Deucher wrote:
> ping?
>
> On Thu, Dec 20, 2018 at 10:10 AM Alex Deucher wrote:
>> Add a new pci id.
>>
>> Signed-off-by: Alex Deucher
>> Cc: sta...@vger.kernel.org
>> ---
>> drivers/gpu/drm/amd/amd
On 2018-12-18 3:33 p.m., Grodzovsky, Andrey wrote:
>
>
> On 12/18/2018 12:09 PM, Kazlauskas, Nicholas wrote:
>> On 12/18/18 10:26 AM, sunpeng...@amd.com wrote:
>>> From: Leo Li
>>>
>>> drm_atomic_helper_check_planes() calls the crtc atomic check
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Zhu,
James
Sent: Monday, December 17, 2018 9:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: jzh...@gmail.com
Subject: [PATCH v2] drm/amdgpu:Improves robustness
The series are:
Acked-by: Leo Liu
On 12/13/18 1:08 PM, Zhu, James wrote:
> Remove bit 31 for scratch2 to indicate the Hardware bug work around is active.
>
> Signed-off-by: James Zhu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
> 1 file changed, 2 insertio
er writes needs to be guarded for asynchronous updates to work.
> The dc_lock mutex was added for this.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106175
>
> Cc: Leo Li
> Cc: Harry Wentland
> Signed-off-by: Nicholas Kazlauskas
I just skimmed through the calls
Just make them properly i.e. put 0 to the Nop reg
Signed-off-by: Leo Liu
---
tests/amdgpu/vcn_tests.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index d9f05af8..859ec496 100644
--- a/tests/amdgpu
Reviewed-by: Leo Li
On 2018-12-07 1:10 p.m., Deucher, Alexander wrote:
> Acked-by: Alex Deucher
>
>
> *From:* amd-gfx on behalf of
> Nicholas Kazlauskas
> *Sent:* Friday, December 7, 2018 12:15:01
Reviewed-by: Leo Li
On 2018-12-07 1:14 p.m., Alex Deucher wrote:
> Acked-by: Alex Deucher
> On Fri, Dec 7, 2018 at 10:07 AM Nicholas Kazlauskas
> wrote:
>>
>> [Why]
>> These properties aren't being carried over when the atomic state.
>> This tricks atomic chec
Please re-state the patch subject instead of "Fixed S3 hung issue"
With that fixed, the patch is
Reviewed-by: Leo Liu
On 12/4/18 10:31 AM, Zhu, James wrote:
> Replace vcn_v1_0_stop with vcn_v1_0_set_powergating_state during suspend,
> to keep adev->vcn.cur_state update.
On 2018-11-30 10:13 a.m., Deucher, Alexander wrote:
> Acked-by: Alex Deucher
Reviewed-by: Leo Li
>
>
> *From:* amd-gfx on behalf of
> Nicholas Kazlauskas
> *Sent:* Friday, November 30, 2018 10:09
rop the dc->current_state copy from within
> atomic check. It's replaced by a copy from the current atomic state
> which is propagated correctly for the sequence described above.
>
> Since access to the dm_state private object is now locked this should
> also fix issues that
_mode == NULL) {
> /*
>* This may not be an error, the use case is when we have no
> @@ -2824,8 +2839,19 @@ create_stream_for_sink(struct amdgpu_dm_connector
> *aconnector,
> if (!dm_state)
> drm_mode_set_crtcinfo(, 0);
>
> - fill_
by CoverityScan, CID#1475565 ("Dereference before null check")
>
> Fixes: e1e8a020c6b8 ("drm/amd/display: Add support for Freesync 2 HDR and
> Content to Display Mapping")
> Signed-off-by: Colin Ian King
Reviewed-by: Leo Li
Thanks!
> ---
&
emented its own __drm_atomic_helper_crtc_reset(),
> convert it to the common one.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: David Airlie
> Cc: Liviu D
9("drm/amd/display: add retimer log for HWQ tuning use.")
> Cc: Charlene Liu
> Cc: Dmytro Laktyushkin
> Cc: Leo Li
> Signed-off-by: Shaokun Zhang
Reviewed-by: Leo Li
Thanks!
Leo
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
> 1 file changed
On 2018-10-16 08:33 AM, Daniel Vetter wrote:
> On Mon, Oct 15, 2018 at 09:46:40AM -0400, sunpeng...@amd.com wrote:
>> From: Leo Li
>>
>> This fixes a general protection fault, caused by accessing the contents
>> of a flip_done completion object that has already b
Looks good to me. The whole series are:
Acked-by: Leo Liu
On 10/10/2018 02:42 PM, James Zhu wrote:
Update Static Power Gate mode UVD status clear
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
Reviewed-by: Leo Liu
On 10/02/2018 09:20 AM, James Zhu wrote:
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git
Same comment as for v1
Regards,
Leo
On 10/02/2018 04:35 PM, James Zhu wrote:
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 19
low. With that fixed, the patch is
Acked-by: Leo Liu
WREG32_SOC15(UVD, 0,
mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
WREG32_SOC15(
Acked-by: Leo Liu
On 10/02/2018 01:18 PM, James Zhu wrote:
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8
2
Acked-by: Leo Liu
On 10/02/2018 01:35 PM, James Zhu wrote:
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6
e
+ RV family for display engine
+
Probably better to follow Michel's suggestion and not make that an use
configurable option.
Instead just select it based on the dependencies.
The 2nd patch should have taken care of that :)
Leo
Christian.
___
am
On 2018-07-31 02:24 PM, Dan Carpenter wrote:
[ Potential security issue, if I'm reading the code correctly. I don't
really know the code and I haven't looked at the larger context. -dan ]
Hello Leo (Sunpeng) Li,
The patch edf6ffe4f47e: "drm/amd/display: Read AUX channel even if
, 0, mmUVD_SYS_INT_EN), reg_temp);
Here you could use below instead.
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
Ether way, the whole series are
Acked-by: Leo Liu
+
/* clear the bit 4 of VCN_STA
On 2018-07-19 11:17 AM, Harry Wentland wrote:
On 2018-07-19 10:36 AM, Christian König wrote:
Note that Harry and Leo Li are maintainers for that stuff.
Signed-off-by: Christian König
Reviewed-by: Harry Wentland
Reviewed-by: Leo Li
Harry
---
MAINTAINERS | 8
1 file
support.
Reviewed-by: Leo Liu
v2: fix one more missed case in amdgpu_uvd_suspend
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 121
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 10 +--
2 files changed, 64 insertions(+), 67
cannot call amdgpu_ib_schedule directly, so need the entity
to put this job to the scheduler.
The patch is:
Reviewed-by: Leo Liu
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 -
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12
drivers/gpu/drm
Reviewed-by: Leo Liu
On 07/11/2018 02:55 PM, boyuan.zh...@amd.com wrote:
From: Boyuan Zhang
The emit_reg_write_reg_wait function was not assigned for vcn jpeg.
This patch add it back.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 +
1 file changed, 1
Fixes: 22cc6c5e19 (drm/amdgpu: Add runtime VCN PG support)
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 4a3457236e85
To make register read/write reliable. Along with the previous patch,
VCN will work with dpm disabled case.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers
VCN won't get power off when only jpeg active
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index a66cd521a875..4a3457236e85 100644
Have this patch overlooked. This is a good catch.
Reviewed-by: Leo Liu
On 2018-06-29 10:57 AM, Alex Deucher wrote:
Ping?
On Thu, Jun 28, 2018 at 2:37 PM, Alex Deucher wrote:
Was missed when updating the uvd 6 module.
Fixes: 1aac3c9180 (drm/amdgpu: fix insert nop for UVD6 ring)
Signed-off
Looks good to me. Both patches are
Reviewed-by: Leo Liu
On 06/29/2018 10:58 AM, Alex Deucher wrote:
Ping on this series?
On Mon, Jun 25, 2018 at 1:42 PM, Alex Deucher wrote:
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer
On 06/25/2018 04:42 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 4:37 PM, James Zhu wrote:
On 2018-06-25 04:32 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 4:26 PM, James Zhu wrote:
On 2018-06-25 04:02 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 3:17 PM, Leo Liu wrote
] amdgpu_device_init+0x112c/0x1dc0 [amdgpu]
The problem is the ring->me might be more than 1 for ring.
v2: simplified with ring type
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amd
e = mec + 1;
./gfx_v7_0.c:4471: ring->me = mec + 1;
Timothy,
It is not easy to find root cause based on current information.
What asic are you using on this test. IS this UBSAN test open source?
Is it easy for you guide me to reproduce it on my bench?
https://people.freedesktop.org/~narmstrong/me
] amdgpu_device_init+0x112c/0x1dc0 [amdgpu]
ring->me might be set as 2 with amdgpu_gfx_kiq_init_ring.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
]
[ 3.869808] [drm] Found UVD firmware Version: 1.130 Family ID: 16
[ 3.871505] [drm] Found VCE firmware Version: 53.26 Binary ID: 3
The fix will follow.
Regards,
Leo
On 06/25/2018 03:02 PM, Alex Deucher wrote:
On Mon, Jun 25, 2018 at 2:59 PM, James Zhu wrote
On 2018-06-15 02:57 AM, Michel Dänzer wrote:
On 2018-06-14 09:49 PM, Leo Li wrote:
On 2018-06-14 12:57 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new
patchset. Pe
On 2018-06-14 12:57 PM, Michel Dänzer wrote:
Hi Leo,
sorry for the delay.
Appreciate the review, it's not a small change by any means :)
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a ne
_1_66_16))
- DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too
old.\n",
- version_major, version_minor);
+ adev->uvd.fw_version = ((enc_major << 24) | (enc_minor << 16) |
+ (dec
On 06/12/2018 11:46 AM, James Zhu wrote:
Vega20 UVD Firmware has a new version naming convention:
[31, 30] for encode interface major
[29, 24] for encode interface minor
[15, 8] for decode interface minor
[7, 0] for hardware family id
Signed-off-by: James Zhu
Reviewed-by: Leo
.
Regards,
Leo
[15, 8] for firmware revision
[7, 0] for hardware family id
Inside kernel log UVD firmware Version: 1.1.2 (denote major.minor.revision)
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 21 -
1 file changed, 16 insertions(+), 5
On 2018-06-06 01:03 PM, Michel Dänzer wrote:
On 2018-06-06 06:01 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new patchset. Per
Michel's suggestions, there have be
major.minor.revision)
Now the major and minor become 1.1. if you keep looking the code after
the changed part, the 1.1 will cause problem for number of handles,
since that decides how big of bo size for FW runtime.
Regards,
Leo
Apart from that looks good to me, but Leo should have the las
On 2018-06-06 01:03 PM, Michel Dänzer wrote:
On 2018-06-06 06:01 PM, Michel Dänzer wrote:
On 2018-06-01 06:03 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li"
This ended up being different enough from v2 to warrant a new patchset. Per
Michel's suggestions, there have be
On 05/31/2018 01:04 PM, Michel Dänzer wrote:
On 2018-05-31 06:49 PM, Leo Liu wrote:
On 05/31/2018 12:47 PM, Michel Dänzer wrote:
On 2018-05-31 06:39 PM, Leo Liu wrote:
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
diff --git a/drivers/gpu/drm/amd
On 05/31/2018 12:47 PM, Michel Dänzer wrote:
On 2018-05-31 06:39 PM, Leo Liu wrote:
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 12f0d18c6ee8
On 05/31/2018 12:39 PM, Leo Liu wrote:
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
This isn't
On 05/31/2018 12:30 PM, Michel Dänzer wrote:
On 2018-05-30 08:42 PM, Leo Liu wrote:
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
This isn't enough to actually make this part
On 05/31/2018 11:43 AM, Alex Deucher wrote:
On Wed, May 30, 2018 at 2:42 PM, Leo Liu wrote:
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
A few comments below about readability
There are four ioctls in this files, and DOC gives details of
data structures for each of ioctls, and their functionalities.
Signed-off-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 142 +
1 file changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/amd
On 2018-05-28 11:20 AM, Michel Dänzer wrote:
On 2018-05-28 05:06 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
For cases where the CRTC is inactive (DPMS off), where a modeset is not
required, yet the CRTC is still in the atomic state, we sh
On 2018-05-28 05:15 AM, Michel Dänzer wrote:
Hi Leo,
commit e277adc5a06c "drm/amd/display: Hookup color management functions"
broke suspend to RAM on my development system with a Tonga and a Turks
(using the radeon driver). It sometimes, but not always happens when
trying to su
It should be stateless, and no need for scheduler to take care
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 51 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 --
2 files changed, 10 insertions(+), 43 deletions(-)
message.
I will come up a patch to remove those entities for dec and enc.
Regards,
Leo
Christian.
unsigned num_enc_rings;
};
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On 2018-05-18 04:10 AM, Michel Dänzer wrote:
On 2018-05-17 11:43 PM, Leo Li wrote:
On 2018-05-16 01:06 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
3. The three color management properties (Degamma LUT, Color
Transform Matrix
(CTM), and Gamma LUT
On 2018-05-18 04:01 AM, Michel Dänzer wrote:
On 2018-05-17 11:44 PM, Leo Li wrote:
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This will persist color management properties
On 2018-05-18 06:33 AM, Michel Dänzer wrote:
From: Michel Dänzer <michel.daen...@amd.com>
Leo pointed out that drmmode_do_crtc_dpms wasn't getting called when
turning off an output with
xrandr --output --off
This meant that the vblank sequence number and timestamp wouldn't be
On 2018-05-16 01:10 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This will persist color management properties on a CRTC across DPMS
state changes.
Signed-off-by: Leo (Sunpeng) Li <sunpeng...
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The dpms_mode flag on the driver-private CRTC was not being set when
it's DPMS state is set to off. This causes some problems when
se int32_t instead?).
For historical reasons, Xlib uses long for 32-bit values, so you have to
pad each 32-bit value to a long. XCB shouldn't be affected by this.
Noted.
Leo
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/ma
On 2018-05-16 01:08 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Push staged values on the driver-private CRTC, to kernel DRM when it's
initialized. This is to flush out any previous sta
On 2018-05-16 01:09 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The properties on an RandR output needs to stay consistent throughout
it's lifecycle. However, we cannot list color propert
On 2018-05-16 01:07 PM, Michel Dänzer wrote:
On 2018-05-03 08:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Non-legacy color management consists of 3 properties on the CRTC:
Degamma LUT, Color Transformation Matrix (CTM), and Gamma LUT.
Add
On 05/17/2018 02:18 PM, Alex Deucher wrote:
On Thu, May 17, 2018 at 2:12 PM, Leo Liu <leo@amd.com> wrote:
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
We discussed this when we first started working on amdgpu. Does it
have to be 0?
Yes.
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index f9
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 05
Ping :)
Leo
On 2018-05-03 02:31 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This patchset ended up looking quite different from the first. To address some
fundamental issues, the design had to be reworked.
Things gathered from previous review:
.
Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
Thanks Harry,
Reviewed-by: Leo Li <sunpeng...@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_d
On 2018-04-12 06:30 AM, Michel Dänzer wrote:
On 2018-04-11 11:26 PM, Leo Li wrote:
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
Hmm. So either legacy or non-legacy clients won't work at all, or
they'll step on each other's toes, clobbering the HW gamma LUT from
each other.
I'm afraid
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
In cases where CRTC properties are updated witho
On 2018-04-11 04:39 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This change adds a few functions in preparation
On 2018-04-11 04:48 AM, Michel Dänzer wrote:
On 2018-04-10 08:02 PM, Leo Li wrote:
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The functions insert into the output r
On 2018-04-10 04:44 PM, Harry Wentland wrote:
Ping
On 2018-04-09 02:06 PM, Harry Wentland wrote:
Signed-off-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Leo (Sunpeng) Li <sunpeng...@amd.com>
---
drivers/gpu/drm/amd/display/include/logger_types.h | 2 +-
1 fil
On 2018-04-09 10:10 AM, Michel Dänzer wrote:
Hi Leo,
apologies for the late follow-up; I was on vacation and then backlogged.
No worries, thanks for the review :)
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
This change adds a few functions in preparation of enabling CRTC color
managment via the randr interface.
The driver-private CRTC obj
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
In cases where CRTC properties are updated without going through
RRChangeOutputProperty, we don't update the properties in user land.
On 2018-04-09 11:03 AM, Michel Dänzer wrote:
On 2018-03-26 10:00 PM, sunpeng...@amd.com wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
The functions insert into the output resource creation, and property
change functions. CRTC destroy is also hooked-up for proper cle
041896] [drm] Un-gated front end for pipe 3
We're aware of this. It's being tracked internally, but we haven't
gotten to it yet. Thanks for finding the commit!
Leo
Cheers,
Tom
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.f
On 2018-04-04 11:17 AM, Deucher, Alexander wrote:
Do other DCE blocks need this fix as well? Or is this code shared with
say DCE8 and DCE10?
Yes, it's all shared. The hook for this is initialized in
dce110_hw_sequencer_construct(), which is called for all DCE.
Leo
Alex
On 04/05/2018 02:07 PM, James Zhu wrote:
Signed-off-by: James Zhu <james@amd.com>
Acked-by: Leo Liu <leo@amd.com>
Regards,
Leo
---
tests/amdgpu/vce_ib.h| 17
tests/amdgpu/vce_tests.c | 221 ++-
2 files
On 04/04/2018 03:17 PM, James Zhu wrote:
On 2018-04-04 02:44 PM, Leo Liu wrote:
On 04/04/2018 12:43 PM, James Zhu wrote:
Signed-off-by: James Zhu<james@amd.com>
---
tests/amdgpu/vce_ib.h| 21 -
tests/amdgpu/vce_tests.c
d)
+{
+ vce_create[11] = 0x0100; /* disableTwoInstance */
As I know with VCE only one instance, it will ignore this. If you think
it matters, you could make this value default, and re-set it with 2
instances case, since we only have limited HW with 2 instances available.
Regards,
On 04/03/2018 03:48 PM, James Zhu wrote:
On 2018-04-03 03:14 PM, Leo Liu wrote:
On 04/03/2018 03:02 PM, James Zhu wrote:
Signed-off-by: James Zhu <james@amd.com>
---
tests/amdgpu/Makefile.am | 1 +
tests/amdgpu/amdgpu_test.c | 11 +
tests/amdgpu/amdgpu_test.h
_TestInfo vce_mv_tests[] = {
+ { "VCE create", amdgpu_cs_vce_create },
+ { "VCE mvdump", amdgpu_cs_vce_encode_mv },
+ { "VCE destroy", amdgpu_cs_vce_destroy },
Why does it need to have a separated file, and many duplicated stuf
Acked-by: Leo Liu <leo@amd.com>
On 03/19/2018 02:26 PM, Alex Deucher wrote:
On Fri, Mar 16, 2018 at 12:07 PM, Alex Deucher <alexdeuc...@gmail.com> wrote:
Need to be able to query the VCN firmware version from
userspace to determine supported features, etc.
Signed-off-by:
Series are:
Reviewed-by: Leo Liu <leo@amd.com>
On 03/06/2018 03:14 PM, James Zhu wrote:
When UVD is in VM mode, there is not uvd handle exchanged,
uvd.handles are always 0. So vcpu_bo always need save,
Otherwise amdgpu driver will fail during suspend/resume.
Bugzilla:
On 2018-02-27 05:34 AM, Michel Dänzer wrote:
On 2018-02-26 09:15 PM, Harry Wentland wrote:
From: "Leo (Sunpeng) Li" <sunpeng...@amd.com>
Non-legacy LUT size should reflect hw capability. Change size from 256
to 4096.
However, X doesn't seem to play with legacy LUTs of such
Reviewed-by: Leo Liu <leo@amd.com>
On 02/07/2018 02:48 PM, Christian König wrote:
We didn't synced the BO after validating it. Also sart to use
amdgpu_bo_create_reserved to simplify things.
Signed-off-by: Christian König <christian.koe...@amd.com>
---
drivers/gpu/dr
On 02/13/2018 08:57 AM, Christian König wrote:
It's always the obvious. Leo any more comments on this?
If not can we get your rb on this patch as well?
Tested-and-Reviewed-by: Leo Liu <leo@amd.com>
Andrey if Leo gives his ok can you commit both? I'm on vacation and
don'
301 - 400 of 462 matches
Mail list logo
