DRM CRTC shaper and 3D LUTs are optional properties, from
our tests, AMD HW doesn't allow 3D LUT when shaper LUT is set to BYPASS
(without user shaper LUT)
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 81 +--
1 file changed, 38 insertions(+), 43
From: Joshua Ashton
Otherwise this is just initialized to 0.
This needs to actually have a value so that compute_curve can work
for PQ EOTF.
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Joshua Ashton
Add predefined transfer function programming. There is no out gamma ROM,
but we can use AMD color modules to program LUT parameters from a
predefined TF and an empty regamma LUT (or power LUT parameters with
predefined TF setup).
Signed-off-by: Joshua Ashton
---
the color space before applying 3D LUT
conversion.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 185 +++---
3 files changed, 174 insertions(+), 24
Decouple steps of post-blending shaper LUT setup and LUT size validation
according to HW caps as a preparation for DRM CRTC shaper LUT support.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 67 ---
1 file changed, 58 insertions(+), 9 deletions
dynamically
acquire 3D LUT resources when we actually use them, so we don't limit
ourselves with the stream count.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
.../gpu/drm/amd/display/amdgpu_dm
properly.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 39
drivers/gpu/drm/amd/display/dc/dc.h | 8 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core
HW allows us to program shaper LUT without 3D LUT settings and it is
also good for testing shaper LUT behavior, therefore, DC driver should
allow acquiring both 3D and shaper LUT, but programing shaper LUT
without 3D LUT (not initialized).
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4
1 file
to introduce 3D LUT programming and better understand each
step, detach atomic regamma programming from the crtc colocr updating
code.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ---
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git
It follows the same path of out_transfer_func for stream updates, since
shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func()
and this function is called in the atomic commit_tail when
update_flags.bits.out_tf is set.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b
From: Joshua Ashton
Blend 1D LUT or a predefined transfer function can be set to linearize
content before blending, so that it's positioned just before blending
planes, and after 3D LUT (non-linear space). Shaper and Blend LUTs are
1D LUTs that sandwich 3D LUT. Drivers should advertize blend
Add property to set predefined transfer function to enable delinearizing
content with or without shaper LUT. Drivers should advertize this
property acoording to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +
drivers/gpu/drm/amd
. The next patches add these 1D LUTs to the plane color mgmt
pipeline.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5
.../amd/display
Shaper 1D LUT delinearizes content before applying 3D LUT so that, it
comes before 3D LUT. It's an optional property and drivers should attach
it according to HW caps.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++
drivers/gpu/drm/amd/amdgpu
ontent, pass in
(203.0 / 80.0).
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.
From: Joshua Ashton
Create driver-private properties (not DRM KMS generic) for plane degamma
LUT (user-blob and its size).
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14
drivers/gpu/drm/amd
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to delinearize
content with or without LUT (using hardcoded curve caps).
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>From amdgpu_dm_plane we can get it for both CRTC and plane color
properties. We are adding new plane properties for AMD driver-private
color mgmt.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_crtc.c| 37 +--
.../amd/display/amdgpu_dm/amdgpu_dm_plan
From: Joshua Ashton
Add predefined transfer function property to DRM CRTC gamma to convert
to wire encoding with or without gamma LUT.
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
Signed-off-by: Joshua Ashton
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22
-by: Melissa Wen
---
drivers/gpu/drm/drm_atomic.c | 1 +
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
include/drm/drm_plane.h | 7 +++
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c0dc5858a723
-generic, by
now, increase max objs to 41.
Signed-off-by: Melissa Wen
---
include/drm/drm_mode_object.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index 912f1e415685..7e4fb7536c6a 100644
--- a/include/drm
Add CRTC 3D LUT for gamma correction using a 3D lookup table. A shaper
lut must be set to shape the content for a non-linear space. That
details should be handled by the driver according to HW color
capabilities.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14
CRTC shaper LUT shapes the content after blending, i.e., de-linearizes
or normalizes space before applying a 3D LUT color correction. In the
next patch, we add CRTC 3D LUT property to DRM color management after
this shaper LUT and before the current CRTC gamma LUT.
Signed-off-by: Melissa Wen
-developed-by: Joshua Ashton
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/Kconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 06b438217c61..c45a8deb1098 100644
From: Harry Wentland
The shaper LUT requires a 10-bit value of the delta between
segments. We were using dc_fixpt_clamp_u0d10() to do that
but it doesn't do what we want it to do. It will preserve
10-bit precision after the decimal point, but that's not
quite what we want. We want 14-bit
From: Harry Wentland
The region and segment calculation was incapable of dealing
with regions of more than 16 segments. We first fix this.
Now that we can support regions up to 256 elements we can
define a better segment distribution for near-linear LUTs
for our maximum of 256 HW-supported
Regards,
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
[1] https://lore.kernel.org/dri-devel/20220619223104.667413-1-m...@igalia.com/
[2] https://lore.kernel.org/amd-gfx/20220906164628.2361811-1-m...@igalia.com/
[3] https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com
evious tests on HW rotation, I don't see glitches when
splitting pipe, the issue only appears on one-pipe setup, but Xaver is
the best person to validate this on KDE environment.
Thanks,
Reviewed-by: Melissa Wen
>
> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2247
> Cc: Melissa Wen
We don't use this function anywhere, therefore, remove it.
Signed-off-by: Melissa Wen
---
.../amd/display/modules/color/color_gamma.c | 86 ---
.../amd/display/modules/color/color_gamma.h | 3 -
2 files changed, 89 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
This function has many conditions and all code style issues (identation,
missing braces, etc.) make reading it really annoying.
Signed-off-by: Melissa Wen
---
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c| 37 ++-
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git
In mod_color_calculate_{degamma/regamma}_params(), a tf variable is
initialized as TRANSFER_FUNCTION_SRGB but tf is only used after tf =
input->tf, therefore, better to just remove this initial value and avoid
misleading interpretations.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/
The function resource_validate_ctx_update_pointer_after_copy() is
declared in resource.h but never defined, therefore, remove its
declaration from headers.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/inc/resource.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers
Rename mapUserRamp to map_user_ramp and doClamping to do_clamping
Signed-off-by: Melissa Wen
---
.../amd/display/modules/color/color_gamma.c | 50 ++-
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
b
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index feb4bb491525..60bb5634b6e2
nused
_calculate_degamma_curve" since this could just be a matter of missing
parts. If so, happy to remove the patch and include a comment describing
the situation (or the potential usage of it).
Thanks,
Melissa
[1] https://lore.kernel.org/dri-devel/20230109143846.1966301-1-m...@igalia.com/
M
On 02/13, Ville Syrjälä wrote:
> On Mon, Feb 13, 2023 at 11:01:31AM +0200, Pekka Paalanen wrote:
> > On Fri, 10 Feb 2023 14:47:50 -0500
> > Harry Wentland wrote:
> >
> > > On 2/10/23 04:28, Pekka Paalanen wrote:
> > > > On Thu, 9 Feb 2023
On 02/10, Pekka Paalanen wrote:
> On Thu, 9 Feb 2023 13:27:02 -0100
> Melissa Wen wrote:
>
> > On 01/31, Pekka Paalanen wrote:
> > > On Mon, 9 Jan 2023 14:38:09 -0100
> > > Melissa Wen wrote:
> > >
> > > > On 01/09, Melissa Wen wrote:
On 01/31, Pekka Paalanen wrote:
> On Mon, 9 Jan 2023 14:38:09 -0100
> Melissa Wen wrote:
>
> > On 01/09, Melissa Wen wrote:
> > > Hi,
> > >
> > > After collecting comments in different places, here is a second version
> > > of the work on addi
Fix glitches when moving cursor close to the edge on a rotated screen
for drivers with one pipe (without pipe split) by halving dst_x_offset.
Reported-by: Xaver Hugl
Signed-off-by: Melissa Wen
---
Hi,
I'm not sure if having dst_x_offset (or only for the one pipe case) is
the right solution
ition on horizontal
mirror")
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_s
;
> - } bits;
> -};
> -
> struct dc_panel_patch {
> unsigned int dppowerup_delay;
> unsigned int extra_t12_ms;
> @@ -219,8 +207,6 @@ struct dc_edid_caps {
> uint32_t audio_latency;
> uint32_t video_latency;
>
> - union display_conte
On 01/17, Joshua Ashton wrote:
> Implements the 'content type' property for HDMI connectors.
> Verified by checking the avi infoframe on a connected TV.
>
> This also simplifies a lot of the code in that area as well, there were
> a lot of temp variables doing very little and unnecessary logic
>
g here to:
Fixes: 40df2f809e8f ("drm/amd/display: color space ycbcr709 support")
Thanks,
Reviewed-by: Melissa Wen
{ COLOR_SPACE_YCBCR709_BLACK_TYPE,
{ 0x, 0x, 0x, 0x1000, 0x, 0x,
0x, 0x0200, 0x, 0x
On 01/16, Melissa Wen wrote:
> On 01/10, Joshua Ashton wrote:
> > Code in get_output_color_space depends on knowing the pixel encoding to
> > determine whether to pick between eg. COLOR_SPACE_SRGB or
> > COLOR_SPACE_YCBCR709 for transparent RGB -> YCbCr 4:4:4 in the dr
stream->output_color_space = get_output_color_space(timing_out);
LGTM.
I see that we were ignoring the updated value of pixel_encoding in the
previous point. Nice catch!
Reviewed-by: Melissa Wen
> }
>
> static void fill_audio_info(struct audio_info *audio_info,
> --
> 2.39.0
>
signature.asc
Description: PGP signature
On 01/09, Melissa Wen wrote:
> Hi,
>
> After collecting comments in different places, here is a second version
> of the work on adding DRM CRTC 3D LUT support to the current DRM color
> mgmt interface. In comparison to previous proposals [1][2][3], here we
> add 3D LUT b
CRTC color management")
dc_acquire_release_mpc_3dlut initializes the bits required to program
3DLUT in DC MPC hw block, that is applied by set_output_transfer_func().
I still need to double check the timing to acquire and release shaper
and 3D LUTs from the resource pool.
Signed-off-by: M
Now, we can use shaper LUT to delinearize and/or normalize the color
space for a more efficient 3D LUT support (so far, only for DRM atomic
color mgmt). If a degamma 1D LUT is passed to linearize the color space,
a custom shaper 1D LUT can be used before applying 3D LUT.
Signed-off-by: Melissa
Decouple steps of shaper LUT setup and LUT size validation according to
HW caps as a preparation for shaper LUT support.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 22 ---
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers
AMD MPC block support 3D LUTs of dimensions 17 and 9, and also bit
depth 12 and 10, therefore, advertise them to the userspace.
Signed-off-by: Melissa Wen
---
.../amd/display/modules/color/color_gamma.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm
It follows the same path of out_transfer_func for stream updates, since
shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func()
and this function is called in the atomic commit_tail when
update_flags.bits.out_tf is set.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display
Enable DRM crtc properties related to 3D LUT resources (shaper LUT, 3D
LUT and 3D LUT modes) if it's supported by DCN HW, that means DCN
families 3.0+
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 25
From: Alex Hung
Add a 3D LUT mode supported by amdgpu driver.
Note: A patchset "IGT tests for pre-blending 3D LUT interfaces" for this
proposal is sent to IGT mailing list.
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/modules/color/color_gamma.h | 12
1 file changed, 12
Acquire and release 3D LUT and shaper LUT every time we create/remove a
new ctx and add/remove stream to/from it. 3D LUT acquire/release can
fail and therefore we should check its availability during atomic check
considering the new context created not the current one.
Signed-off-by: Melissa Wen
properly.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 39
drivers/gpu/drm/amd/display/dc/dc.h | 8 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core
to introduce 3D LUT programming and better understand each
step, detach atomic regamma programming from the crtc colocr updating
code.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ---
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b
oid misunderstandings here.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 32 ++-
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu
oughts.
Thanks,
Melissa
Alex Hung (2):
drm: Add 3D LUT mode and its attributes
drm/amd/display: Define 3D LUT struct for HDR planes
Melissa Wen (16):
drm/drm_color_mgmt: add shaper LUT to color mgmt properties
drm/drm_color_mgmt: add 3D LUT props to DRM color mgmt
drm/drm_color_mgm
, therefore, DRM
CRTC degamma property shouldn't be enabled for DCE drivers.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b
Shaper LUT and 3D LUT programming is done, so make the DRM color
properties available.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
b
It follows the same path of out_transfer_func for stream updates, since
shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func()
and this function is called in the atomic commit_tail when
update_flags.bits.out_tf is set.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display
Now, we can use shaper LUT to delinearize and/or normalize the color
space for a more efficient 3D LUT support (so far, only for DRM atomic
color mgmt). If a degamma 1D LUT is passed to linearize the color space,
a custom shaper 1D LUT can be used before applying 3D LUT.
Signed-off-by: Melissa
t.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 149 +-
.../gpu/drm/amd/display/dc/core/dc_stream.c | 13 ++
4 files changed, 172 insert
to introduce 3D LUT programming and better understand each
step, detach atomic regamma programming from the crtc colocr updating
code.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ---
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git
Shaper LUT is used to shape the contect after blending, i.e.,
de-linearize space before applying 3D LUT color correction. In the next
patch, we are adding 3D LUT property to DRM color mgmt.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/drm_atomic_state_helper.c | 4 +++
drivers/gpu/drm
by the driver according to its color capabilities.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++
drivers/gpu/drm/drm_atomic_uapi.c | 10
drivers/gpu/drm/drm_color_mgmt.c | 58 +++
drivers/gpu/drm/drm_fb_helper.c
Describe some expected behavior of the AMD DM color mgmt programming.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b
oid misunderstandings here.
Signed-off-by: Melissa Wen
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 32 ++-
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu
RFC]
https://lore.kernel.org/amd-gfx/20220619223104.667413-1-m...@igalia.com/
[VA_API]
http://intel.github.io/libva/structVAProcFilterParameterBuffer3DLUT.html
[KMS_pipe_API] https://gitlab.freedesktop.org/pq/color-and-hdr/-/issues/11
Let me know your thoughts.
Thanks in advance,
Melissa
Melissa
On 08/24, Simon Ser wrote:
> This series adds support for DRM_MODE_PAGE_FLIP_ASYNC for atomic
> commits, aka. "immediate flip" (which might result in tearing).
> The feature was only available via the legacy uAPI, however for
> gaming use-cases it may be desirable to enable it via the atomic
>
On 08/17, Mikhail Gavrilov wrote:
> On Mon, Aug 15, 2022 at 3:37 PM Mikhail Gavrilov
> wrote:
> >
> > Thanks, I tested this patch.
> > But with this patch use-after-free problem happening in another place:
>
> Does anyone have an idea why the second use-after-free happened?
> From the trace I
gt; - mutex_unlock(>bo_list->bo_list_mutex);
> + if (r)
> return r;
> - }
>
> r = amdgpu_sync_fence(>job->sync, bo_va->last_pt_update);
> - if (r) {
> - mutex_unlock(>bo_list->bo_list_mutex);
> + if (r)
> return r;
> - }
Nice catch, Maíra!
Reviewed-by: Melissa Wen
> }
>
> r = amdgpu_vm_handle_moved(adev, vm);
> --
> 2.37.2
>
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On 08/14, Maíra Canal wrote:
> Hi Mikhail
>
> Looks like this use-after-free problem was introduced on
> 90af0ca047f3049c4b46e902f432ad6ef1e2ded6. Checking this patch it seems
> like: if amdgpu_cs_vm_handling return r != 0, then it will unlock
> bo_list_mutex inside the function
On 08/05, Simon Ser wrote:
> Hi,
>
> Have you seen [1] and [2]? CC'ing Sean and Hans, it seems like there's
> a disagreement regarding probing early vs. setting the initial value to
> UNKNOWN.
>
> If a driver doesn't fetch EDIDs before exposing them to user-space,
> then there is an amount of
On 08/04, Melissa Wen wrote:
> To set the panel orientation property with quirk, we need the mode size
> provided by EDID. This info is available after EDID is read by
> dc_link_detect()
> and updated by amdgpu_dm_update_connector_after_detect(). The detection
> happens
On 08/08, Hans de Goede wrote:
> Hi,
>
> On 8/5/22 19:34, Simon Ser wrote:
> > Hi,
> >
> > Have you seen [1] and [2]? CC'ing Sean and Hans, it seems like there's
> > a disagreement regarding probing early vs. setting the initial value to
> > UNKNOWN.
>
> At least for the discussions I've been
ientation quirks")
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0d54c1486739..2de
(Tales)
Signed-off-by: Melissa Wen
Reviewed-by: Harry Wentland
Reviewed-by: Tales Aparecida
---
.../gpu/amdgpu/display/display-manager.rst| 9 ++
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 109 +-
2 files changed, 90 insertions(+), 28 deletions(-)
diff --git
AMD GPU display manager (DM) maps DRM pixel blend modes (None,
Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
options. Describe relevant elements and how to set and test them to get
the expected DRM blend mode on DCN hw.
v2:
- add ref tag (Tales)
Signed-off-by: Melissa
/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769
v2:
- fix typos (Tales)
- add MPCC to MPC entry in the glossary
Signed-off-by: Melissa Wen
Reviewed-by: Tales Aparecida
---
.../gpu/amdgpu/display/dc-glossary.rst| 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
typos (Tales)
- describe missing struct parameters (Tales and Siqueira)
Co-developed-by: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Melissa Wen
Reviewed-by: Tales Aparecida
---
.../amdgpu/display/dcn2_cm_drm_current.svg| 1370 +++
.../amdgpu/display
://lore.kernel.org/amd-gfx/7a95d6a4-bc2f-b0e8-83f8-8cc5b7559...@amd.com/
Melissa Wen (4):
Documentation/amdgpu_dm: Add DM color correction documentation
Documentation/amdgpu/display: add DC color caps info
drm/amd/display: add doc entries for MPC blending configuration
Documentation/gpu/amdgpu
On 08/03, Melissa Wen wrote:
> To set the panel orientation property with quirk, we need the mode size
> provided by EDID. This info is available after EDID is read by
> dc_link_detect()
> and updated by amdgpu_dm_update_connector_after_detect(). The detection
> happens
bf390
[2.565304] R13: 000d R14: 55873f7c4cb0 R15: 55873f797820
[2.565306]
[2.565307] ---[ end trace ]---
Fixes: d77de7880e0e0 ("amd/display: enable panel orientation quirks")
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/d
On 07/26, Magali Lemes wrote:
> On 7/25/22 20:38, Melissa Wen wrote:
>
> > On 07/25, Magali Lemes wrote:
> > > On 7/25/22 16:42, André Almeida wrote:
> > > > Hi Magali,
> > > >
> > > > Às 15:15 de 25/07/22, Magali Lemes escreveu:
> &g
On 07/25, Magali Lemes wrote:
> Add missing headers to solve the following warnings from sparse:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.c:656:17:
> warning: symbol 'ddr4_wm_table_gs' was not declared. Should it be static?
>
On 07/25, Magali Lemes wrote:
>
> On 7/25/22 16:42, André Almeida wrote:
> > Hi Magali,
> >
> > Às 15:15 de 25/07/22, Magali Lemes escreveu:
> > > As "dcn3_15_soc" and "dcn3_16_soc" are of type "struct
> > > _vcs_dpi_soc_bounding_box_st", change their types accordingly.
> > >
> > I can see that
On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > AMD GPU display manager (DM) maps DRM pixel blend modes (None,
> > Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
> > options. Describe relevant elements and how
On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
> > to DC color correction entities. Part of this mapping is already
> > documented as code comments and can be con
On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > Describe structs and enums used to set blend mode properties to MPC
> > blocks. Some pieces of information are already available as code
> > comments, and were just formatted.
float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
uses soft float
Therefore, remove the -mno-gnu-attribute flag for dcn301/powerpc and
move FPU-associated code to DML folder.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 6
float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o uses
soft float
Therefore, remove the -mno-gnu-attribute flag for dcn21/powerpc and move
FPU-associated code to DML folder.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 6 -
.../amd
hard float,
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
uses soft float
Therefore, remove the -mno-gnu-attribute flag for dcn30/powerpc and move
FPU-associated code to DML folder.
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 6
Many lines of code in dcn31_resource_construct are wrapped by DC_FP
macro to protect FPU operations; however, there is no FPU in this
region. Therefore, just remove the wrapper for clarity.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 6 --
1 file
/powerpc64-linux-ld: failed to merge
target specific data of file
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o
[1] https://lore.kernel.org/amd-gfx/20220716195144.342960-1-m...@igalia.com/
Reported-by: Guenter Roeck
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc
. This series doesn't cover
recent drivers dcn32/314.
Thanks Guenter, Maíra, Siqueira and Alex for all inputs on this
debugging process. Let me know your thoughts on this approach.
Melissa
[1] https://lore.kernel.org/amd-gfx/20220618232737.2036722-1-li...@roeck-us.net/
Melissa Wen (5):
drm/amd
/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 91 +
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
b/drivers/gpu/drm
301 - 400 of 462 matches
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