the topmost plane is a video plane
(overlay only).
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++-
.../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 22 +++-
.../amd
for dcn30_internal_validate_bw
and created a validate_bw method for DCN314 with the allow_self_refresh_only
flag set to false (to support mem clk switching).
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Nasir Osman
---
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 16 +++---
.../drm
From: Charlene Liu
[Why]
In virtual link use case, link->ddc could be NULL.
[How]
Add null pointer check to avoid undefined behavior.
Reviewed-by: Martin Leung
Reviewed-by: Hansen Dsouza
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
.../amd/display/dc/dcn10/dcn10_hw_sequence
with rotation
configs, hence disabling it.
[how]
Within DML, modified unbounded request mode to be configured only when
the rotation angle of the plane is 0.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Nasir Osman
---
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
From: Nicholas Kazlauskas
[Why]
Request from HW team to update the latencies to the new measured values.
[How]
Update the values in the bounding box.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dml/dcn314
From: Aric Cyr
This version brings along the following:
- Move domain power control to DMCUB for DCN314
- Enable P-state validation check for DCN314
- Add support for multiple overlay planes
- Fixes in prefetch, k1 k2 divider programming and more
- Code cleanup
Acked-by: Qingqing Zhuo
Signed
master pipes for current
link and only toggle DPMS for active master pipes connected to the link.
Add assert in case we get called to program dpms with non master pipe.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Wenjing Liu
---
.../display/dc/link/accessories/link_dp_cts.c | 42
-enabled after the video window is stable.
Reviewed-by: Sun peng Li
Acked-by: Qingqing Zhuo
Signed-off-by: Tom Chung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 ---
drivers/gpu/drm/amd/display/dc/dc_link.h | 1 +
2 files changed, 37 insertions(+), 5 deletions
From: "Leo (Hanghong) Ma"
[Why]
The FreeSync active bit unconditionally set in HDMI VSIF.
[How]
Set this bit to true when FAMS is enable on desktop.
Reviewed-by: Felipe Clark
Acked-by: Qingqing Zhuo
Signed-off-by: Leo (Hanghong) Ma
---
.../gpu/drm/amd/display/modules/freesync/
generic sequence.
Reviewed-by: Jerry Zuo
Acked-by: Qingqing Zhuo
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../gpu/drm/amd/display/dc/link/link_dpms.c | 95 ---
3 files changed
ewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hws
h bw
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
.../dc/dml/dcn32/display_mode_vba_32.c| 9
.../dc/dml/dcn32/display_mode_vba_util_32.c | 21 ++-
.../dc/dml/dcn32/display_mode_vba_util_32.h | 5 -
3 files changed, 29 insertions(+
From: Daniel Miess
This reverts commit 59ce92eba0df932949c7c557868a9b2f379baa5e
[Why]
This commit causes corruption when viewing a P010
video clip on a 300Hz eDP
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Daniel Miess
---
.../dc/clk_mgr/dcn314/dcn314_clk_mgr.c
From: Samson Tam
[Why]
In disable_dangling_plane, for phantom pipes, we enable OTG so
disable programming gets the double buffer update. But this
causes an underflow to occur.
[How]
Enable DPG prior to enabling OTG.
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Samson Tam
some further refactor so the
logic is easier to understand to prevent future coding error in this sequence.
Reviewed-by: Samson Tam
Acked-by: Qingqing Zhuo
Signed-off-by: Wenjing Liu
---
.../gpu/drm/amd/display/dc/link/link_dpms.c | 51 +--
.../display/dc/link/protocols
MPO video cases
- Ensure that global vratio prefetch (i.e. total prefetch BW vs.
total active bandwidth) does not excited 4.0
Reviewed-by: Nevenko Stupar
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 2 ++
.../drm/amd/display/dc/dml
potential display corruption issues.
The command will be ignored on firmware that does not support DOMAIN
power control and the pipes will remain always on - frequent PG cycling
can cause the issue to occur on the old sequence, so we should avoid it.
Reviewed-by: Hansen Dsouza
Acked-by: Qingqing
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Move domain power control to DMCUB for DCN314
- Enable P-state validation check for DCN314
- Add support for multiple overlay planes
- Fixes in prefetch, k1 k2 divider programming and more
- Code cleanup
Cc:
From: Nicholas Kazlauskas
[Why]
To align with DCN31 behavior. This helps avoid p-state hangs in
the case where underflow does occur.
[How]
Flip the bit to true.
Reviewed-by: Hansen Dsouza
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/dcn314
82dca8576d14f3dcb775b3be5f1bbb5df9a682ac
which was incorrectly reverted.
Reviewed-by: Josip Pavic
Acked-by: Qingqing Zhuo
Signed-off-by: Jingwen Zhu
---
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c| 26 ++-
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
From: Aric Cyr
This version brings along the following:
- FW 0.0.153.0
- Code re-organize for dc_link.c
- Bug fixes on rotation, DRR and more
- DCN314 domain power control moved to dmcub
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file
potential display corruption issues.
The command will be ignored on firmware that does not support DOMAIN
power control and the pipes will remain always on - frequent PG cycling
can cause the issue to occur on the old sequence, so we should avoid it.
Reviewed-by: Hansen Dsouza
Acked-by: Qingqing
From: Hans de Goede
Remove CONFI_BACKLIGHT_CLASS_DEVICE ifdef
that was accidently introduced back.
Reviewed-by: Hamza Mahfooz
Acked-by: Qingqing Zhuo
Signed-off-by: Hans de Goede
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
1 file changed, 3
From: Anthony Koo
[Why]
- Reduce reserved size from 9 to 8 dwords to reduce structure size
and allow the union dmub_rb_cmd to fit into max 64-bytes cmd size
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
1
MPO video cases
- Ensure that global vratio prefetch (i.e. total prefetch BW vs.
total active bandwidth) does not excited 4.0
Reviewed-by: Nevenko Stupar
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
.../drm/amd/display/dc/dcn32/dcn32_resource.h | 2 ++
.../drm/amd/display/dc/dml
From: "Leo (Hanghong) Ma"
[Why && How]
Add support to read manufacturer OUI
and device id from HDMI SCDC.
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 17
drivers/gpu/
From: Wesley Chalmers
[WHY]
DRR and Pipe cannot be updated on
the same frame, or else underflow will
occur.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++
drivers/gpu/drm/amd/display/dc
5643f0991d70
[ 42.725361] R13: 0009 R14: 5643f22d0c50 R15: 5643f0a74550
[ 42.732621]
Reviewed-by: Samson Tam
Acked-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 10 ++
1 file changed, 6 insertions(+),
is lower than OTG FP2, no such problems
occur.
[HOW]
If FP2 is being lowered, update the VTG register in lock as normal.
If FP2 is being raised, wait until after OTG unlock, so that OTG FP2 is
raised first, then update VTG.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
From: Wesley Chalmers
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Defer all DPP adjustment requests till optimized_required is false.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Wesley Chalmers
This DC patchset brings improvements in multiple areas. In summary, we have:
- DC 3.2.222
- FW 0.0.153.0
- Code re-organize for dc_link.c
- Bug fixes on rotation, DRR and more
- DCN314 domain power control moved to dmcub
Cc: Daniel Wheeler
---
Alvin Lee (1):
drm/amd/display: Set max vratio
ub
operation when it was unnecessary and causing
the hang issue. This commit drops the unnecessary
dmub code and, consequently, fixes the second display not
lighting up the issue.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 +--
From: Alvin Lee
Watermark calculation was incorrect
due to missing brackets.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
that check.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn10
From: Alvin Lee
pipe_ctx[i] exists even if the pipe is not
in use. If the pipe is not in use it will
always have a null stream, so don't return
false in this case.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/dcn32
From: Rodrigo Siqueira
Some unused macros might mislead developers
during the debug, which can be removed without
any issue. This commit drops some unused references
to SE_COMMON_MASK_SH_LIST_DCN32.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dcn32
From: Aric Cyr
DC version 3.2.207 brings along the following:
- PMFW z-state interface update
- Cursor update refactor
- Fixes to DSC validation, DCFCLK during Freesync, etc.
- Code cleanup
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file
From: Rodrigo Siqueira
In multiple parts of the DCN code, we
write directly to the OTG_V_TOTAL_* registers
in some OPTC functions. Let's avoid it by using
the set_vtotal_min_max.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 18
Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Max Tseng
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 145 ++
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 1 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 1
did not
set it for DCN20, this commit initializes the
set_vtotal_min_max with the DCN10 function.
Acked-by: Qingqing Zhuo
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc
unt in dc_state
correctly reflect that in drm_atomic_state which comes up with correct dsc
decision.
Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic
check")
Reviewed-by: Roman Li
Acked-by: Qingqing Zhuo
Signed-off-by: Fangzhi Zuo
Tested-by: Mark Broadw
From: Dillon Varone
[Why & How]
FCLK pstate allow message should not be
dependent on local "update_fclk".
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 4 ++--
1 file changed
-by: Mustapha Ghaddar
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Meenakshikumar Somasundaram
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 31 +++
drivers/gpu/drm/amd/display/dc/dc.h | 3 ++
drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1
From: Aurabindo Pillai
[Why]
Doing timing sync seqence for phantom pipes
will not go through since they are not fully
programmed like normal pipes. Skip the sequence
on such pipes
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Aurabindo Pillai
---
.../amd/display/dc/dcn10
From: Dmytro Laktyushkin
[Why & How]
Prevents certain configs blocking s0i3
when streams aren't completely removed
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
---
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 9 ++---
1 file change
From: Dillon Varone
[Why & How]
Acquire FCLK DPM levels to properly
construct DML clock limits. Further add
new logic to keep number of indices for
each clock in clk_mgr.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
.../display/dc/clk_mgr/d
From: Jun Lei
[Why & How]
Add a helper to map ODM/MPC/Multi-Plane
resources from DC
Reviewed-by: Nevenko Stupar
Reviewed-by: Chaitanya Dhere
Acked-by: Qingqing Zhuo
Signed-off-by: Jun Lei
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 49 ++-
drivers/gpu/drm
]
Increase HW status waiting time for DISPCLK
frequency divider change and OTG busy status
when disable OTG.
Reviewed-by: Ariel Bernstein
Acked-by: Qingqing Zhuo
Signed-off-by: Vladimir Stempen
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4 ++--
drivers/gpu/drm/amd/display
From: Dillon Varone
[Why?]
Currently phy_pix_clk is used to program DTO's which is incorrect.
[How?]
Use the timing pixel clock to program DTO's correctly.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/link
From: Josip Pavic
[Why & How]
Increase width of some variables to avoid comparing integers of
different widths
Reviewed-by: Alvin Lee
Acked-by: Qingqing Zhuo
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 3 +--
1 file changed, 1 insertion(+
From: Martin Leung
[Why & How]
bug was caused when moving variable from stack to
heap because it was reusable and garbage was left
over, so we need to zero mem
Fixes: 593eef8c1a5e ("drm/amd/display: reduce stack size in dcn32 dml (v2)")
Reviewed-by: Rodrigo Siqueira
Acked-by:
.
Take DCFCLK calculated after Freesync bandwidth
parameters are assigned and bandwidth is
recalculated.
Reviewed-by: Martin Leung
Reviewed-by: Nevenko Stupar
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Vladimir Stempen
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
From: Dillon Varone
This reverts commit 0a1b86a611f14df7a490b827556a4b8c2e31c050.
[Why & How]
The reverted commit creates memory leak and causes issue
upon driver install.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/
This DC patch-set brings improvements in multiple areas. In summary, we
highlight:
- PMFW z-state interface update
- Cursor update refactor
- Fixes to DSC validation, DCFCLK during Freesync, etc.
- Code cleanup
Cc: Daniel Wheeler
---
Alvin Lee (2):
drm/amd/display: Fix watermark
From: Nicholas Kazlauskas
[Why]
Request from PMFW to change the messaging format to specify whether we
support z-state via individual bits.
[How]
Update the args we pass in the support message.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
.../drm
From: Michael Strauss
This reverts commit f07023c8bb2c596af97dea9995d9f5a0140cddd3.
[WHY]
Regressions untentionally caused by change,
reverting until this can be resolved.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core
From: Aric Cyr
This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu
From: Jasdeep Dhillon
[why & how]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN30 to DML, where all FPU code
should locate.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Jasdeep Dhi
ing dpp_inst instead of i
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_
From: Jimmy Kizito
[Why]
Driver needs up to date DPIA HPD status.
[How]
Use HPD query command to get DPIA HPD status.
Reviewed-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3
From: David Galiffi
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 9 ++---
1 file changed, 6 insertions(+
tus in the context
associated with the stream, so let's do that.
The primary, non MPO pipe should not have a NULL plane state.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 ++-
drivers/
or the second eDP in a dual eDP system.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Derek Lai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 20 insertions(+), 3 deletions
From: Alvin Lee
[Why & How]
Code clean up in dc.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 -
2 files changed, 9 insertions(+
bit as well.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements in link training fallback
* Adding individual edp hotplug support
* Fixes in DPIA HPD status, display clock change hang, etc.
* FPU isolation work for DCN30
---
Alvin Lee (1):
drm/amd/display:
bandwidth.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 77 +--
1 file changed, 53 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd
From: Aric Cyr
This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers/gpu
From: Jasdeep Dhillon
[why & how]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN30 to DML, where all FPU code
should locate.
Reviewed-by: Rodrigo Siqueira
Acked-by: Qingqing Zhuo
Signed-off-by: Jasdeep Dhi
From: Michael Strauss
[WHY]
Regressions untentionally caused by change,
reverting until this can be resolved.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Michael Strauss
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 171 +++---
drivers/gpu/drm/amd/display
or the second eDP in a dual eDP system.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Qingqing Zhuo
Signed-off-by: Derek Lai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 21 +--
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
2 files changed, 20 insertions(+), 3 deletions
tus in the context
associated with the stream, so let's do that.
The primary, non MPO pipe should not have a NULL plane state.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 3 ++-
drivers/
bit as well.
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off-by: Paul Hsieh
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
b/drivers/gpu/drm/amd/display/dc/dce
ing dpp_inst instead of i
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_
From: David Galiffi
[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.
Reviewed-by: Martin Leung
Acked-by: Qingqing Zhuo
Signed-off-by: David Galiffi
---
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 9 ++---
1 file changed, 6 insertions(+
From: Alvin Lee
[Why & How]
Code clean up in dc.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 1 -
2 files changed, 9 insertions(+
From: Jimmy Kizito
[Why]
Driver needs up to date DPIA HPD status.
[How]
Use HPD query command to get DPIA HPD status.
Reviewed-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3
bandwidth.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Jimmy Kizito
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 77 +--
1 file changed, 53 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements in link training fallback
* Adding individual edp hotplug support
* Fixes in DPIA HPD status, display clock change hang, etc.
* FPU isolation work for DCN30
---
Alvin Lee (1):
drm/amd/display:
From: Sung Joon Kim
[why]
DML validation fails when we connect two or
more displays with HDR. Need to increase
DRAM BW to make the validation passing.
Following the value from DCN31.
[how]
Change the max DRAM BW DML field to 60%.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off
er size. When it is to
optimize BW, set compbuf size back to maximum possible size.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Duncan Ma
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 12 ++--
.../gpu/drm/amd/disp
From: Dmytro Laktyushkin
[Why & How]
Due to how pmfw fills out the table when dcfclk states are disabled,
using dcfclk based clk table would cause a no read situation.
Revert the change to prevent underflow until a better solution is coded.
Reviewed-by: Charlene Liu
Acked-by: Qingqing
From: Dmytro Laktyushkin
[WHy & How]
Unbounded requesting is unsupported on pipe split modes
and this change prevents us running into such a situation
with wide modes.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Harry Went
From: Anthony Koo
[Why & How]
- Remove tick count definition since it can be different
per HW revision
Acked-by: Qingqing Zhuo
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff -
From: Aric Cyr
This version brings along the following:
- FW promotion to 0.0.94
- Enable seamless boot for DCN301
- Improvements in bandwidth validation
- Fixes in flags update, link encoder assignments, DSC, ODM combine and more
Acked-by: Qingqing Zhuo
Signed-off-by: Aric Cyr
---
drivers
From: Martin Leung
[Why & How]
when changing some code we accidentally
changed else if-> if. reverting that.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Martin Leung
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
1 file changed, 1 insertion(+), 2 de
.
Reviewed-by: Dmytro Laktyushkin
Acked-by: Qingqing Zhuo
Signed-off-by: Danny Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core
From: Yi-Ling Chen
[WHY]
Due to pass the wrong parameter down to the enable_stream_gating(),
it would cause the DSC of the removing stream would not be PG.
[HOW]
To pass the correct parameter down th the enable_stream_gating().
Reviewed-by: Anthony Koo
Acked-by: Qingqing Zhuo
Signed-off
:
ATOM_CONNECTOR_CAP_RECORD_TYPE,
ATOM_CONNECTOR_SPEED_UPTO and
ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE.
Reviewed-by: Jun Lei
Acked-by: Qingqing Zhuo
Signed-off-by: Nevenko Stupar
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd
From: Mikita Lipski
[why/how]
Fixing -Wint-in-bool-context Clang Build Failure
Reviewed-by: Nicholas Choi
Acked-by: Qingqing Zhuo
Signed-off-by: Mikita Lipski
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Sung Joon Kim
[why]
Need to keep track of number of
references to stream pointer.
[how]
Call stream retain/release whenever
necessary in link_enc table assignment
sequence.
Reviewed-by: Aric Cyr
Acked-by: Qingqing Zhuo
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc
From: Zhan Liu
[Why]
Rename function name so it aligns with other resource
function names being used by dcn10.
[How]
Rename function name for consistency.
Reviewed-by: Ahmad Othman
Acked-by: Qingqing Zhuo
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
signments are *not* valid
when committing a state, so as a workaround it needs to be cleared
before passing it back into DC.
Fixes: 1a80a0d88ac5 ("drm/amd/display: Fix dynamic encoder reassignment")
Reviewed-by: Harry Wentland
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
From: "Guo, Bing"
[Why]
OPTC_BYTES_PER_PIXEL calculation for 4:2:2 and 4:2:0 could have error.
[How]
Change to use following formula:
OPTC_DSC_BYTES_PER_PIXEL = ceiling((chunk size * 2^28) / slice width)
Reviewed-by: Wenjing Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Bing Guo
--
- it's a 1:1
mapping.
Fixes: cdaae8371aa9 ("drm/amd/display: Handle GPU reset for DC block")
Reviewed-by: Harry Wentland
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Zhan Liu
[Why]
DCN301 is capable of running seamless boot
if keep_stolen_vga_memory is not set.
[How]
Add a helper to check whether an ASIC can support
seamless boot and set it based on base driver flags.
Reviewed-by: Charlene Liu
Acked-by: Qingqing Zhuo
Signed-off-by: Zhan Liu
interrupts.
Fixes: 81927e2808be ("drm/amd/display: Support for DMUB AUX")
Reviewed-by: Jude Shih
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/a
and
Acked-by: Qingqing Zhuo
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display
From: Charlene Liu
[Why & How]
Per hardware requirements, add a flag to control
z10 enable/disable.
Reviewed-by: Sung joon Kim
Acked-by: Qingqing Zhuo
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 5 +
1 file changed, 5 insertions(+)
diff -
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- DC 3.2.163
- FW promotion to 0.0.94
- Enable seamless boot for DCN301
- Improvements in bandwidth validation
- Fixes in flags update, link encoder assignments, DSC, ODM combine and more
Thank you,
Lillian
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