[PATCH] drm/amd/include: Update df 3.6 mask and shift definition

2018-06-12 Thread Shaoyun Liu
The register field hsas been changed in df 3.6, update to correct setting Change-Id: Id625d7698b610c07081f421537964686f8f0b67c Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PATCH] drm/amdgpu: Fix NULL pointer when load kfd driver with PP block is disabled

2018-05-30 Thread Shaoyun Liu
When PP block is disabled, return a fix value(100M) for mclk and sclk on bare-metal mode. This will cover the emulation mode as well. Change-Id: If34e3517b6cb6f31e898bbe7921485fbddb79fb9 Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 18 +++--- 1 file

[PATCH] drm/amdgpu: Fix NULL pointer when load kfd driver with PP block is disabled

2018-05-30 Thread Shaoyun Liu
Change-Id: If34e3517b6cb6f31e898bbe7921485fbddb79fb9 Signed-off-by: Shaoyun Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index

[PATCH] drm/amdgpu: Always call kfd post reset after reset

2018-04-11 Thread Shaoyun Liu
Even reset failed, kfd post reset need to be called to make lock balance on kfd side Change-Id: I8b6ef29d7527915611be0b96a9cd039bc75bb0a9 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++ 1 file changed, 3 insertions(+), 4 del

[PATCH] drm/amdgpu: Double the timeout count on emulation mode

2018-02-07 Thread Shaoyun Liu
Change-Id: If73d9e5f1f2f998d927f506ca4b7a961db368716 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

[PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

2018-02-06 Thread Shaoyun Liu
Add common smu_soc_asic_init function to emulate the sillicon post sequence Change-Id: I6ff04e1199d1ebdbdb31d0e7e8ca3c240c61ab3a Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile| 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++ d

[PATCH] drm/amdgpu: Avoid get vram info from atom bios on emulation mode

2018-02-06 Thread Shaoyun Liu
Change-Id: I10030e83d63b2c27bfd16b64178e4f07c13addfa Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_

[PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

2018-02-06 Thread Shaoyun Liu
Change-Id: I6ff04e1199d1ebdbdb31d0e7e8ca3c240c61ab3a Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/emu_soc.c | 33 + drivers/gpu/d

[PATCH] drm/amdgpu: Fix none-powerplay issue when load driver on emulation mode

2018-02-06 Thread Shaoyun Liu
On emulation mode , driver will be loaded with powerplay disabled Change-Id: I22c343d990f9a306b033728a1cb560c1e8a4677f Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 8 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/g

[PATCH] drm/amdgpu: Add place holder for soc15 asic init on emulation

2018-02-01 Thread Shaoyun Liu
Change-Id: I6ff04e1199d1ebdbdb31d0e7e8ca3c240c61ab3a Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/emu_soc.c | 34 ++ drivers/gpu/d

[PATCH] drm/amdgpu: Basic emulation support

2018-02-01 Thread Shaoyun Liu
Add amdgpu_emu_mode module parameter to control the emulation mode Avoid vbios operation on emulation since there is no vbios post duirng emulation, use the common hw_init to simulate the post Change-Id: Iba32fa16e735490e7401e471219797b83c6c2a58 Signed-off-by: Shaoyun Liu <shaoyun@amd.

[PATCH] drm/amdgpu: Enable ip block bit mask print out info by default

2018-02-01 Thread Shaoyun Liu
Change-Id: I9f794b9a4cbb3cc929ddc1e4f43d9509ce86d638 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/

[PATCH 2/2] drm/amdgpu: avoid vbios operation on emulation

2018-02-01 Thread Shaoyun Liu
There is no vbios post during emulation, use the common hw_init to simulate the post Change-Id: If363766cdd1d0dee9505c5b390732a35e6b80dee Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 21 +++-- 1 file changed, 19 inse

[PATCH 1/2] drm/amdgpu: Set module parameter for emulation

2018-02-01 Thread Shaoyun Liu
During emulation period, use the directly load for firmware also only enable the GFX , SDMA and necessary common, gmc, ih IP block Signed-off-by: Shaoyun Liu <shaoyun@amd.com> Change-Id: I325910fa06be4060725f404e471cc79daaf343c3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +++

[PATCH] drm/amdgpu: Set the bit of ip_block_mask correspond to the IP block define

2018-02-01 Thread Shaoyun Liu
Change-Id: I4bdc6dbcd82f32416f65e0a38fb9c3cb580684bf Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/

[PATCH] drm/amdgpu: Fix compile break after remove the soc15ip.h

2018-02-01 Thread Shaoyun Liu
Change-Id: I972b6d1e22434d01cdf819a528fc6360afc5a6bd Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/

[PATCH 3/3] drm/amdgpu: reset kfd during amdgpu reset

2018-01-26 Thread Shaoyun Liu
Change-Id: I222f4bb2c9a91c7a4764e6aa706e7d7f2e6d948d Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 19 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 6 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 + 3

[PATCH 2/3] drm/amdkfd: Add gpu reset interface and place holder

2018-01-26 Thread Shaoyun Liu
Change-Id: If0babeaeb5237da6ce4d5c400e7df649cba5a8ac Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 10 ++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/

[PATCH 1/3] drm/amd: Add gpu reset interfaces between amdgpu and amdkfd

2018-01-26 Thread Shaoyun Liu
Change-Id: Id2d38642bec9ea1e5fd471e5b8aff027a08438b0 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/i

[PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

2017-12-01 Thread Shaoyun Liu
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

2017-12-01 Thread Shaoyun Liu
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 19 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

[PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

2017-11-30 Thread Shaoyun Liu
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 228 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +-- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 22 ++-- d

[PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

2017-11-30 Thread Shaoyun Liu
Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 126 ++ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 ++-- 2 files changed, 65 insertions(+), 95 del

[PATCH 4/5] drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic register offset

2017-11-29 Thread Shaoyun Liu
Change-Id: Ibfeb782a67e07c4b0d24b1e1903f860735a307e6 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 25 --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 drivers/gpu/drm/amd/amdgpu/psp_v

[PATCH 5/5] drm/admgpu: Reduce the usage of soc15ip.h

2017-11-29 Thread Shaoyun Liu
Change-Id: I132079eb13264aeab62c9e40c1a351609f15f90e Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 - drivers/gpu/d

[PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

2017-11-29 Thread Shaoyun Liu
Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 259 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c| 13 +- d

[PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

2017-11-29 Thread Shaoyun Liu
Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 --- 2 files changed, 11 insertions(

[PATCH 1/5] drm/amdgpu: Dynamic initialize IP base offset

2017-11-29 Thread Shaoyun Liu
Change-Id: I84217de7c188f8886383500da3c91e488086586b Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 27 ++ drivers/gpu/drm/amd/amdgpu/soc15.c | 10 + drive

[PATCH 1/2] drm/amdgpu: Dynamic initialize IP base offset

2017-11-27 Thread Shaoyun Liu
Change-Id: I84217de7c188f8886383500da3c91e488086586b Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 24 + drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++ drive

[PATCH 2/2] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

2017-11-27 Thread Shaoyun Liu
Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 --- 2 files changed, 11 insertions(

[PATCH 2/3] drm/amdgpu: Dynamic initialize IP base offset

2017-11-27 Thread Shaoyun Liu
Change-Id: I84217de7c188f8886383500da3c91e488086586b Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 24 + drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++ drive

[PATCH 3/3] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

2017-11-27 Thread Shaoyun Liu
Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 21 +++ drivers/gpu/drm/amd/amdgpu/soc15_common.h | 34 --- 2 files changed, 11 insertions(

[PATCH 1/3] drm/amdgpu: Add SOC15 IP offset define file

2017-11-27 Thread Shaoyun Liu
Change-Id: I654d02891b80f3457ddcd80d6a8ea5ace295a89c Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- .../drm/amd/include/asic_reg/vega10/ip_offset_1.h | 1248 1 file changed, 1248 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ip_of

[PATCH] drm/amdgpu: Fix recursive evict/restore worker on a multiple mapped bo

2017-08-04 Thread Shaoyun Liu
with the eviction fence Signed-off-by: Shaoyun Liu <shaoyun@amd.com> Change-Id: I4a7dba32c21cbd5fc77512c0476b8d2b4b6ea155 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/

[PATCH 2/2] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULER

2017-07-19 Thread Shaoyun Liu
Change-Id: I780e276983ba5a3bf077d274c84eb168585c806a Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 5 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/d

[PATCH 1/2] drm/amd: Add mqd as parameter in kfd2kgd.hqd_destroy interface

2017-07-19 Thread Shaoyun Liu
Change-Id: I11522965287622bf577fca2aa5dee2aaf791a77f Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++-- drive

[PATCH 2/2] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULER

2017-07-19 Thread Shaoyun Liu
Change-Id: I780e276983ba5a3bf077d274c84eb168585c806a Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 11 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 2 files changed, 23 insertions(+) diff

[PATCH 1/2] drm/amd: Add mqd as parameter in kfd2kgd.hqd_destroy interface

2017-07-19 Thread Shaoyun Liu
Change-Id: I11522965287622bf577fca2aa5dee2aaf791a77f Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++-- drive

[PATCH 2/3] drm/amdkfd: hqd_destroy interface change from KFD side

2017-07-18 Thread Shaoyun Liu
Change-Id: I5bd514b4357d1082f4e8be3df2a1b37051c9bd9f Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c| 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/d

[PATCH 2/3] drm/amdkfd: hqd_destroy interface change from KFD side

2017-07-18 Thread Shaoyun Liu
Change-Id: I5bd514b4357d1082f4e8be3df2a1b37051c9bd9f Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 2 +- 3 files chan

[PATCH 3/3] drm/amdgpu: Clear active for HIQ in RLC_CP_SCHEDULERS

2017-07-18 Thread Shaoyun Liu
Change-Id: Ibc3ae5ac852405b77908bc26f899fe97bde88d86 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 15 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.

[PATCH 2/2] drm/amdgpu: Invalidate tlb for all hubs on Rocm stack

2017-07-07 Thread Shaoyun Liu
Change-Id: I6e4b07b14d72a2ae51b7436cfddf478e26be417c Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/

[PATCH 1/2] drm/amdgpu: Add invalidate tlb for all hub bit field define

2017-07-07 Thread Shaoyun Liu
Change-Id: I56475b72ac9f9a8e2701c58c5b10e1f2930af7cd Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index 298ef4e..3

[PATCH] drm/amdgpu: NO KIQ usage on nbio hdp flush routine

2017-07-04 Thread Shaoyun Liu
nbio hdp flush routine are called within atomic context. Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register since this register has its own VF copy Change-Id: Ia5e2d409f1ea47c67d9e56859b1902bed1b020c6 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/d

[PATCH 3/3] drm/amdgpu: Use polling for KIQ read/write register

2017-06-30 Thread Shaoyun Liu
Change-Id: I87762bfc9903401ac06892bed10efa1767c15025 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 47 +++- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vir

[PATCH 1/3] drm/amdgpu: Use spin_lock instead of mutex for KIQ

2017-06-30 Thread Shaoyun Liu
KIQ read/write register will be called in atomic context so mutex can not be used Change-Id: Ifa14293b3cdfcf74cd7930a4058154d0a7d7f97c Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +- d

[PATCH 2/3] drm/amdgpu: Add wrap function for fence driver to expose cpu and gpu address

2017-06-30 Thread Shaoyun Liu
Change-Id: I5c6267253bfe5507a8821a482cf378852946 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_

[PATCH] drm/amdgpu: Make KIQ read/write register routine be atomic

2017-06-29 Thread Shaoyun Liu
1. Use spin lock instead of mutex in KIQ 2. Directly write to KIQ fence address instead of using fence_emit() 3. Disable the interrupt for KIQ read/write and use CPU polling Change-Id: Id3693a2878ce1338f55aee3def6e7fc0f6b81996 Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/g

[PATCH] drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usages

2017-05-01 Thread Shaoyun Liu
Firmware used reg set 2 for tlb invalidation. AMDGPU can start from reg set 3 to avoid the conflict. AMDKFD will use the reg set 0 or 1 when necesary. Change-Id: I71c595701f47110df0242d6926607c94bd5644eb Signed-off-by: Shaoyun Liu <shaoyun@amd.com> --- drivers/gpu/drm/amd/amdgpu/gmc_