Currently our debugfs bank selection logic only
supports a single GC instance. This updates the functions
amdgpu_gfx_select_se_sh() and amdgpu_gfx_select_me_pipe_q()
to support a GC instance parameter and ultimately a GC
instance selection via the IOCTL to debugfs.
Signed-off-by: Tom St Denis <tom.stde...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 44 +++++++++++++++------
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 7 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h | 15 ++++++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 ++++++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 ++++++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 18 +++++++--
9 files changed, 98 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 6066aebf491c..3a09028277f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -139,7 +139,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct
file *f,
sh_bank, instance_bank);
} else if (use_ring) {
mutex_lock(&adev->srbm_mutex);
- amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
+ amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid, 0);
}
if (pm_pg_lock)
@@ -172,7 +172,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct
file *f,
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff,
0xffffffff);
mutex_unlock(&adev->grbm_idx_mutex);
} else if (use_ring) {
- amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
+ amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
}
@@ -261,15 +261,15 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f,
char __user *buf, u32 off
return -EINVAL;
}
mutex_lock(&adev->grbm_idx_mutex);
- amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
+ amdgpu_gfx_select_se_sh_instanced(adev, rd->id.grbm.se,
rd->id.grbm.sh,
-
rd->id.grbm.instance);
+
rd->id.grbm.instance, rd->id.gc_instance);
}
if (rd->id.use_srbm) {
mutex_lock(&adev->srbm_mutex);
amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me,
rd->id.srbm.pipe,
-
rd->id.srbm.queue, rd->id.srbm.vmid);
+
rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.gc_instance);
}
if (rd->id.pg_lock)
@@ -295,12 +295,12 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f,
char __user *buf, u32 off
}
end:
if (rd->id.use_grbm) {
- amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff,
0xffffffff);
+ amdgpu_gfx_select_se_sh_instanced(adev, 0xffffffff, 0xffffffff,
0xffffffff, 0);
mutex_unlock(&adev->grbm_idx_mutex);
}
if (rd->id.use_srbm) {
- amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
+ amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
}
@@ -319,17 +319,39 @@ static ssize_t amdgpu_debugfs_regs2_op(struct file *f,
char __user *buf, u32 off
static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd,
unsigned long data)
{
struct amdgpu_debugfs_regs2_data *rd = f->private_data;
+ struct amdgpu_debugfs_regs2_iocdata v1_data;
int r;
+ mutex_lock(&rd->lock);
+
switch (cmd) {
+ case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2:
+ r = copy_from_user(&rd->id, (struct
amdgpu_debugfs_regs2_iocdata_v2 *)data, sizeof rd->id);
+ if (r)
+ return r ? -EINVAL : 0;
+ goto done;
case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
- mutex_lock(&rd->lock);
- r = copy_from_user(&rd->id, (struct
amdgpu_debugfs_regs2_iocdata *)data, sizeof rd->id);
- mutex_unlock(&rd->lock);
- return r ? -EINVAL : 0;
+ r = copy_from_user(&v1_data, (struct
amdgpu_debugfs_regs2_iocdata *)data, sizeof v1_data);
+ if (r)
+ return r ? -EINVAL : 0;
+ goto v1_copy;
default:
return -EINVAL;
}
+
+v1_copy:
+ rd->id.use_srbm = v1_data.use_srbm;
+ rd->id.use_grbm = v1_data.use_grbm;
+ rd->id.pg_lock = v1_data.pg_lock;
+ rd->id.grbm.se = v1_data.grbm.se;
+ rd->id.grbm.sh = v1_data.grbm.sh;
+ rd->id.grbm.instance = v1_data.grbm.instance;
+ rd->id.srbm.me = v1_data.srbm.me;
+ rd->id.srbm.pipe = v1_data.srbm.pipe;
+ rd->id.srbm.queue = v1_data.srbm.queue;
+ rd->id.gc_instance = 0;
+done:
+ mutex_unlock(&rd->lock);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 832b3807f1d6..e6e722a30f08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -216,6 +216,8 @@ struct amdgpu_gfx_funcs {
uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
u32 sh_num, u32 instance);
+ void (*select_se_sh_instanced)(struct amdgpu_device *adev, u32 se_num,
+ u32 sh_num, u32 instance, u32 gc_inst);
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t *dst, int *no_fields);
void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
@@ -225,7 +227,7 @@ struct amdgpu_gfx_funcs {
uint32_t wave, uint32_t start, uint32_t size,
uint32_t *dst);
void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
- u32 queue, u32 vmid);
+ u32 queue, u32 vmid, u32 instance);
void (*init_spm_golden)(struct amdgpu_device *adev);
void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
};
@@ -356,7 +358,8 @@ struct amdgpu_gfx {
#define amdgpu_gfx_get_gpu_clock_counter(adev)
(adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance)
(adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
-#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid)
(adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
+#define amdgpu_gfx_select_se_sh_instanced(adev, se, sh, instance, gc_inst)
(adev)->gfx.funcs->select_se_sh_instanced ?
(adev)->gfx.funcs->select_se_sh_instanced((adev), (se), (sh), (instance),
(gc_inst)) : (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
+#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, instance)
(adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid),
(instance))
#define amdgpu_gfx_init_spm_golden(adev)
(adev)->gfx.funcs->init_spm_golden((adev))
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h
index 919d9d401750..a49519e6a3c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umr.h
@@ -35,17 +35,30 @@ struct amdgpu_debugfs_regs2_iocdata {
} srbm;
};
+struct amdgpu_debugfs_regs2_iocdata_v2 {
+ __u32 use_srbm, use_grbm, pg_lock;
+ struct {
+ __u32 se, sh, instance;
+ } grbm;
+ struct {
+ __u32 me, pipe, queue, vmid;
+ } srbm;
+ u32 gc_instance;
+};
+
/*
* MMIO debugfs state data (per file* handle)
*/
struct amdgpu_debugfs_regs2_data {
struct amdgpu_device *adev;
struct mutex lock;
- struct amdgpu_debugfs_regs2_iocdata id;
+ struct amdgpu_debugfs_regs2_iocdata_v2 id;
};
enum AMDGPU_DEBUGFS_REGS2_CMDS {
AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE=0,
+ AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2,
};
#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20,
AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata)
+#define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20,
AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index af94ac580d3e..e47b51374f95 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3506,6 +3506,8 @@ static void gfx_v10_3_set_power_brake_sequence(struct
amdgpu_device *adev);
static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
uint16_t pasid, uint32_t flush_type,
bool all_hub, uint8_t dst_sel);
+static void gfx_v10_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num, u32 sh_num,
+ u32 instance, u32 gc_inst);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t
queue_mask)
{
@@ -4417,7 +4419,7 @@ static void gfx_v10_0_read_wave_vgprs(struct
amdgpu_device *adev, uint32_t simd,
}
static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 q, u32 vm)
+ u32 me, u32 pipe, u32 q, u32 vm, u32
instance)
{
nv_grbm_select(adev, me, pipe, q, vm);
}
@@ -4441,6 +4443,7 @@ static void gfx_v10_0_update_perfmon_mgcg(struct
amdgpu_device *adev,
static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v10_0_select_se_sh,
+ .select_se_sh_instanced = &gfx_v10_0_select_se_sh_instanced,
.read_wave_data = &gfx_v10_0_read_wave_data,
.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
@@ -4790,8 +4793,8 @@ static int gfx_v10_0_sw_fini(void *handle)
return 0;
}
-static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
- u32 sh_num, u32 instance)
+static void gfx_v10_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num,
+ u32 sh_num, u32 instance, u32 gc_inst)
{
u32 data;
@@ -4814,7 +4817,13 @@ static void gfx_v10_0_select_se_sh(struct amdgpu_device
*adev, u32 se_num,
else
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
- WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
+ WREG32_SOC15(GC, gc_inst, mmGRBM_GFX_INDEX, data);
+}
+
+static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
+ u32 sh_num, u32 instance)
+{
+ gfx_v10_0_select_se_sh_instanced(adev, se_num, sh_num, instance, 0);
}
static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 251109723ab6..d970390be94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -122,6 +122,8 @@ static void gfx_v11_0_set_safe_mode(struct amdgpu_device
*adev);
static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
bool enable);
+static void gfx_v11_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num, u32 sh_num,
+ u32 instance, u32 gc_inst);
static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t
queue_mask)
{
@@ -826,7 +828,7 @@ static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device
*adev, uint32_t simd,
}
static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32
me, u32 pipe, u32 q, u32 vm)
+ u32
me, u32 pipe, u32 q, u32 vm, u32 instance)
{
soc21_grbm_select(adev, me, pipe, q, vm);
}
@@ -834,6 +836,7 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device
*adev,
static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v11_0_select_se_sh,
+ .select_se_sh_instanced = &gfx_v11_0_select_se_sh_instanced,
.read_wave_data = &gfx_v11_0_read_wave_data,
.read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
@@ -1477,8 +1480,8 @@ static int gfx_v11_0_sw_fini(void *handle)
return 0;
}
-static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
- u32 sh_num, u32 instance)
+static void gfx_v11_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num,
+ u32 sh_num, u32 instance, u32 gc_inst)
{
u32 data;
@@ -1501,7 +1504,13 @@ static void gfx_v11_0_select_se_sh(struct amdgpu_device
*adev, u32 se_num,
else
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
- WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
+ WREG32_SOC15(GC, gc_inst, regGRBM_GFX_INDEX, data);
+}
+
+static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
+ u32 sh_num, u32 instance)
+{
+ gfx_v11_0_select_se_sh_instanced(adev, se_num, sh_num, instance, 0);
}
static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 204b246f0e3f..3fc7edd160d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3016,7 +3016,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device
*adev, uint32_t simd,
}
static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 q, u32 vm)
+ u32 me, u32 pipe, u32 q, u32 vm, u32 instance)
{
DRM_INFO("Not implemented\n");
}
@@ -3024,6 +3024,7 @@ static void gfx_v6_0_select_me_pipe_q(struct
amdgpu_device *adev,
static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v6_0_select_se_sh,
+ .select_se_sh_instanced = NULL,
.read_wave_data = &gfx_v6_0_read_wave_data,
.read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
.select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 0f2976507e48..162a64b45472 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4179,7 +4179,7 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device
*adev, uint32_t simd,
}
static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 q, u32 vm)
+ u32 me, u32 pipe, u32 q, u32 vm, u32 instance)
{
cik_srbm_select(adev, me, pipe, q, vm);
}
@@ -4187,6 +4187,7 @@ static void gfx_v7_0_select_me_pipe_q(struct
amdgpu_device *adev,
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v7_0_select_se_sh,
+ .select_se_sh_instanced = NULL,
.read_wave_data = &gfx_v7_0_read_wave_data,
.read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
.select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7f0b18b0d4c4..221fec5234c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3444,7 +3444,7 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device
*adev,
}
static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 q, u32 vm)
+ u32 me, u32 pipe, u32 q, u32 vm, u32 instance)
{
vi_srbm_select(adev, me, pipe, q, vm);
}
@@ -5279,6 +5279,7 @@ static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device
*adev, uint32_t simd,
static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v8_0_select_se_sh,
+ .select_se_sh_instanced = NULL,
.read_wave_data = &gfx_v8_0_read_wave_data,
.read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
.select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 0320be4a5fc6..264213977986 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -761,6 +761,9 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device
*adev,
void *inject_if);
static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
+static void gfx_v9_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num, u32 sh_num,
+ u32 instance, u32 gc_inst);
+
static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
uint64_t queue_mask)
{
@@ -1888,7 +1891,7 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device
*adev, uint32_t simd,
}
static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
- u32 me, u32 pipe, u32 q, u32 vm)
+ u32 me, u32 pipe, u32 q, u32 vm, u32 instance)
{
soc15_grbm_select(adev, me, pipe, q, vm);
}
@@ -1896,6 +1899,7 @@ static void gfx_v9_0_select_me_pipe_q(struct
amdgpu_device *adev,
static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v9_0_select_se_sh,
+ .select_se_sh_instanced = &gfx_v9_0_select_se_sh_instanced,
.read_wave_data = &gfx_v9_0_read_wave_data,
.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
@@ -2274,8 +2278,8 @@ static void gfx_v9_0_tiling_mode_table_init(struct
amdgpu_device *adev)
/* TODO */
}
-void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
- u32 instance)
+static void gfx_v9_0_select_se_sh_instanced(struct amdgpu_device *adev, u32
se_num, u32 sh_num,
+ u32 instance, u32 gc_inst)
{
u32 data;
@@ -2294,7 +2298,13 @@ void gfx_v9_0_select_se_sh(struct amdgpu_device *adev,
u32 se_num, u32 sh_num,
else
data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
- WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
+ WREG32_SOC15_RLC_SHADOW(GC, gc_inst, mmGRBM_GFX_INDEX, data);
+}
+
+void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
+ u32 instance)
+{
+ gfx_v9_0_select_se_sh_instanced(adev, se_num, sh_num, instance, 0);
}
static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
--
2.34.1
