esktop.org
Cc: Deucher, Alexander ; Pelloux-prayer, Pierre-eric
; Huang, Ray ; Tuikov,
Luben
Subject: Re: [PATCH] drm/amdgpu: GFX9, GFX10: GRBM requires 1-cycle delay
Hi Changfeng,
> So how can we deal with the firmware between mec version(402) and mec
> version(421)?
Well of hand I see
: Koenig, Christian
Sent: Monday, October 28, 2019 6:47 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Pelloux-prayer, Pierre-eric
; Huang, Ray ; Tuikov,
Luben
Subject: Re: [PATCH] drm/amdgpu: GFX9, GFX10: GRBM requires 1-cycle delay
Hi Changfeng,
> So how
;
> -----Original Message-----
> From: Koenig, Christian
> Sent: Friday, October 25, 2019 11:54 PM
> To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Pelloux-prayer,
> Pierre-eric ; Huang, Ray
> ; Tuikov, Luben
> Subject: Re: [PATCH] drm/am
On 2019-10-26 08:09, Koenig, Christian wrote:
> Am 26.10.19 um 00:45 schrieb Tuikov, Luben:
>> On 2019-10-25 12:19 p.m., Koenig, Christian wrote:
>>> Am 25.10.19 um 18:05 schrieb Alex Deucher:
On Fri, Oct 25, 2019 at 2:49 AM Koenig, Christian
wrote:
> Am 24.10.19 um 23:16 schrieb
Am 26.10.19 um 00:45 schrieb Tuikov, Luben:
> On 2019-10-25 12:19 p.m., Koenig, Christian wrote:
>> Am 25.10.19 um 18:05 schrieb Alex Deucher:
>>> On Fri, Oct 25, 2019 at 2:49 AM Koenig, Christian
>>> wrote:
Am 24.10.19 um 23:16 schrieb Tuikov, Luben:
> The GRBM interface is now capable
On 2019-10-25 12:19 p.m., Koenig, Christian wrote:
> Am 25.10.19 um 18:05 schrieb Alex Deucher:
>> On Fri, Oct 25, 2019 at 2:49 AM Koenig, Christian
>> wrote:
>>> Am 24.10.19 um 23:16 schrieb Tuikov, Luben:
The GRBM interface is now capable of bursting
1-cycle op per register, a WRITE
Am 25.10.19 um 18:05 schrieb Alex Deucher:
> On Fri, Oct 25, 2019 at 2:49 AM Koenig, Christian
> wrote:
>> Am 24.10.19 um 23:16 schrieb Tuikov, Luben:
>>> The GRBM interface is now capable of bursting
>>> 1-cycle op per register, a WRITE followed by
>>> another WRITE, or a WRITE followed by a
On Fri, Oct 25, 2019 at 2:49 AM Koenig, Christian
wrote:
>
> Am 24.10.19 um 23:16 schrieb Tuikov, Luben:
> > The GRBM interface is now capable of bursting
> > 1-cycle op per register, a WRITE followed by
> > another WRITE, or a WRITE followed by a READ--much
> > faster than previous muti-cycle
Hi Changfeng,
that won't work, you can't add this to
amdgpu_ring_emit_reg_write_reg_wait_helper or break all read triggered
registers (like the semaphore ones).
Additional to that it will never work on GFX9, since the CP firmware
there uses the integrated write/wait command and you can't add
a_v5_0_ring_init_cond_exec,
--
2.17.1
Could someone give some suggestions about it?
BR,
Changfeng.
-Original Message-
From: amd-gfx On Behalf Of Huang, Ray
Sent: Friday, October 25, 2019 5:26 PM
To: Tuikov, Luben
Cc: Deucher, Alexander ; Pelloux-prayer, Pierre-eric
; Koenig, Christ
On Thu, Oct 24, 2019 at 09:16:55PM +, Tuikov, Luben wrote:
> The GRBM interface is now capable of bursting 1-cycle op per register,
> a WRITE followed by another WRITE, or a WRITE followed by a READ--much
> faster than previous muti-cycle per completed-transaction interface.
> This causes a
Am 24.10.19 um 23:16 schrieb Tuikov, Luben:
> The GRBM interface is now capable of bursting
> 1-cycle op per register, a WRITE followed by
> another WRITE, or a WRITE followed by a READ--much
> faster than previous muti-cycle per
> completed-transaction interface. This causes a
> problem, whereby
Inline.
-Original Message-
From: amd-gfx On Behalf Of Tuikov, Luben
Sent: Friday, October 25, 2019 5:17 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Pelloux-prayer, Pierre-eric
; Tuikov, Luben ;
Koenig, Christian
Subject: [PATCH] drm/amdgpu: GFX9, GFX10: GRBM
The GRBM interface is now capable of bursting
1-cycle op per register, a WRITE followed by
another WRITE, or a WRITE followed by a READ--much
faster than previous muti-cycle per
completed-transaction interface. This causes a
problem, whereby status registers requiring a
read/write by hardware,
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