[PATCH 07/19] drm/amd/display: w/a for dcn315 inconsistent smu clock table

[Qingqing Zhuo]

From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>

[Why & How]
w/a for dcn315 inconsistent smu clock.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Acked-by: Qingqing Zhuo <qingqing.z...@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c   | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index a737782b2840..b737cbc468f5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -522,6 +522,11 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
                bw_params->clk_table.entries[i].dcfclk_mhz = 
clock_table->DcfClocks[0];
                bw_params->clk_table.entries[i].wck_ratio = 1;
                i++;
+       } else if (clock_table->NumDcfClkLevelsEnabled != 
clock_table->NumSocClkLevelsEnabled) {
+               bw_params->clk_table.entries[i-1].voltage = 
clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
+               bw_params->clk_table.entries[i-1].socclk_mhz = 
clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
+               bw_params->clk_table.entries[i-1].dispclk_mhz = 
clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
+               bw_params->clk_table.entries[i-1].dppclk_mhz = 
clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
        }
        bw_params->clk_table.num_entries = i;
 
-- 
2.34.1