From: Sung Joon Kim <sungjoon....@amd.com>

[WHY & HOW]
To support higher link rates that sink allows, we need to make
sure driver is ready and perform correct link-training sequence.

Reviewed-by: Wenjing Liu <wenjing....@amd.com>
Acked-by: Alex Hung <alex.h...@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon....@amd.com>
---
 .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c 
b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 107b2cec572d..8f57b344f09e 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -209,6 +209,9 @@ static enum dc_link_rate 
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in
        case 8100000:
                link_rate = LINK_RATE_HIGH3;    // Rate_9 (HBR3)- 8.10 Gbps/Lane
                break;
+       case 10000000:
+               link_rate = LINK_RATE_UHBR10;   // UHBR10 - 10.0 Gbps/Lane
+               break;
        default:
                link_rate = LINK_RATE_UNKNOWN;
                break;
-- 
2.34.1

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