From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Currently the paremeters are extracted as if dml is calculating
using pipes as we pass them in. in reality, dml internally merges
pipes into planes if pipe split is detected.
This change adds reverse logic to dcn20_calculate_dlg_params so
that the global sync parameters can be correctly extracted for
all the pipes when pipe split is enabled.
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Reviewed-by: Charlene Liu <charlene....@amd.com>
Acked-by: Leo Li <sunpeng...@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 229 ++++++++++--------
.../gpu/drm/amd/display/dc/inc/core_types.h | 1 -
2 files changed, 131 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index bbd0c6ac2d8c..be6638cd373d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2436,100 +2436,100 @@ void dcn20_calculate_wm(
int pipe_cnt, i, pipe_idx;
for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count;
i++) {
- if (!context->res_ctx.pipe_ctx[i].stream)
- continue;
-
- pipes[pipe_cnt].clks_cfg.refclk_mhz =
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
- pipes[pipe_cnt].clks_cfg.dispclk_mhz =
context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
-
- if (pipe_split_from[i] < 0) {
- pipes[pipe_cnt].clks_cfg.dppclk_mhz =
-
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
- if
(context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
- pipes[pipe_cnt].pipe.dest.odm_combine =
-
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
- else
- pipes[pipe_cnt].pipe.dest.odm_combine =
0;
- pipe_idx++;
- } else {
- pipes[pipe_cnt].clks_cfg.dppclk_mhz =
-
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
- if
(context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] ==
pipe_split_from[i])
- pipes[pipe_cnt].pipe.dest.odm_combine =
-
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
- else
- pipes[pipe_cnt].pipe.dest.odm_combine =
0;
- }
-
- if (dc->config.forced_clocks) {
- pipes[pipe_cnt].clks_cfg.dispclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
- pipes[pipe_cnt].clks_cfg.dppclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
- }
- if (dc->debug.min_disp_clk_khz >
pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
- pipes[pipe_cnt].clks_cfg.dispclk_mhz =
dc->debug.min_disp_clk_khz / 1000.0;
- if (dc->debug.min_dpp_clk_khz >
pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
- pipes[pipe_cnt].clks_cfg.dppclk_mhz =
dc->debug.min_dpp_clk_khz / 1000.0;
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
- pipe_cnt++;
- }
+ pipes[pipe_cnt].clks_cfg.refclk_mhz =
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
+ pipes[pipe_cnt].clks_cfg.dispclk_mhz =
context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
- if (pipe_cnt != pipe_idx) {
- if (dc->res_pool->funcs->populate_dml_pipes)
- pipe_cnt =
dc->res_pool->funcs->populate_dml_pipes(dc,
- &context->res_ctx, pipes);
+ if (pipe_split_from[i] < 0) {
+ pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
+ if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx]
== pipe_idx)
+ pipes[pipe_cnt].pipe.dest.odm_combine =
+
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
else
- pipe_cnt =
dcn20_populate_dml_pipes_from_context(dc,
- &context->res_ctx, pipes);
+ pipes[pipe_cnt].pipe.dest.odm_combine = 0;
+ pipe_idx++;
+ } else {
+ pipes[pipe_cnt].clks_cfg.dppclk_mhz =
+
context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
+ if
(context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] ==
pipe_split_from[i])
+ pipes[pipe_cnt].pipe.dest.odm_combine =
+
context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_split_from[i]];
+ else
+ pipes[pipe_cnt].pipe.dest.odm_combine = 0;
}
- *out_pipe_cnt = pipe_cnt;
+ if (dc->config.forced_clocks) {
+ pipes[pipe_cnt].clks_cfg.dispclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+ pipes[pipe_cnt].clks_cfg.dppclk_mhz =
context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+ }
+ if (dc->debug.min_disp_clk_khz >
pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
+ pipes[pipe_cnt].clks_cfg.dispclk_mhz =
dc->debug.min_disp_clk_khz / 1000.0;
+ if (dc->debug.min_dpp_clk_khz >
pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
+ pipes[pipe_cnt].clks_cfg.dppclk_mhz =
dc->debug.min_dpp_clk_khz / 1000.0;
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+ pipe_cnt++;
+ }
- /* only pipe 0 is read for voltage and dcf/soc clocks */
- if (vlevel < 1) {
- pipes[0].clks_cfg.voltage = 1;
- pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
- }
- context->bw_ctx.bw.dcn.watermarks.b.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
- if (vlevel < 2) {
- pipes[0].clks_cfg.voltage = 2;
- pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
- }
- context->bw_ctx.bw.dcn.watermarks.c.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
- if (vlevel < 3) {
- pipes[0].clks_cfg.voltage = 3;
- pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
- }
- context->bw_ctx.bw.dcn.watermarks.d.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
- pipes[0].clks_cfg.voltage = vlevel;
- pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
- pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
- context->bw_ctx.bw.dcn.watermarks.a.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
-
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
- context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ if (pipe_cnt != pipe_idx) {
+ if (dc->res_pool->funcs->populate_dml_pipes)
+ pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
+ &context->res_ctx, pipes);
+ else
+ pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
+ &context->res_ctx, pipes);
+ }
+
+ *out_pipe_cnt = pipe_cnt;
+
+ pipes[0].clks_cfg.voltage = vlevel;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
+ /* only pipe 0 is read for voltage and dcf/soc clocks */
+ if (vlevel < 1) {
+ pipes[0].clks_cfg.voltage = 1;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
+ }
+ context->bw_ctx.bw.dcn.watermarks.b.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+ if (vlevel < 2) {
+ pipes[0].clks_cfg.voltage = 2;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+ }
+ context->bw_ctx.bw.dcn.watermarks.c.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+ if (vlevel < 3) {
+ pipes[0].clks_cfg.voltage = 3;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
+ }
+ context->bw_ctx.bw.dcn.watermarks.d.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+ pipes[0].clks_cfg.voltage = vlevel;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+ context->bw_ctx.bw.dcn.watermarks.a.urgent_ns =
get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+ context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns =
get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
}
void dcn20_calculate_dlg_params(
@@ -2538,7 +2538,8 @@ void dcn20_calculate_dlg_params(
int pipe_cnt,
int vlevel)
{
- int i, pipe_idx;
+ int i, j, pipe_idx, pipe_idx_unsplit;
+ bool visited[MAX_PIPES] = { 0 };
/* Writeback MCIF_WB arbitration parameters */
dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -2554,31 +2555,63 @@ void dcn20_calculate_dlg_params(
!=
dm_dram_clock_change_unsupported;
context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+ /*
+ * An artifact of dml pipe split/odm is that pipes get merged back
together for
+ * calculation. Therefore we need to only extract for first pipe in
ascending index order
+ * and copy into the other split half.
+ */
+ for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i <
dc->res_pool->pipe_count; i++) {
+ if (!context->res_ctx.pipe_ctx[i].stream)
+ continue;
+ if (!visited[pipe_idx]) {
+ display_pipe_source_params_st *src =
&pipes[pipe_idx_unsplit].pipe.src;
+ display_pipe_dest_params_st *dst =
&pipes[pipe_idx_unsplit].pipe.dest;
+
+ dst->vstartup_start =
context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
+ dst->vupdate_offset =
context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
+ dst->vupdate_width =
context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
+ dst->vready_offset =
context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
+ /*
+ * j iterates inside pipes array, unlike i which
iterates inside
+ * pipe_ctx array
+ */
+ if (src->is_hsplit)
+ for (j = pipe_idx + 1; j < pipe_cnt; j++) {
+ display_pipe_source_params_st *src_j =
&pipes[j].pipe.src;
+ display_pipe_dest_params_st *dst_j =
&pipes[j].pipe.dest;
+
+ if (src_j->is_hsplit && !visited[j]
+ && src->hsplit_grp ==
src_j->hsplit_grp) {
+ dst_j->vstartup_start =
context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
+ dst_j->vupdate_offset =
context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
+ dst_j->vupdate_width =
context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
+ dst_j->vready_offset =
context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
+ visited[j] = true;
+ }
+ }
+ visited[pipe_idx] = true;
+ pipe_idx_unsplit++;
+ }
+ pipe_idx++;
+ }
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
- pipes[pipe_idx].pipe.dest.vstartup_start =
context->bw_ctx.dml.vba.VStartup[pipe_idx];
- pipes[pipe_idx].pipe.dest.vupdate_offset =
context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
- pipes[pipe_idx].pipe.dest.vupdate_width =
context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
- pipes[pipe_idx].pipe.dest.vready_offset =
context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
if (context->bw_ctx.bw.dcn.clk.dppclk_khz <
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
context->bw_ctx.bw.dcn.clk.dppclk_khz =
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
-
context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
-#endif
+ ASSERT(visited[pipe_idx]);
context->res_ctx.pipe_ctx[i].pipe_dlg_param =
pipes[pipe_idx].pipe.dest;
pipe_idx++;
}
/*save a original dppclock copy*/
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz =
context->bw_ctx.bw.dcn.clk.dppclk_khz;
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz =
context->bw_ctx.bw.dcn.clk.dispclk_khz;
- context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz*1000;
- context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz*1000;
+ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
+ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
bool cstate_en =
context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
!= 2;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 1d66c4b09612..74186cf1c285 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -234,7 +234,6 @@ struct stream_resource {
struct output_pixel_processor *opp;
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
struct display_stream_compressor *dsc;
- int dscclk_khz;
#endif
struct timing_generator *tg;
struct stream_encoder *stream_enc;
--
2.22.0
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